1 /* 2 * Copyright 2013 Red Hat 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 #ifndef VIRTGPU_DRM_H 25 #define VIRTGPU_DRM_H 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 /* Please note that modifications to all structs defined here are 34 * subject to backwards-compatibility constraints. 35 * 36 * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel 37 * compatibility Keep fields aligned to their size 38 */ 39 40 #define DRM_VIRTGPU_MAP 0x01 41 #define DRM_VIRTGPU_EXECBUFFER 0x02 42 #define DRM_VIRTGPU_GETPARAM 0x03 43 #define DRM_VIRTGPU_RESOURCE_CREATE 0x04 44 #define DRM_VIRTGPU_RESOURCE_INFO 0x05 45 #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06 46 #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07 47 #define DRM_VIRTGPU_WAIT 0x08 48 #define DRM_VIRTGPU_GET_CAPS 0x09 49 50 #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01 51 #define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02 52 #define VIRTGPU_EXECBUF_FLAGS (\ 53 VIRTGPU_EXECBUF_FENCE_FD_IN |\ 54 VIRTGPU_EXECBUF_FENCE_FD_OUT |\ 55 0) 56 57 struct drm_virtgpu_map { 58 __u64 offset; /* use for mmap system call */ 59 __u32 handle; 60 __u32 pad; 61 }; 62 63 struct drm_virtgpu_execbuffer { 64 __u32 flags; 65 __u32 size; 66 __u64 command; /* void* */ 67 __u64 bo_handles; 68 __u32 num_bo_handles; 69 __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */ 70 }; 71 72 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ 73 #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */ 74 75 struct drm_virtgpu_getparam { 76 __u64 param; 77 __u64 value; 78 }; 79 80 /* NO_BO flags? NO resource flag? */ 81 /* resource flag for y_0_top */ 82 struct drm_virtgpu_resource_create { 83 __u32 target; 84 __u32 format; 85 __u32 bind; 86 __u32 width; 87 __u32 height; 88 __u32 depth; 89 __u32 array_size; 90 __u32 last_level; 91 __u32 nr_samples; 92 __u32 flags; 93 __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */ 94 __u32 res_handle; /* returned by kernel */ 95 __u32 size; /* validate transfer in the host */ 96 __u32 stride; /* validate transfer in the host */ 97 }; 98 99 struct drm_virtgpu_resource_info { 100 __u32 bo_handle; 101 __u32 res_handle; 102 __u32 size; 103 union { 104 __u32 stride; 105 __u32 strides[4]; /* strides[0] is accessible with stride. */ 106 }; 107 __u32 num_planes; 108 __u32 offsets[4]; 109 __u64 format_modifier; 110 }; 111 112 struct drm_virtgpu_3d_box { 113 __u32 x; 114 __u32 y; 115 __u32 z; 116 __u32 w; 117 __u32 h; 118 __u32 d; 119 }; 120 121 struct drm_virtgpu_3d_transfer_to_host { 122 __u32 bo_handle; 123 struct drm_virtgpu_3d_box box; 124 __u32 level; 125 __u32 offset; 126 }; 127 128 struct drm_virtgpu_3d_transfer_from_host { 129 __u32 bo_handle; 130 struct drm_virtgpu_3d_box box; 131 __u32 level; 132 __u32 offset; 133 }; 134 135 #define VIRTGPU_WAIT_NOWAIT 1 /* like it */ 136 struct drm_virtgpu_3d_wait { 137 __u32 handle; /* 0 is an invalid handle */ 138 __u32 flags; 139 }; 140 141 struct drm_virtgpu_get_caps { 142 __u32 cap_set_id; 143 __u32 cap_set_ver; 144 __u64 addr; 145 __u32 size; 146 __u32 pad; 147 }; 148 149 #define DRM_IOCTL_VIRTGPU_MAP \ 150 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) 151 152 #define DRM_IOCTL_VIRTGPU_EXECBUFFER \ 153 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\ 154 struct drm_virtgpu_execbuffer) 155 156 #define DRM_IOCTL_VIRTGPU_GETPARAM \ 157 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\ 158 struct drm_virtgpu_getparam) 159 160 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \ 161 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \ 162 struct drm_virtgpu_resource_create) 163 164 #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \ 165 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \ 166 struct drm_virtgpu_resource_info) 167 168 #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \ 169 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \ 170 struct drm_virtgpu_3d_transfer_from_host) 171 172 #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \ 173 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \ 174 struct drm_virtgpu_3d_transfer_to_host) 175 176 #define DRM_IOCTL_VIRTGPU_WAIT \ 177 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \ 178 struct drm_virtgpu_3d_wait) 179 180 #define DRM_IOCTL_VIRTGPU_GET_CAPS \ 181 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \ 182 struct drm_virtgpu_get_caps) 183 184 #if defined(__cplusplus) 185 } 186 #endif 187 188 #endif 189