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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Target Register Enum Values                                                *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass MipsMCRegisterClasses[];
17
18namespace Mips {
19enum {
20  NoRegister,
21  AT = 1,
22  DSPCCond = 2,
23  DSPCarry = 3,
24  DSPEFI = 4,
25  DSPOutFlag = 5,
26  DSPPos = 6,
27  DSPSCount = 7,
28  FP = 8,
29  GP = 9,
30  MSAAccess = 10,
31  MSACSR = 11,
32  MSAIR = 12,
33  MSAMap = 13,
34  MSAModify = 14,
35  MSARequest = 15,
36  MSASave = 16,
37  MSAUnmap = 17,
38  PC = 18,
39  RA = 19,
40  SP = 20,
41  ZERO = 21,
42  A0 = 22,
43  A1 = 23,
44  A2 = 24,
45  A3 = 25,
46  AC0 = 26,
47  AC1 = 27,
48  AC2 = 28,
49  AC3 = 29,
50  AT_64 = 30,
51  COP00 = 31,
52  COP01 = 32,
53  COP02 = 33,
54  COP03 = 34,
55  COP04 = 35,
56  COP05 = 36,
57  COP06 = 37,
58  COP07 = 38,
59  COP08 = 39,
60  COP09 = 40,
61  COP20 = 41,
62  COP21 = 42,
63  COP22 = 43,
64  COP23 = 44,
65  COP24 = 45,
66  COP25 = 46,
67  COP26 = 47,
68  COP27 = 48,
69  COP28 = 49,
70  COP29 = 50,
71  COP30 = 51,
72  COP31 = 52,
73  COP32 = 53,
74  COP33 = 54,
75  COP34 = 55,
76  COP35 = 56,
77  COP36 = 57,
78  COP37 = 58,
79  COP38 = 59,
80  COP39 = 60,
81  COP010 = 61,
82  COP011 = 62,
83  COP012 = 63,
84  COP013 = 64,
85  COP014 = 65,
86  COP015 = 66,
87  COP016 = 67,
88  COP017 = 68,
89  COP018 = 69,
90  COP019 = 70,
91  COP020 = 71,
92  COP021 = 72,
93  COP022 = 73,
94  COP023 = 74,
95  COP024 = 75,
96  COP025 = 76,
97  COP026 = 77,
98  COP027 = 78,
99  COP028 = 79,
100  COP029 = 80,
101  COP030 = 81,
102  COP031 = 82,
103  COP210 = 83,
104  COP211 = 84,
105  COP212 = 85,
106  COP213 = 86,
107  COP214 = 87,
108  COP215 = 88,
109  COP216 = 89,
110  COP217 = 90,
111  COP218 = 91,
112  COP219 = 92,
113  COP220 = 93,
114  COP221 = 94,
115  COP222 = 95,
116  COP223 = 96,
117  COP224 = 97,
118  COP225 = 98,
119  COP226 = 99,
120  COP227 = 100,
121  COP228 = 101,
122  COP229 = 102,
123  COP230 = 103,
124  COP231 = 104,
125  COP310 = 105,
126  COP311 = 106,
127  COP312 = 107,
128  COP313 = 108,
129  COP314 = 109,
130  COP315 = 110,
131  COP316 = 111,
132  COP317 = 112,
133  COP318 = 113,
134  COP319 = 114,
135  COP320 = 115,
136  COP321 = 116,
137  COP322 = 117,
138  COP323 = 118,
139  COP324 = 119,
140  COP325 = 120,
141  COP326 = 121,
142  COP327 = 122,
143  COP328 = 123,
144  COP329 = 124,
145  COP330 = 125,
146  COP331 = 126,
147  D0 = 127,
148  D1 = 128,
149  D2 = 129,
150  D3 = 130,
151  D4 = 131,
152  D5 = 132,
153  D6 = 133,
154  D7 = 134,
155  D8 = 135,
156  D9 = 136,
157  D10 = 137,
158  D11 = 138,
159  D12 = 139,
160  D13 = 140,
161  D14 = 141,
162  D15 = 142,
163  DSPOutFlag20 = 143,
164  DSPOutFlag21 = 144,
165  DSPOutFlag22 = 145,
166  DSPOutFlag23 = 146,
167  F0 = 147,
168  F1 = 148,
169  F2 = 149,
170  F3 = 150,
171  F4 = 151,
172  F5 = 152,
173  F6 = 153,
174  F7 = 154,
175  F8 = 155,
176  F9 = 156,
177  F10 = 157,
178  F11 = 158,
179  F12 = 159,
180  F13 = 160,
181  F14 = 161,
182  F15 = 162,
183  F16 = 163,
184  F17 = 164,
185  F18 = 165,
186  F19 = 166,
187  F20 = 167,
188  F21 = 168,
189  F22 = 169,
190  F23 = 170,
191  F24 = 171,
192  F25 = 172,
193  F26 = 173,
194  F27 = 174,
195  F28 = 175,
196  F29 = 176,
197  F30 = 177,
198  F31 = 178,
199  FCC0 = 179,
200  FCC1 = 180,
201  FCC2 = 181,
202  FCC3 = 182,
203  FCC4 = 183,
204  FCC5 = 184,
205  FCC6 = 185,
206  FCC7 = 186,
207  FCR0 = 187,
208  FCR1 = 188,
209  FCR2 = 189,
210  FCR3 = 190,
211  FCR4 = 191,
212  FCR5 = 192,
213  FCR6 = 193,
214  FCR7 = 194,
215  FCR8 = 195,
216  FCR9 = 196,
217  FCR10 = 197,
218  FCR11 = 198,
219  FCR12 = 199,
220  FCR13 = 200,
221  FCR14 = 201,
222  FCR15 = 202,
223  FCR16 = 203,
224  FCR17 = 204,
225  FCR18 = 205,
226  FCR19 = 206,
227  FCR20 = 207,
228  FCR21 = 208,
229  FCR22 = 209,
230  FCR23 = 210,
231  FCR24 = 211,
232  FCR25 = 212,
233  FCR26 = 213,
234  FCR27 = 214,
235  FCR28 = 215,
236  FCR29 = 216,
237  FCR30 = 217,
238  FCR31 = 218,
239  FP_64 = 219,
240  F_HI0 = 220,
241  F_HI1 = 221,
242  F_HI2 = 222,
243  F_HI3 = 223,
244  F_HI4 = 224,
245  F_HI5 = 225,
246  F_HI6 = 226,
247  F_HI7 = 227,
248  F_HI8 = 228,
249  F_HI9 = 229,
250  F_HI10 = 230,
251  F_HI11 = 231,
252  F_HI12 = 232,
253  F_HI13 = 233,
254  F_HI14 = 234,
255  F_HI15 = 235,
256  F_HI16 = 236,
257  F_HI17 = 237,
258  F_HI18 = 238,
259  F_HI19 = 239,
260  F_HI20 = 240,
261  F_HI21 = 241,
262  F_HI22 = 242,
263  F_HI23 = 243,
264  F_HI24 = 244,
265  F_HI25 = 245,
266  F_HI26 = 246,
267  F_HI27 = 247,
268  F_HI28 = 248,
269  F_HI29 = 249,
270  F_HI30 = 250,
271  F_HI31 = 251,
272  GP_64 = 252,
273  HI0 = 253,
274  HI1 = 254,
275  HI2 = 255,
276  HI3 = 256,
277  HWR0 = 257,
278  HWR1 = 258,
279  HWR2 = 259,
280  HWR3 = 260,
281  HWR4 = 261,
282  HWR5 = 262,
283  HWR6 = 263,
284  HWR7 = 264,
285  HWR8 = 265,
286  HWR9 = 266,
287  HWR10 = 267,
288  HWR11 = 268,
289  HWR12 = 269,
290  HWR13 = 270,
291  HWR14 = 271,
292  HWR15 = 272,
293  HWR16 = 273,
294  HWR17 = 274,
295  HWR18 = 275,
296  HWR19 = 276,
297  HWR20 = 277,
298  HWR21 = 278,
299  HWR22 = 279,
300  HWR23 = 280,
301  HWR24 = 281,
302  HWR25 = 282,
303  HWR26 = 283,
304  HWR27 = 284,
305  HWR28 = 285,
306  HWR29 = 286,
307  HWR30 = 287,
308  HWR31 = 288,
309  K0 = 289,
310  K1 = 290,
311  LO0 = 291,
312  LO1 = 292,
313  LO2 = 293,
314  LO3 = 294,
315  MPL0 = 295,
316  MPL1 = 296,
317  MPL2 = 297,
318  P0 = 298,
319  P1 = 299,
320  P2 = 300,
321  RA_64 = 301,
322  S0 = 302,
323  S1 = 303,
324  S2 = 304,
325  S3 = 305,
326  S4 = 306,
327  S5 = 307,
328  S6 = 308,
329  S7 = 309,
330  SP_64 = 310,
331  T0 = 311,
332  T1 = 312,
333  T2 = 313,
334  T3 = 314,
335  T4 = 315,
336  T5 = 316,
337  T6 = 317,
338  T7 = 318,
339  T8 = 319,
340  T9 = 320,
341  V0 = 321,
342  V1 = 322,
343  W0 = 323,
344  W1 = 324,
345  W2 = 325,
346  W3 = 326,
347  W4 = 327,
348  W5 = 328,
349  W6 = 329,
350  W7 = 330,
351  W8 = 331,
352  W9 = 332,
353  W10 = 333,
354  W11 = 334,
355  W12 = 335,
356  W13 = 336,
357  W14 = 337,
358  W15 = 338,
359  W16 = 339,
360  W17 = 340,
361  W18 = 341,
362  W19 = 342,
363  W20 = 343,
364  W21 = 344,
365  W22 = 345,
366  W23 = 346,
367  W24 = 347,
368  W25 = 348,
369  W26 = 349,
370  W27 = 350,
371  W28 = 351,
372  W29 = 352,
373  W30 = 353,
374  W31 = 354,
375  ZERO_64 = 355,
376  A0_64 = 356,
377  A1_64 = 357,
378  A2_64 = 358,
379  A3_64 = 359,
380  AC0_64 = 360,
381  D0_64 = 361,
382  D1_64 = 362,
383  D2_64 = 363,
384  D3_64 = 364,
385  D4_64 = 365,
386  D5_64 = 366,
387  D6_64 = 367,
388  D7_64 = 368,
389  D8_64 = 369,
390  D9_64 = 370,
391  D10_64 = 371,
392  D11_64 = 372,
393  D12_64 = 373,
394  D13_64 = 374,
395  D14_64 = 375,
396  D15_64 = 376,
397  D16_64 = 377,
398  D17_64 = 378,
399  D18_64 = 379,
400  D19_64 = 380,
401  D20_64 = 381,
402  D21_64 = 382,
403  D22_64 = 383,
404  D23_64 = 384,
405  D24_64 = 385,
406  D25_64 = 386,
407  D26_64 = 387,
408  D27_64 = 388,
409  D28_64 = 389,
410  D29_64 = 390,
411  D30_64 = 391,
412  D31_64 = 392,
413  DSPOutFlag16_19 = 393,
414  HI0_64 = 394,
415  K0_64 = 395,
416  K1_64 = 396,
417  LO0_64 = 397,
418  S0_64 = 398,
419  S1_64 = 399,
420  S2_64 = 400,
421  S3_64 = 401,
422  S4_64 = 402,
423  S5_64 = 403,
424  S6_64 = 404,
425  S7_64 = 405,
426  T0_64 = 406,
427  T1_64 = 407,
428  T2_64 = 408,
429  T3_64 = 409,
430  T4_64 = 410,
431  T5_64 = 411,
432  T6_64 = 412,
433  T7_64 = 413,
434  T8_64 = 414,
435  T9_64 = 415,
436  V0_64 = 416,
437  V1_64 = 417,
438  NUM_TARGET_REGS 	// 418
439};
440} // end namespace Mips
441
442// Register classes
443
444namespace Mips {
445enum {
446  MSA128F16RegClassID = 0,
447  MSA128F16_with_sub_64_in_OddSPRegClassID = 1,
448  OddSPRegClassID = 2,
449  CCRRegClassID = 3,
450  COP0RegClassID = 4,
451  COP2RegClassID = 5,
452  COP3RegClassID = 6,
453  DSPRRegClassID = 7,
454  FGR32RegClassID = 8,
455  FGRCCRegClassID = 9,
456  FGRH32RegClassID = 10,
457  GPR32RegClassID = 11,
458  HWRegsRegClassID = 12,
459  GPR32NONZERORegClassID = 13,
460  OddSP_with_sub_hiRegClassID = 14,
461  FGR32_and_OddSPRegClassID = 15,
462  FGRH32_and_OddSPRegClassID = 16,
463  OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 17,
464  CPU16RegsPlusSPRegClassID = 18,
465  CPU16RegsRegClassID = 19,
466  FCCRegClassID = 20,
467  GPRMM16RegClassID = 21,
468  GPRMM16MovePRegClassID = 22,
469  GPRMM16ZeroRegClassID = 23,
470  MSACtrlRegClassID = 24,
471  OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 25,
472  CPU16Regs_and_GPRMM16ZeroRegClassID = 26,
473  GPR32NONZERO_and_GPRMM16MovePRegClassID = 27,
474  CPU16Regs_and_GPRMM16MovePRegClassID = 28,
475  GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 29,
476  HI32DSPRegClassID = 30,
477  LO32DSPRegClassID = 31,
478  GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 32,
479  CPURARegRegClassID = 33,
480  CPUSPRegRegClassID = 34,
481  DSPCCRegClassID = 35,
482  GP32RegClassID = 36,
483  GPR32ZERORegClassID = 37,
484  HI32RegClassID = 38,
485  LO32RegClassID = 39,
486  SP32RegClassID = 40,
487  FGR64RegClassID = 41,
488  GPR64RegClassID = 42,
489  GPR64_with_sub_32_in_GPR32NONZERORegClassID = 43,
490  AFGR64RegClassID = 44,
491  FGR64_and_OddSPRegClassID = 45,
492  GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 46,
493  AFGR64_and_OddSPRegClassID = 47,
494  GPR64_with_sub_32_in_CPU16RegsRegClassID = 48,
495  GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 49,
496  GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 50,
497  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 51,
498  GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 52,
499  ACC64DSPRegClassID = 53,
500  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 54,
501  GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 55,
502  GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 56,
503  OCTEON_MPLRegClassID = 57,
504  OCTEON_PRegClassID = 58,
505  ACC64RegClassID = 59,
506  GP64RegClassID = 60,
507  GPR64_with_sub_32_in_CPURARegRegClassID = 61,
508  GPR64_with_sub_32_in_GPR32ZERORegClassID = 62,
509  HI64RegClassID = 63,
510  LO64RegClassID = 64,
511  SP64RegClassID = 65,
512  MSA128BRegClassID = 66,
513  MSA128DRegClassID = 67,
514  MSA128HRegClassID = 68,
515  MSA128WRegClassID = 69,
516  MSA128B_with_sub_64_in_OddSPRegClassID = 70,
517  MSA128WEvensRegClassID = 71,
518  ACC128RegClassID = 72,
519
520  };
521} // end namespace Mips
522
523
524// Subregister indices
525
526namespace Mips {
527enum {
528  NoSubRegister,
529  sub_32,	// 1
530  sub_64,	// 2
531  sub_dsp16_19,	// 3
532  sub_dsp20,	// 4
533  sub_dsp21,	// 5
534  sub_dsp22,	// 6
535  sub_dsp23,	// 7
536  sub_hi,	// 8
537  sub_lo,	// 9
538  sub_hi_then_sub_32,	// 10
539  sub_32_sub_hi_then_sub_32,	// 11
540  NUM_TARGET_SUBREGS
541};
542} // end namespace Mips
543
544} // end namespace llvm
545
546#endif // GET_REGINFO_ENUM
547
548/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
549|*                                                                            *|
550|* MC Register Information                                                    *|
551|*                                                                            *|
552|* Automatically generated file, do not edit!                                 *|
553|*                                                                            *|
554\*===----------------------------------------------------------------------===*/
555
556
557#ifdef GET_REGINFO_MC_DESC
558#undef GET_REGINFO_MC_DESC
559
560namespace llvm {
561
562extern const MCPhysReg MipsRegDiffLists[] = {
563  /* 0 */ 0, 0,
564  /* 2 */ 4, 1, 1, 1, 1, 0,
565  /* 8 */ 388, 65286, 1, 1, 1, 0,
566  /* 14 */ 20, 1, 0,
567  /* 17 */ 21, 1, 0,
568  /* 20 */ 22, 1, 0,
569  /* 23 */ 23, 1, 0,
570  /* 26 */ 24, 1, 0,
571  /* 29 */ 25, 1, 0,
572  /* 32 */ 26, 1, 0,
573  /* 35 */ 27, 1, 0,
574  /* 38 */ 28, 1, 0,
575  /* 41 */ 29, 1, 0,
576  /* 44 */ 30, 1, 0,
577  /* 47 */ 31, 1, 0,
578  /* 50 */ 32, 1, 0,
579  /* 53 */ 33, 1, 0,
580  /* 56 */ 34, 1, 0,
581  /* 59 */ 35, 1, 0,
582  /* 62 */ 65415, 1, 0,
583  /* 65 */ 65513, 1, 0,
584  /* 68 */ 3, 0,
585  /* 70 */ 4, 0,
586  /* 72 */ 6, 0,
587  /* 74 */ 11, 0,
588  /* 76 */ 12, 0,
589  /* 78 */ 22, 0,
590  /* 80 */ 23, 0,
591  /* 82 */ 29, 0,
592  /* 84 */ 30, 0,
593  /* 86 */ 65308, 72, 0,
594  /* 89 */ 65346, 72, 0,
595  /* 92 */ 38, 65322, 73, 0,
596  /* 96 */ 95, 0,
597  /* 98 */ 96, 0,
598  /* 100 */ 106, 0,
599  /* 102 */ 211, 0,
600  /* 104 */ 243, 0,
601  /* 106 */ 282, 0,
602  /* 108 */ 290, 0,
603  /* 110 */ 334, 0,
604  /* 112 */ 64983, 0,
605  /* 114 */ 65060, 0,
606  /* 116 */ 65148, 0,
607  /* 118 */ 65202, 0,
608  /* 120 */ 65205, 0,
609  /* 122 */ 65246, 0,
610  /* 124 */ 65254, 0,
611  /* 126 */ 65271, 0,
612  /* 128 */ 65293, 0,
613  /* 130 */ 37, 65430, 103, 65395, 65309, 0,
614  /* 136 */ 65325, 0,
615  /* 138 */ 65395, 0,
616  /* 140 */ 65396, 0,
617  /* 142 */ 65397, 0,
618  /* 144 */ 65398, 0,
619  /* 146 */ 65410, 0,
620  /* 148 */ 65415, 0,
621  /* 150 */ 65430, 0,
622  /* 152 */ 65440, 0,
623  /* 154 */ 65441, 0,
624  /* 156 */ 141, 65498, 0,
625  /* 159 */ 65516, 234, 65498, 0,
626  /* 163 */ 65515, 235, 65498, 0,
627  /* 167 */ 65514, 236, 65498, 0,
628  /* 171 */ 65513, 237, 65498, 0,
629  /* 175 */ 65512, 238, 65498, 0,
630  /* 179 */ 65511, 239, 65498, 0,
631  /* 183 */ 65510, 240, 65498, 0,
632  /* 187 */ 65509, 241, 65498, 0,
633  /* 191 */ 65508, 242, 65498, 0,
634  /* 195 */ 65507, 243, 65498, 0,
635  /* 199 */ 65506, 244, 65498, 0,
636  /* 203 */ 65505, 245, 65498, 0,
637  /* 207 */ 65504, 246, 65498, 0,
638  /* 211 */ 65503, 247, 65498, 0,
639  /* 215 */ 65502, 248, 65498, 0,
640  /* 219 */ 65501, 249, 65498, 0,
641  /* 223 */ 65500, 250, 65498, 0,
642  /* 227 */ 265, 65498, 0,
643  /* 230 */ 65271, 371, 65499, 0,
644  /* 234 */ 65309, 368, 65502, 0,
645  /* 238 */ 65507, 0,
646  /* 240 */ 65510, 0,
647  /* 242 */ 65511, 0,
648  /* 244 */ 65512, 0,
649  /* 246 */ 65516, 0,
650  /* 248 */ 65521, 0,
651  /* 250 */ 65522, 0,
652  /* 252 */ 65535, 0,
653};
654
655extern const LaneBitmask MipsLaneMaskLists[] = {
656  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
657  /* 2 */ LaneBitmask(0x00000001), LaneBitmask::getAll(),
658  /* 4 */ LaneBitmask(0x00000002), LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
659  /* 10 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
660};
661
662extern const uint16_t MipsSubRegIdxLists[] = {
663  /* 0 */ 1, 0,
664  /* 2 */ 3, 4, 5, 6, 7, 0,
665  /* 8 */ 2, 9, 8, 0,
666  /* 12 */ 9, 1, 8, 10, 11, 0,
667};
668
669extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = {
670  { 65535, 65535 },
671  { 0, 32 },	// sub_32
672  { 0, 64 },	// sub_64
673  { 16, 4 },	// sub_dsp16_19
674  { 20, 1 },	// sub_dsp20
675  { 21, 1 },	// sub_dsp21
676  { 22, 1 },	// sub_dsp22
677  { 23, 1 },	// sub_dsp23
678  { 32, 32 },	// sub_hi
679  { 0, 32 },	// sub_lo
680  { 32, 32 },	// sub_hi_then_sub_32
681  { 0, 64 },	// sub_32_sub_hi_then_sub_32
682};
683
684extern const char MipsRegStrings[] = {
685  /* 0 */ 'C', 'O', 'P', '0', '0', 0,
686  /* 6 */ 'C', 'O', 'P', '0', '1', '0', 0,
687  /* 13 */ 'C', 'O', 'P', '2', '1', '0', 0,
688  /* 20 */ 'C', 'O', 'P', '3', '1', '0', 0,
689  /* 27 */ 'D', '1', '0', 0,
690  /* 31 */ 'F', '1', '0', 0,
691  /* 35 */ 'F', '_', 'H', 'I', '1', '0', 0,
692  /* 42 */ 'F', 'C', 'R', '1', '0', 0,
693  /* 48 */ 'H', 'W', 'R', '1', '0', 0,
694  /* 54 */ 'W', '1', '0', 0,
695  /* 58 */ 'C', 'O', 'P', '0', '2', '0', 0,
696  /* 65 */ 'C', 'O', 'P', '2', '2', '0', 0,
697  /* 72 */ 'C', 'O', 'P', '3', '2', '0', 0,
698  /* 79 */ 'F', '2', '0', 0,
699  /* 83 */ 'F', '_', 'H', 'I', '2', '0', 0,
700  /* 90 */ 'C', 'O', 'P', '2', '0', 0,
701  /* 96 */ 'F', 'C', 'R', '2', '0', 0,
702  /* 102 */ 'H', 'W', 'R', '2', '0', 0,
703  /* 108 */ 'W', '2', '0', 0,
704  /* 112 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0,
705  /* 125 */ 'C', 'O', 'P', '0', '3', '0', 0,
706  /* 132 */ 'C', 'O', 'P', '2', '3', '0', 0,
707  /* 139 */ 'C', 'O', 'P', '3', '3', '0', 0,
708  /* 146 */ 'F', '3', '0', 0,
709  /* 150 */ 'F', '_', 'H', 'I', '3', '0', 0,
710  /* 157 */ 'C', 'O', 'P', '3', '0', 0,
711  /* 163 */ 'F', 'C', 'R', '3', '0', 0,
712  /* 169 */ 'H', 'W', 'R', '3', '0', 0,
713  /* 175 */ 'W', '3', '0', 0,
714  /* 179 */ 'A', '0', 0,
715  /* 182 */ 'A', 'C', '0', 0,
716  /* 186 */ 'F', 'C', 'C', '0', 0,
717  /* 191 */ 'D', '0', 0,
718  /* 194 */ 'F', '0', 0,
719  /* 197 */ 'F', '_', 'H', 'I', '0', 0,
720  /* 203 */ 'K', '0', 0,
721  /* 206 */ 'M', 'P', 'L', '0', 0,
722  /* 211 */ 'L', 'O', '0', 0,
723  /* 215 */ 'P', '0', 0,
724  /* 218 */ 'F', 'C', 'R', '0', 0,
725  /* 223 */ 'H', 'W', 'R', '0', 0,
726  /* 228 */ 'S', '0', 0,
727  /* 231 */ 'T', '0', 0,
728  /* 234 */ 'V', '0', 0,
729  /* 237 */ 'W', '0', 0,
730  /* 240 */ 'C', 'O', 'P', '0', '1', 0,
731  /* 246 */ 'C', 'O', 'P', '0', '1', '1', 0,
732  /* 253 */ 'C', 'O', 'P', '2', '1', '1', 0,
733  /* 260 */ 'C', 'O', 'P', '3', '1', '1', 0,
734  /* 267 */ 'D', '1', '1', 0,
735  /* 271 */ 'F', '1', '1', 0,
736  /* 275 */ 'F', '_', 'H', 'I', '1', '1', 0,
737  /* 282 */ 'F', 'C', 'R', '1', '1', 0,
738  /* 288 */ 'H', 'W', 'R', '1', '1', 0,
739  /* 294 */ 'W', '1', '1', 0,
740  /* 298 */ 'C', 'O', 'P', '0', '2', '1', 0,
741  /* 305 */ 'C', 'O', 'P', '2', '2', '1', 0,
742  /* 312 */ 'C', 'O', 'P', '3', '2', '1', 0,
743  /* 319 */ 'F', '2', '1', 0,
744  /* 323 */ 'F', '_', 'H', 'I', '2', '1', 0,
745  /* 330 */ 'C', 'O', 'P', '2', '1', 0,
746  /* 336 */ 'F', 'C', 'R', '2', '1', 0,
747  /* 342 */ 'H', 'W', 'R', '2', '1', 0,
748  /* 348 */ 'W', '2', '1', 0,
749  /* 352 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0,
750  /* 365 */ 'C', 'O', 'P', '0', '3', '1', 0,
751  /* 372 */ 'C', 'O', 'P', '2', '3', '1', 0,
752  /* 379 */ 'C', 'O', 'P', '3', '3', '1', 0,
753  /* 386 */ 'F', '3', '1', 0,
754  /* 390 */ 'F', '_', 'H', 'I', '3', '1', 0,
755  /* 397 */ 'C', 'O', 'P', '3', '1', 0,
756  /* 403 */ 'F', 'C', 'R', '3', '1', 0,
757  /* 409 */ 'H', 'W', 'R', '3', '1', 0,
758  /* 415 */ 'W', '3', '1', 0,
759  /* 419 */ 'A', '1', 0,
760  /* 422 */ 'A', 'C', '1', 0,
761  /* 426 */ 'F', 'C', 'C', '1', 0,
762  /* 431 */ 'D', '1', 0,
763  /* 434 */ 'F', '1', 0,
764  /* 437 */ 'F', '_', 'H', 'I', '1', 0,
765  /* 443 */ 'K', '1', 0,
766  /* 446 */ 'M', 'P', 'L', '1', 0,
767  /* 451 */ 'L', 'O', '1', 0,
768  /* 455 */ 'P', '1', 0,
769  /* 458 */ 'F', 'C', 'R', '1', 0,
770  /* 463 */ 'H', 'W', 'R', '1', 0,
771  /* 468 */ 'S', '1', 0,
772  /* 471 */ 'T', '1', 0,
773  /* 474 */ 'V', '1', 0,
774  /* 477 */ 'W', '1', 0,
775  /* 480 */ 'C', 'O', 'P', '0', '2', 0,
776  /* 486 */ 'C', 'O', 'P', '0', '1', '2', 0,
777  /* 493 */ 'C', 'O', 'P', '2', '1', '2', 0,
778  /* 500 */ 'C', 'O', 'P', '3', '1', '2', 0,
779  /* 507 */ 'D', '1', '2', 0,
780  /* 511 */ 'F', '1', '2', 0,
781  /* 515 */ 'F', '_', 'H', 'I', '1', '2', 0,
782  /* 522 */ 'F', 'C', 'R', '1', '2', 0,
783  /* 528 */ 'H', 'W', 'R', '1', '2', 0,
784  /* 534 */ 'W', '1', '2', 0,
785  /* 538 */ 'C', 'O', 'P', '0', '2', '2', 0,
786  /* 545 */ 'C', 'O', 'P', '2', '2', '2', 0,
787  /* 552 */ 'C', 'O', 'P', '3', '2', '2', 0,
788  /* 559 */ 'F', '2', '2', 0,
789  /* 563 */ 'F', '_', 'H', 'I', '2', '2', 0,
790  /* 570 */ 'C', 'O', 'P', '2', '2', 0,
791  /* 576 */ 'F', 'C', 'R', '2', '2', 0,
792  /* 582 */ 'H', 'W', 'R', '2', '2', 0,
793  /* 588 */ 'W', '2', '2', 0,
794  /* 592 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0,
795  /* 605 */ 'C', 'O', 'P', '3', '2', 0,
796  /* 611 */ 'A', '2', 0,
797  /* 614 */ 'A', 'C', '2', 0,
798  /* 618 */ 'F', 'C', 'C', '2', 0,
799  /* 623 */ 'D', '2', 0,
800  /* 626 */ 'F', '2', 0,
801  /* 629 */ 'F', '_', 'H', 'I', '2', 0,
802  /* 635 */ 'M', 'P', 'L', '2', 0,
803  /* 640 */ 'L', 'O', '2', 0,
804  /* 644 */ 'P', '2', 0,
805  /* 647 */ 'F', 'C', 'R', '2', 0,
806  /* 652 */ 'H', 'W', 'R', '2', 0,
807  /* 657 */ 'S', '2', 0,
808  /* 660 */ 'T', '2', 0,
809  /* 663 */ 'W', '2', 0,
810  /* 666 */ 'C', 'O', 'P', '0', '3', 0,
811  /* 672 */ 'C', 'O', 'P', '0', '1', '3', 0,
812  /* 679 */ 'C', 'O', 'P', '2', '1', '3', 0,
813  /* 686 */ 'C', 'O', 'P', '3', '1', '3', 0,
814  /* 693 */ 'D', '1', '3', 0,
815  /* 697 */ 'F', '1', '3', 0,
816  /* 701 */ 'F', '_', 'H', 'I', '1', '3', 0,
817  /* 708 */ 'F', 'C', 'R', '1', '3', 0,
818  /* 714 */ 'H', 'W', 'R', '1', '3', 0,
819  /* 720 */ 'W', '1', '3', 0,
820  /* 724 */ 'C', 'O', 'P', '0', '2', '3', 0,
821  /* 731 */ 'C', 'O', 'P', '2', '2', '3', 0,
822  /* 738 */ 'C', 'O', 'P', '3', '2', '3', 0,
823  /* 745 */ 'F', '2', '3', 0,
824  /* 749 */ 'F', '_', 'H', 'I', '2', '3', 0,
825  /* 756 */ 'C', 'O', 'P', '2', '3', 0,
826  /* 762 */ 'F', 'C', 'R', '2', '3', 0,
827  /* 768 */ 'H', 'W', 'R', '2', '3', 0,
828  /* 774 */ 'W', '2', '3', 0,
829  /* 778 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0,
830  /* 791 */ 'C', 'O', 'P', '3', '3', 0,
831  /* 797 */ 'A', '3', 0,
832  /* 800 */ 'A', 'C', '3', 0,
833  /* 804 */ 'F', 'C', 'C', '3', 0,
834  /* 809 */ 'D', '3', 0,
835  /* 812 */ 'F', '3', 0,
836  /* 815 */ 'F', '_', 'H', 'I', '3', 0,
837  /* 821 */ 'L', 'O', '3', 0,
838  /* 825 */ 'F', 'C', 'R', '3', 0,
839  /* 830 */ 'H', 'W', 'R', '3', 0,
840  /* 835 */ 'S', '3', 0,
841  /* 838 */ 'T', '3', 0,
842  /* 841 */ 'W', '3', 0,
843  /* 844 */ 'C', 'O', 'P', '0', '4', 0,
844  /* 850 */ 'C', 'O', 'P', '0', '1', '4', 0,
845  /* 857 */ 'C', 'O', 'P', '2', '1', '4', 0,
846  /* 864 */ 'C', 'O', 'P', '3', '1', '4', 0,
847  /* 871 */ 'D', '1', '4', 0,
848  /* 875 */ 'F', '1', '4', 0,
849  /* 879 */ 'F', '_', 'H', 'I', '1', '4', 0,
850  /* 886 */ 'F', 'C', 'R', '1', '4', 0,
851  /* 892 */ 'H', 'W', 'R', '1', '4', 0,
852  /* 898 */ 'W', '1', '4', 0,
853  /* 902 */ 'C', 'O', 'P', '0', '2', '4', 0,
854  /* 909 */ 'C', 'O', 'P', '2', '2', '4', 0,
855  /* 916 */ 'C', 'O', 'P', '3', '2', '4', 0,
856  /* 923 */ 'F', '2', '4', 0,
857  /* 927 */ 'F', '_', 'H', 'I', '2', '4', 0,
858  /* 934 */ 'C', 'O', 'P', '2', '4', 0,
859  /* 940 */ 'F', 'C', 'R', '2', '4', 0,
860  /* 946 */ 'H', 'W', 'R', '2', '4', 0,
861  /* 952 */ 'W', '2', '4', 0,
862  /* 956 */ 'C', 'O', 'P', '3', '4', 0,
863  /* 962 */ 'D', '1', '0', '_', '6', '4', 0,
864  /* 969 */ 'D', '2', '0', '_', '6', '4', 0,
865  /* 976 */ 'D', '3', '0', '_', '6', '4', 0,
866  /* 983 */ 'A', '0', '_', '6', '4', 0,
867  /* 989 */ 'A', 'C', '0', '_', '6', '4', 0,
868  /* 996 */ 'D', '0', '_', '6', '4', 0,
869  /* 1002 */ 'H', 'I', '0', '_', '6', '4', 0,
870  /* 1009 */ 'K', '0', '_', '6', '4', 0,
871  /* 1015 */ 'L', 'O', '0', '_', '6', '4', 0,
872  /* 1022 */ 'S', '0', '_', '6', '4', 0,
873  /* 1028 */ 'T', '0', '_', '6', '4', 0,
874  /* 1034 */ 'V', '0', '_', '6', '4', 0,
875  /* 1040 */ 'D', '1', '1', '_', '6', '4', 0,
876  /* 1047 */ 'D', '2', '1', '_', '6', '4', 0,
877  /* 1054 */ 'D', '3', '1', '_', '6', '4', 0,
878  /* 1061 */ 'A', '1', '_', '6', '4', 0,
879  /* 1067 */ 'D', '1', '_', '6', '4', 0,
880  /* 1073 */ 'K', '1', '_', '6', '4', 0,
881  /* 1079 */ 'S', '1', '_', '6', '4', 0,
882  /* 1085 */ 'T', '1', '_', '6', '4', 0,
883  /* 1091 */ 'V', '1', '_', '6', '4', 0,
884  /* 1097 */ 'D', '1', '2', '_', '6', '4', 0,
885  /* 1104 */ 'D', '2', '2', '_', '6', '4', 0,
886  /* 1111 */ 'A', '2', '_', '6', '4', 0,
887  /* 1117 */ 'D', '2', '_', '6', '4', 0,
888  /* 1123 */ 'S', '2', '_', '6', '4', 0,
889  /* 1129 */ 'T', '2', '_', '6', '4', 0,
890  /* 1135 */ 'D', '1', '3', '_', '6', '4', 0,
891  /* 1142 */ 'D', '2', '3', '_', '6', '4', 0,
892  /* 1149 */ 'A', '3', '_', '6', '4', 0,
893  /* 1155 */ 'D', '3', '_', '6', '4', 0,
894  /* 1161 */ 'S', '3', '_', '6', '4', 0,
895  /* 1167 */ 'T', '3', '_', '6', '4', 0,
896  /* 1173 */ 'D', '1', '4', '_', '6', '4', 0,
897  /* 1180 */ 'D', '2', '4', '_', '6', '4', 0,
898  /* 1187 */ 'D', '4', '_', '6', '4', 0,
899  /* 1193 */ 'S', '4', '_', '6', '4', 0,
900  /* 1199 */ 'T', '4', '_', '6', '4', 0,
901  /* 1205 */ 'D', '1', '5', '_', '6', '4', 0,
902  /* 1212 */ 'D', '2', '5', '_', '6', '4', 0,
903  /* 1219 */ 'D', '5', '_', '6', '4', 0,
904  /* 1225 */ 'S', '5', '_', '6', '4', 0,
905  /* 1231 */ 'T', '5', '_', '6', '4', 0,
906  /* 1237 */ 'D', '1', '6', '_', '6', '4', 0,
907  /* 1244 */ 'D', '2', '6', '_', '6', '4', 0,
908  /* 1251 */ 'D', '6', '_', '6', '4', 0,
909  /* 1257 */ 'S', '6', '_', '6', '4', 0,
910  /* 1263 */ 'T', '6', '_', '6', '4', 0,
911  /* 1269 */ 'D', '1', '7', '_', '6', '4', 0,
912  /* 1276 */ 'D', '2', '7', '_', '6', '4', 0,
913  /* 1283 */ 'D', '7', '_', '6', '4', 0,
914  /* 1289 */ 'S', '7', '_', '6', '4', 0,
915  /* 1295 */ 'T', '7', '_', '6', '4', 0,
916  /* 1301 */ 'D', '1', '8', '_', '6', '4', 0,
917  /* 1308 */ 'D', '2', '8', '_', '6', '4', 0,
918  /* 1315 */ 'D', '8', '_', '6', '4', 0,
919  /* 1321 */ 'T', '8', '_', '6', '4', 0,
920  /* 1327 */ 'D', '1', '9', '_', '6', '4', 0,
921  /* 1334 */ 'D', '2', '9', '_', '6', '4', 0,
922  /* 1341 */ 'D', '9', '_', '6', '4', 0,
923  /* 1347 */ 'T', '9', '_', '6', '4', 0,
924  /* 1353 */ 'R', 'A', '_', '6', '4', 0,
925  /* 1359 */ 'Z', 'E', 'R', 'O', '_', '6', '4', 0,
926  /* 1367 */ 'F', 'P', '_', '6', '4', 0,
927  /* 1373 */ 'G', 'P', '_', '6', '4', 0,
928  /* 1379 */ 'S', 'P', '_', '6', '4', 0,
929  /* 1385 */ 'A', 'T', '_', '6', '4', 0,
930  /* 1391 */ 'F', 'C', 'C', '4', 0,
931  /* 1396 */ 'D', '4', 0,
932  /* 1399 */ 'F', '4', 0,
933  /* 1402 */ 'F', '_', 'H', 'I', '4', 0,
934  /* 1408 */ 'F', 'C', 'R', '4', 0,
935  /* 1413 */ 'H', 'W', 'R', '4', 0,
936  /* 1418 */ 'S', '4', 0,
937  /* 1421 */ 'T', '4', 0,
938  /* 1424 */ 'W', '4', 0,
939  /* 1427 */ 'C', 'O', 'P', '0', '5', 0,
940  /* 1433 */ 'C', 'O', 'P', '0', '1', '5', 0,
941  /* 1440 */ 'C', 'O', 'P', '2', '1', '5', 0,
942  /* 1447 */ 'C', 'O', 'P', '3', '1', '5', 0,
943  /* 1454 */ 'D', '1', '5', 0,
944  /* 1458 */ 'F', '1', '5', 0,
945  /* 1462 */ 'F', '_', 'H', 'I', '1', '5', 0,
946  /* 1469 */ 'F', 'C', 'R', '1', '5', 0,
947  /* 1475 */ 'H', 'W', 'R', '1', '5', 0,
948  /* 1481 */ 'W', '1', '5', 0,
949  /* 1485 */ 'C', 'O', 'P', '0', '2', '5', 0,
950  /* 1492 */ 'C', 'O', 'P', '2', '2', '5', 0,
951  /* 1499 */ 'C', 'O', 'P', '3', '2', '5', 0,
952  /* 1506 */ 'F', '2', '5', 0,
953  /* 1510 */ 'F', '_', 'H', 'I', '2', '5', 0,
954  /* 1517 */ 'C', 'O', 'P', '2', '5', 0,
955  /* 1523 */ 'F', 'C', 'R', '2', '5', 0,
956  /* 1529 */ 'H', 'W', 'R', '2', '5', 0,
957  /* 1535 */ 'W', '2', '5', 0,
958  /* 1539 */ 'C', 'O', 'P', '3', '5', 0,
959  /* 1545 */ 'F', 'C', 'C', '5', 0,
960  /* 1550 */ 'D', '5', 0,
961  /* 1553 */ 'F', '5', 0,
962  /* 1556 */ 'F', '_', 'H', 'I', '5', 0,
963  /* 1562 */ 'F', 'C', 'R', '5', 0,
964  /* 1567 */ 'H', 'W', 'R', '5', 0,
965  /* 1572 */ 'S', '5', 0,
966  /* 1575 */ 'T', '5', 0,
967  /* 1578 */ 'W', '5', 0,
968  /* 1581 */ 'C', 'O', 'P', '0', '6', 0,
969  /* 1587 */ 'C', 'O', 'P', '0', '1', '6', 0,
970  /* 1594 */ 'C', 'O', 'P', '2', '1', '6', 0,
971  /* 1601 */ 'C', 'O', 'P', '3', '1', '6', 0,
972  /* 1608 */ 'F', '1', '6', 0,
973  /* 1612 */ 'F', '_', 'H', 'I', '1', '6', 0,
974  /* 1619 */ 'F', 'C', 'R', '1', '6', 0,
975  /* 1625 */ 'H', 'W', 'R', '1', '6', 0,
976  /* 1631 */ 'W', '1', '6', 0,
977  /* 1635 */ 'C', 'O', 'P', '0', '2', '6', 0,
978  /* 1642 */ 'C', 'O', 'P', '2', '2', '6', 0,
979  /* 1649 */ 'C', 'O', 'P', '3', '2', '6', 0,
980  /* 1656 */ 'F', '2', '6', 0,
981  /* 1660 */ 'F', '_', 'H', 'I', '2', '6', 0,
982  /* 1667 */ 'C', 'O', 'P', '2', '6', 0,
983  /* 1673 */ 'F', 'C', 'R', '2', '6', 0,
984  /* 1679 */ 'H', 'W', 'R', '2', '6', 0,
985  /* 1685 */ 'W', '2', '6', 0,
986  /* 1689 */ 'C', 'O', 'P', '3', '6', 0,
987  /* 1695 */ 'F', 'C', 'C', '6', 0,
988  /* 1700 */ 'D', '6', 0,
989  /* 1703 */ 'F', '6', 0,
990  /* 1706 */ 'F', '_', 'H', 'I', '6', 0,
991  /* 1712 */ 'F', 'C', 'R', '6', 0,
992  /* 1717 */ 'H', 'W', 'R', '6', 0,
993  /* 1722 */ 'S', '6', 0,
994  /* 1725 */ 'T', '6', 0,
995  /* 1728 */ 'W', '6', 0,
996  /* 1731 */ 'C', 'O', 'P', '0', '7', 0,
997  /* 1737 */ 'C', 'O', 'P', '0', '1', '7', 0,
998  /* 1744 */ 'C', 'O', 'P', '2', '1', '7', 0,
999  /* 1751 */ 'C', 'O', 'P', '3', '1', '7', 0,
1000  /* 1758 */ 'F', '1', '7', 0,
1001  /* 1762 */ 'F', '_', 'H', 'I', '1', '7', 0,
1002  /* 1769 */ 'F', 'C', 'R', '1', '7', 0,
1003  /* 1775 */ 'H', 'W', 'R', '1', '7', 0,
1004  /* 1781 */ 'W', '1', '7', 0,
1005  /* 1785 */ 'C', 'O', 'P', '0', '2', '7', 0,
1006  /* 1792 */ 'C', 'O', 'P', '2', '2', '7', 0,
1007  /* 1799 */ 'C', 'O', 'P', '3', '2', '7', 0,
1008  /* 1806 */ 'F', '2', '7', 0,
1009  /* 1810 */ 'F', '_', 'H', 'I', '2', '7', 0,
1010  /* 1817 */ 'C', 'O', 'P', '2', '7', 0,
1011  /* 1823 */ 'F', 'C', 'R', '2', '7', 0,
1012  /* 1829 */ 'H', 'W', 'R', '2', '7', 0,
1013  /* 1835 */ 'W', '2', '7', 0,
1014  /* 1839 */ 'C', 'O', 'P', '3', '7', 0,
1015  /* 1845 */ 'F', 'C', 'C', '7', 0,
1016  /* 1850 */ 'D', '7', 0,
1017  /* 1853 */ 'F', '7', 0,
1018  /* 1856 */ 'F', '_', 'H', 'I', '7', 0,
1019  /* 1862 */ 'F', 'C', 'R', '7', 0,
1020  /* 1867 */ 'H', 'W', 'R', '7', 0,
1021  /* 1872 */ 'S', '7', 0,
1022  /* 1875 */ 'T', '7', 0,
1023  /* 1878 */ 'W', '7', 0,
1024  /* 1881 */ 'C', 'O', 'P', '0', '8', 0,
1025  /* 1887 */ 'C', 'O', 'P', '0', '1', '8', 0,
1026  /* 1894 */ 'C', 'O', 'P', '2', '1', '8', 0,
1027  /* 1901 */ 'C', 'O', 'P', '3', '1', '8', 0,
1028  /* 1908 */ 'F', '1', '8', 0,
1029  /* 1912 */ 'F', '_', 'H', 'I', '1', '8', 0,
1030  /* 1919 */ 'F', 'C', 'R', '1', '8', 0,
1031  /* 1925 */ 'H', 'W', 'R', '1', '8', 0,
1032  /* 1931 */ 'W', '1', '8', 0,
1033  /* 1935 */ 'C', 'O', 'P', '0', '2', '8', 0,
1034  /* 1942 */ 'C', 'O', 'P', '2', '2', '8', 0,
1035  /* 1949 */ 'C', 'O', 'P', '3', '2', '8', 0,
1036  /* 1956 */ 'F', '2', '8', 0,
1037  /* 1960 */ 'F', '_', 'H', 'I', '2', '8', 0,
1038  /* 1967 */ 'C', 'O', 'P', '2', '8', 0,
1039  /* 1973 */ 'F', 'C', 'R', '2', '8', 0,
1040  /* 1979 */ 'H', 'W', 'R', '2', '8', 0,
1041  /* 1985 */ 'W', '2', '8', 0,
1042  /* 1989 */ 'C', 'O', 'P', '3', '8', 0,
1043  /* 1995 */ 'D', '8', 0,
1044  /* 1998 */ 'F', '8', 0,
1045  /* 2001 */ 'F', '_', 'H', 'I', '8', 0,
1046  /* 2007 */ 'F', 'C', 'R', '8', 0,
1047  /* 2012 */ 'H', 'W', 'R', '8', 0,
1048  /* 2017 */ 'T', '8', 0,
1049  /* 2020 */ 'W', '8', 0,
1050  /* 2023 */ 'C', 'O', 'P', '0', '9', 0,
1051  /* 2029 */ 'C', 'O', 'P', '0', '1', '9', 0,
1052  /* 2036 */ 'C', 'O', 'P', '2', '1', '9', 0,
1053  /* 2043 */ 'C', 'O', 'P', '3', '1', '9', 0,
1054  /* 2050 */ 'F', '1', '9', 0,
1055  /* 2054 */ 'F', '_', 'H', 'I', '1', '9', 0,
1056  /* 2061 */ 'F', 'C', 'R', '1', '9', 0,
1057  /* 2067 */ 'H', 'W', 'R', '1', '9', 0,
1058  /* 2073 */ 'W', '1', '9', 0,
1059  /* 2077 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0,
1060  /* 2093 */ 'C', 'O', 'P', '0', '2', '9', 0,
1061  /* 2100 */ 'C', 'O', 'P', '2', '2', '9', 0,
1062  /* 2107 */ 'C', 'O', 'P', '3', '2', '9', 0,
1063  /* 2114 */ 'F', '2', '9', 0,
1064  /* 2118 */ 'F', '_', 'H', 'I', '2', '9', 0,
1065  /* 2125 */ 'C', 'O', 'P', '2', '9', 0,
1066  /* 2131 */ 'F', 'C', 'R', '2', '9', 0,
1067  /* 2137 */ 'H', 'W', 'R', '2', '9', 0,
1068  /* 2143 */ 'W', '2', '9', 0,
1069  /* 2147 */ 'C', 'O', 'P', '3', '9', 0,
1070  /* 2153 */ 'D', '9', 0,
1071  /* 2156 */ 'F', '9', 0,
1072  /* 2159 */ 'F', '_', 'H', 'I', '9', 0,
1073  /* 2165 */ 'F', 'C', 'R', '9', 0,
1074  /* 2170 */ 'H', 'W', 'R', '9', 0,
1075  /* 2175 */ 'T', '9', 0,
1076  /* 2178 */ 'W', '9', 0,
1077  /* 2181 */ 'R', 'A', 0,
1078  /* 2184 */ 'P', 'C', 0,
1079  /* 2187 */ 'D', 'S', 'P', 'E', 'F', 'I', 0,
1080  /* 2194 */ 'Z', 'E', 'R', 'O', 0,
1081  /* 2199 */ 'F', 'P', 0,
1082  /* 2202 */ 'G', 'P', 0,
1083  /* 2205 */ 'S', 'P', 0,
1084  /* 2208 */ 'M', 'S', 'A', 'I', 'R', 0,
1085  /* 2214 */ 'M', 'S', 'A', 'C', 'S', 'R', 0,
1086  /* 2221 */ 'A', 'T', 0,
1087  /* 2224 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0,
1088  /* 2233 */ 'M', 'S', 'A', 'S', 'a', 'v', 'e', 0,
1089  /* 2241 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0,
1090  /* 2252 */ 'M', 'S', 'A', 'M', 'a', 'p', 0,
1091  /* 2259 */ 'M', 'S', 'A', 'U', 'n', 'm', 'a', 'p', 0,
1092  /* 2268 */ 'D', 'S', 'P', 'P', 'o', 's', 0,
1093  /* 2275 */ 'M', 'S', 'A', 'A', 'c', 'c', 'e', 's', 's', 0,
1094  /* 2285 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0,
1095  /* 2295 */ 'M', 'S', 'A', 'R', 'e', 'q', 'u', 'e', 's', 't', 0,
1096  /* 2306 */ 'M', 'S', 'A', 'M', 'o', 'd', 'i', 'f', 'y', 0,
1097  /* 2316 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0,
1098};
1099
1100extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors
1101  { 5, 0, 0, 0, 0, 0 },
1102  { 2221, 1, 82, 1, 4033, 0 },
1103  { 2224, 1, 1, 1, 4033, 0 },
1104  { 2316, 1, 1, 1, 4033, 0 },
1105  { 2187, 1, 1, 1, 4033, 0 },
1106  { 2241, 8, 1, 2, 32, 4 },
1107  { 2268, 1, 1, 1, 1089, 0 },
1108  { 2285, 1, 1, 1, 1089, 0 },
1109  { 2199, 1, 102, 1, 1089, 0 },
1110  { 2202, 1, 104, 1, 1089, 0 },
1111  { 2275, 1, 1, 1, 1089, 0 },
1112  { 2214, 1, 1, 1, 1089, 0 },
1113  { 2208, 1, 1, 1, 1089, 0 },
1114  { 2252, 1, 1, 1, 1089, 0 },
1115  { 2306, 1, 1, 1, 1089, 0 },
1116  { 2295, 1, 1, 1, 1089, 0 },
1117  { 2233, 1, 1, 1, 1089, 0 },
1118  { 2259, 1, 1, 1, 1089, 0 },
1119  { 2184, 1, 1, 1, 1089, 0 },
1120  { 2181, 1, 106, 1, 1089, 0 },
1121  { 2205, 1, 108, 1, 1089, 0 },
1122  { 2194, 1, 110, 1, 1089, 0 },
1123  { 179, 1, 110, 1, 1089, 0 },
1124  { 419, 1, 110, 1, 1089, 0 },
1125  { 611, 1, 110, 1, 1089, 0 },
1126  { 797, 1, 110, 1, 1089, 0 },
1127  { 182, 227, 110, 9, 1042, 10 },
1128  { 422, 227, 1, 9, 1042, 10 },
1129  { 614, 227, 1, 9, 1042, 10 },
1130  { 800, 227, 1, 9, 1042, 10 },
1131  { 1385, 238, 1, 0, 0, 2 },
1132  { 0, 1, 1, 1, 1153, 0 },
1133  { 240, 1, 1, 1, 1153, 0 },
1134  { 480, 1, 1, 1, 1153, 0 },
1135  { 666, 1, 1, 1, 1153, 0 },
1136  { 844, 1, 1, 1, 1153, 0 },
1137  { 1427, 1, 1, 1, 1153, 0 },
1138  { 1581, 1, 1, 1, 1153, 0 },
1139  { 1731, 1, 1, 1, 1153, 0 },
1140  { 1881, 1, 1, 1, 1153, 0 },
1141  { 2023, 1, 1, 1, 1153, 0 },
1142  { 90, 1, 1, 1, 1153, 0 },
1143  { 330, 1, 1, 1, 1153, 0 },
1144  { 570, 1, 1, 1, 1153, 0 },
1145  { 756, 1, 1, 1, 1153, 0 },
1146  { 934, 1, 1, 1, 1153, 0 },
1147  { 1517, 1, 1, 1, 1153, 0 },
1148  { 1667, 1, 1, 1, 1153, 0 },
1149  { 1817, 1, 1, 1, 1153, 0 },
1150  { 1967, 1, 1, 1, 1153, 0 },
1151  { 2125, 1, 1, 1, 1153, 0 },
1152  { 157, 1, 1, 1, 1153, 0 },
1153  { 397, 1, 1, 1, 1153, 0 },
1154  { 605, 1, 1, 1, 1153, 0 },
1155  { 791, 1, 1, 1, 1153, 0 },
1156  { 956, 1, 1, 1, 1153, 0 },
1157  { 1539, 1, 1, 1, 1153, 0 },
1158  { 1689, 1, 1, 1, 1153, 0 },
1159  { 1839, 1, 1, 1, 1153, 0 },
1160  { 1989, 1, 1, 1, 1153, 0 },
1161  { 2147, 1, 1, 1, 1153, 0 },
1162  { 6, 1, 1, 1, 1153, 0 },
1163  { 246, 1, 1, 1, 1153, 0 },
1164  { 486, 1, 1, 1, 1153, 0 },
1165  { 672, 1, 1, 1, 1153, 0 },
1166  { 850, 1, 1, 1, 1153, 0 },
1167  { 1433, 1, 1, 1, 1153, 0 },
1168  { 1587, 1, 1, 1, 1153, 0 },
1169  { 1737, 1, 1, 1, 1153, 0 },
1170  { 1887, 1, 1, 1, 1153, 0 },
1171  { 2029, 1, 1, 1, 1153, 0 },
1172  { 58, 1, 1, 1, 1153, 0 },
1173  { 298, 1, 1, 1, 1153, 0 },
1174  { 538, 1, 1, 1, 1153, 0 },
1175  { 724, 1, 1, 1, 1153, 0 },
1176  { 902, 1, 1, 1, 1153, 0 },
1177  { 1485, 1, 1, 1, 1153, 0 },
1178  { 1635, 1, 1, 1, 1153, 0 },
1179  { 1785, 1, 1, 1, 1153, 0 },
1180  { 1935, 1, 1, 1, 1153, 0 },
1181  { 2093, 1, 1, 1, 1153, 0 },
1182  { 125, 1, 1, 1, 1153, 0 },
1183  { 365, 1, 1, 1, 1153, 0 },
1184  { 13, 1, 1, 1, 1153, 0 },
1185  { 253, 1, 1, 1, 1153, 0 },
1186  { 493, 1, 1, 1, 1153, 0 },
1187  { 679, 1, 1, 1, 1153, 0 },
1188  { 857, 1, 1, 1, 1153, 0 },
1189  { 1440, 1, 1, 1, 1153, 0 },
1190  { 1594, 1, 1, 1, 1153, 0 },
1191  { 1744, 1, 1, 1, 1153, 0 },
1192  { 1894, 1, 1, 1, 1153, 0 },
1193  { 2036, 1, 1, 1, 1153, 0 },
1194  { 65, 1, 1, 1, 1153, 0 },
1195  { 305, 1, 1, 1, 1153, 0 },
1196  { 545, 1, 1, 1, 1153, 0 },
1197  { 731, 1, 1, 1, 1153, 0 },
1198  { 909, 1, 1, 1, 1153, 0 },
1199  { 1492, 1, 1, 1, 1153, 0 },
1200  { 1642, 1, 1, 1, 1153, 0 },
1201  { 1792, 1, 1, 1, 1153, 0 },
1202  { 1942, 1, 1, 1, 1153, 0 },
1203  { 2100, 1, 1, 1, 1153, 0 },
1204  { 132, 1, 1, 1, 1153, 0 },
1205  { 372, 1, 1, 1, 1153, 0 },
1206  { 20, 1, 1, 1, 1153, 0 },
1207  { 260, 1, 1, 1, 1153, 0 },
1208  { 500, 1, 1, 1, 1153, 0 },
1209  { 686, 1, 1, 1, 1153, 0 },
1210  { 864, 1, 1, 1, 1153, 0 },
1211  { 1447, 1, 1, 1, 1153, 0 },
1212  { 1601, 1, 1, 1, 1153, 0 },
1213  { 1751, 1, 1, 1, 1153, 0 },
1214  { 1901, 1, 1, 1, 1153, 0 },
1215  { 2043, 1, 1, 1, 1153, 0 },
1216  { 72, 1, 1, 1, 1153, 0 },
1217  { 312, 1, 1, 1, 1153, 0 },
1218  { 552, 1, 1, 1, 1153, 0 },
1219  { 738, 1, 1, 1, 1153, 0 },
1220  { 916, 1, 1, 1, 1153, 0 },
1221  { 1499, 1, 1, 1, 1153, 0 },
1222  { 1649, 1, 1, 1, 1153, 0 },
1223  { 1799, 1, 1, 1, 1153, 0 },
1224  { 1949, 1, 1, 1, 1153, 0 },
1225  { 2107, 1, 1, 1, 1153, 0 },
1226  { 139, 1, 1, 1, 1153, 0 },
1227  { 379, 1, 1, 1, 1153, 0 },
1228  { 191, 14, 1, 9, 994, 10 },
1229  { 431, 17, 1, 9, 994, 10 },
1230  { 623, 20, 1, 9, 994, 10 },
1231  { 809, 23, 1, 9, 994, 10 },
1232  { 1396, 26, 1, 9, 994, 10 },
1233  { 1550, 29, 1, 9, 994, 10 },
1234  { 1700, 32, 1, 9, 994, 10 },
1235  { 1850, 35, 1, 9, 994, 10 },
1236  { 1995, 38, 1, 9, 994, 10 },
1237  { 2153, 41, 1, 9, 994, 10 },
1238  { 27, 44, 1, 9, 994, 10 },
1239  { 267, 47, 1, 9, 994, 10 },
1240  { 507, 50, 1, 9, 994, 10 },
1241  { 693, 53, 1, 9, 994, 10 },
1242  { 871, 56, 1, 9, 994, 10 },
1243  { 1454, 59, 1, 9, 994, 10 },
1244  { 112, 1, 144, 1, 2305, 0 },
1245  { 352, 1, 142, 1, 2305, 0 },
1246  { 592, 1, 140, 1, 2305, 0 },
1247  { 778, 1, 138, 1, 2305, 0 },
1248  { 194, 1, 159, 1, 4001, 0 },
1249  { 434, 1, 163, 1, 4001, 0 },
1250  { 626, 1, 163, 1, 4001, 0 },
1251  { 812, 1, 167, 1, 4001, 0 },
1252  { 1399, 1, 167, 1, 4001, 0 },
1253  { 1553, 1, 171, 1, 4001, 0 },
1254  { 1703, 1, 171, 1, 4001, 0 },
1255  { 1853, 1, 175, 1, 4001, 0 },
1256  { 1998, 1, 175, 1, 4001, 0 },
1257  { 2156, 1, 179, 1, 4001, 0 },
1258  { 31, 1, 179, 1, 4001, 0 },
1259  { 271, 1, 183, 1, 4001, 0 },
1260  { 511, 1, 183, 1, 4001, 0 },
1261  { 697, 1, 187, 1, 4001, 0 },
1262  { 875, 1, 187, 1, 4001, 0 },
1263  { 1458, 1, 191, 1, 4001, 0 },
1264  { 1608, 1, 191, 1, 4001, 0 },
1265  { 1758, 1, 195, 1, 4001, 0 },
1266  { 1908, 1, 195, 1, 4001, 0 },
1267  { 2050, 1, 199, 1, 4001, 0 },
1268  { 79, 1, 199, 1, 4001, 0 },
1269  { 319, 1, 203, 1, 4001, 0 },
1270  { 559, 1, 203, 1, 4001, 0 },
1271  { 745, 1, 207, 1, 4001, 0 },
1272  { 923, 1, 207, 1, 4001, 0 },
1273  { 1506, 1, 211, 1, 4001, 0 },
1274  { 1656, 1, 211, 1, 4001, 0 },
1275  { 1806, 1, 215, 1, 4001, 0 },
1276  { 1956, 1, 215, 1, 4001, 0 },
1277  { 2114, 1, 219, 1, 4001, 0 },
1278  { 146, 1, 219, 1, 4001, 0 },
1279  { 386, 1, 223, 1, 4001, 0 },
1280  { 186, 1, 1, 1, 4001, 0 },
1281  { 426, 1, 1, 1, 4001, 0 },
1282  { 618, 1, 1, 1, 4001, 0 },
1283  { 804, 1, 1, 1, 4001, 0 },
1284  { 1391, 1, 1, 1, 4001, 0 },
1285  { 1545, 1, 1, 1, 4001, 0 },
1286  { 1695, 1, 1, 1, 4001, 0 },
1287  { 1845, 1, 1, 1, 4001, 0 },
1288  { 218, 1, 1, 1, 4001, 0 },
1289  { 458, 1, 1, 1, 4001, 0 },
1290  { 647, 1, 1, 1, 4001, 0 },
1291  { 825, 1, 1, 1, 4001, 0 },
1292  { 1408, 1, 1, 1, 4001, 0 },
1293  { 1562, 1, 1, 1, 4001, 0 },
1294  { 1712, 1, 1, 1, 4001, 0 },
1295  { 1862, 1, 1, 1, 4001, 0 },
1296  { 2007, 1, 1, 1, 4001, 0 },
1297  { 2165, 1, 1, 1, 4001, 0 },
1298  { 42, 1, 1, 1, 4001, 0 },
1299  { 282, 1, 1, 1, 4001, 0 },
1300  { 522, 1, 1, 1, 4001, 0 },
1301  { 708, 1, 1, 1, 4001, 0 },
1302  { 886, 1, 1, 1, 4001, 0 },
1303  { 1469, 1, 1, 1, 4001, 0 },
1304  { 1619, 1, 1, 1, 4001, 0 },
1305  { 1769, 1, 1, 1, 4001, 0 },
1306  { 1919, 1, 1, 1, 4001, 0 },
1307  { 2061, 1, 1, 1, 4001, 0 },
1308  { 96, 1, 1, 1, 4001, 0 },
1309  { 336, 1, 1, 1, 4001, 0 },
1310  { 576, 1, 1, 1, 4001, 0 },
1311  { 762, 1, 1, 1, 4001, 0 },
1312  { 940, 1, 1, 1, 4001, 0 },
1313  { 1523, 1, 1, 1, 4001, 0 },
1314  { 1673, 1, 1, 1, 4001, 0 },
1315  { 1823, 1, 1, 1, 4001, 0 },
1316  { 1973, 1, 1, 1, 4001, 0 },
1317  { 2131, 1, 1, 1, 4001, 0 },
1318  { 163, 1, 1, 1, 4001, 0 },
1319  { 403, 1, 1, 1, 4001, 0 },
1320  { 1367, 136, 1, 0, 1184, 2 },
1321  { 197, 1, 156, 1, 3969, 0 },
1322  { 437, 1, 156, 1, 3969, 0 },
1323  { 629, 1, 156, 1, 3969, 0 },
1324  { 815, 1, 156, 1, 3969, 0 },
1325  { 1402, 1, 156, 1, 3969, 0 },
1326  { 1556, 1, 156, 1, 3969, 0 },
1327  { 1706, 1, 156, 1, 3969, 0 },
1328  { 1856, 1, 156, 1, 3969, 0 },
1329  { 2001, 1, 156, 1, 3969, 0 },
1330  { 2159, 1, 156, 1, 3969, 0 },
1331  { 35, 1, 156, 1, 3969, 0 },
1332  { 275, 1, 156, 1, 3969, 0 },
1333  { 515, 1, 156, 1, 3969, 0 },
1334  { 701, 1, 156, 1, 3969, 0 },
1335  { 879, 1, 156, 1, 3969, 0 },
1336  { 1462, 1, 156, 1, 3969, 0 },
1337  { 1612, 1, 156, 1, 3969, 0 },
1338  { 1762, 1, 156, 1, 3969, 0 },
1339  { 1912, 1, 156, 1, 3969, 0 },
1340  { 2054, 1, 156, 1, 3969, 0 },
1341  { 83, 1, 156, 1, 3969, 0 },
1342  { 323, 1, 156, 1, 3969, 0 },
1343  { 563, 1, 156, 1, 3969, 0 },
1344  { 749, 1, 156, 1, 3969, 0 },
1345  { 927, 1, 156, 1, 3969, 0 },
1346  { 1510, 1, 156, 1, 3969, 0 },
1347  { 1660, 1, 156, 1, 3969, 0 },
1348  { 1810, 1, 156, 1, 3969, 0 },
1349  { 1960, 1, 156, 1, 3969, 0 },
1350  { 2118, 1, 156, 1, 3969, 0 },
1351  { 150, 1, 156, 1, 3969, 0 },
1352  { 390, 1, 156, 1, 3969, 0 },
1353  { 1373, 128, 1, 0, 1216, 2 },
1354  { 199, 1, 234, 1, 1826, 0 },
1355  { 439, 1, 134, 1, 1826, 0 },
1356  { 631, 1, 134, 1, 1826, 0 },
1357  { 817, 1, 134, 1, 1826, 0 },
1358  { 223, 1, 1, 1, 3937, 0 },
1359  { 463, 1, 1, 1, 3937, 0 },
1360  { 652, 1, 1, 1, 3937, 0 },
1361  { 830, 1, 1, 1, 3937, 0 },
1362  { 1413, 1, 1, 1, 3937, 0 },
1363  { 1567, 1, 1, 1, 3937, 0 },
1364  { 1717, 1, 1, 1, 3937, 0 },
1365  { 1867, 1, 1, 1, 3937, 0 },
1366  { 2012, 1, 1, 1, 3937, 0 },
1367  { 2170, 1, 1, 1, 3937, 0 },
1368  { 48, 1, 1, 1, 3937, 0 },
1369  { 288, 1, 1, 1, 3937, 0 },
1370  { 528, 1, 1, 1, 3937, 0 },
1371  { 714, 1, 1, 1, 3937, 0 },
1372  { 892, 1, 1, 1, 3937, 0 },
1373  { 1475, 1, 1, 1, 3937, 0 },
1374  { 1625, 1, 1, 1, 3937, 0 },
1375  { 1775, 1, 1, 1, 3937, 0 },
1376  { 1925, 1, 1, 1, 3937, 0 },
1377  { 2067, 1, 1, 1, 3937, 0 },
1378  { 102, 1, 1, 1, 3937, 0 },
1379  { 342, 1, 1, 1, 3937, 0 },
1380  { 582, 1, 1, 1, 3937, 0 },
1381  { 768, 1, 1, 1, 3937, 0 },
1382  { 946, 1, 1, 1, 3937, 0 },
1383  { 1529, 1, 1, 1, 3937, 0 },
1384  { 1679, 1, 1, 1, 3937, 0 },
1385  { 1829, 1, 1, 1, 3937, 0 },
1386  { 1979, 1, 1, 1, 3937, 0 },
1387  { 2137, 1, 1, 1, 3937, 0 },
1388  { 169, 1, 1, 1, 3937, 0 },
1389  { 409, 1, 1, 1, 3937, 0 },
1390  { 203, 1, 100, 1, 3937, 0 },
1391  { 443, 1, 100, 1, 3937, 0 },
1392  { 211, 1, 230, 1, 1794, 0 },
1393  { 451, 1, 126, 1, 1794, 0 },
1394  { 640, 1, 126, 1, 1794, 0 },
1395  { 821, 1, 126, 1, 1794, 0 },
1396  { 206, 1, 1, 1, 3905, 0 },
1397  { 446, 1, 1, 1, 3905, 0 },
1398  { 635, 1, 1, 1, 3905, 0 },
1399  { 215, 1, 1, 1, 3905, 0 },
1400  { 455, 1, 1, 1, 3905, 0 },
1401  { 644, 1, 1, 1, 3905, 0 },
1402  { 1353, 124, 1, 0, 1248, 2 },
1403  { 228, 1, 98, 1, 3873, 0 },
1404  { 468, 1, 98, 1, 3873, 0 },
1405  { 657, 1, 98, 1, 3873, 0 },
1406  { 835, 1, 98, 1, 3873, 0 },
1407  { 1418, 1, 98, 1, 3873, 0 },
1408  { 1572, 1, 98, 1, 3873, 0 },
1409  { 1722, 1, 98, 1, 3873, 0 },
1410  { 1872, 1, 98, 1, 3873, 0 },
1411  { 1379, 122, 1, 0, 1280, 2 },
1412  { 231, 1, 96, 1, 3841, 0 },
1413  { 471, 1, 96, 1, 3841, 0 },
1414  { 660, 1, 96, 1, 3841, 0 },
1415  { 838, 1, 96, 1, 3841, 0 },
1416  { 1421, 1, 96, 1, 3841, 0 },
1417  { 1575, 1, 96, 1, 3841, 0 },
1418  { 1725, 1, 96, 1, 3841, 0 },
1419  { 1875, 1, 96, 1, 3841, 0 },
1420  { 2017, 1, 96, 1, 3841, 0 },
1421  { 2175, 1, 96, 1, 3841, 0 },
1422  { 234, 1, 96, 1, 3841, 0 },
1423  { 474, 1, 96, 1, 3841, 0 },
1424  { 237, 92, 1, 8, 1425, 10 },
1425  { 477, 92, 1, 8, 1425, 10 },
1426  { 663, 92, 1, 8, 1425, 10 },
1427  { 841, 92, 1, 8, 1425, 10 },
1428  { 1424, 92, 1, 8, 1425, 10 },
1429  { 1578, 92, 1, 8, 1425, 10 },
1430  { 1728, 92, 1, 8, 1425, 10 },
1431  { 1878, 92, 1, 8, 1425, 10 },
1432  { 2020, 92, 1, 8, 1425, 10 },
1433  { 2178, 92, 1, 8, 1425, 10 },
1434  { 54, 92, 1, 8, 1425, 10 },
1435  { 294, 92, 1, 8, 1425, 10 },
1436  { 534, 92, 1, 8, 1425, 10 },
1437  { 720, 92, 1, 8, 1425, 10 },
1438  { 898, 92, 1, 8, 1425, 10 },
1439  { 1481, 92, 1, 8, 1425, 10 },
1440  { 1631, 92, 1, 8, 1425, 10 },
1441  { 1781, 92, 1, 8, 1425, 10 },
1442  { 1931, 92, 1, 8, 1425, 10 },
1443  { 2073, 92, 1, 8, 1425, 10 },
1444  { 108, 92, 1, 8, 1425, 10 },
1445  { 348, 92, 1, 8, 1425, 10 },
1446  { 588, 92, 1, 8, 1425, 10 },
1447  { 774, 92, 1, 8, 1425, 10 },
1448  { 952, 92, 1, 8, 1425, 10 },
1449  { 1535, 92, 1, 8, 1425, 10 },
1450  { 1685, 92, 1, 8, 1425, 10 },
1451  { 1835, 92, 1, 8, 1425, 10 },
1452  { 1985, 92, 1, 8, 1425, 10 },
1453  { 2143, 92, 1, 8, 1425, 10 },
1454  { 175, 92, 1, 8, 1425, 10 },
1455  { 415, 92, 1, 8, 1425, 10 },
1456  { 1359, 118, 1, 0, 1921, 2 },
1457  { 983, 118, 1, 0, 1921, 2 },
1458  { 1061, 118, 1, 0, 1921, 2 },
1459  { 1111, 118, 1, 0, 1921, 2 },
1460  { 1149, 118, 1, 0, 1921, 2 },
1461  { 989, 130, 1, 12, 656, 10 },
1462  { 996, 93, 157, 9, 1377, 10 },
1463  { 1067, 93, 157, 9, 1377, 10 },
1464  { 1117, 93, 157, 9, 1377, 10 },
1465  { 1155, 93, 157, 9, 1377, 10 },
1466  { 1187, 93, 157, 9, 1377, 10 },
1467  { 1219, 93, 157, 9, 1377, 10 },
1468  { 1251, 93, 157, 9, 1377, 10 },
1469  { 1283, 93, 157, 9, 1377, 10 },
1470  { 1315, 93, 157, 9, 1377, 10 },
1471  { 1341, 93, 157, 9, 1377, 10 },
1472  { 962, 93, 157, 9, 1377, 10 },
1473  { 1040, 93, 157, 9, 1377, 10 },
1474  { 1097, 93, 157, 9, 1377, 10 },
1475  { 1135, 93, 157, 9, 1377, 10 },
1476  { 1173, 93, 157, 9, 1377, 10 },
1477  { 1205, 93, 157, 9, 1377, 10 },
1478  { 1237, 93, 157, 9, 1377, 10 },
1479  { 1269, 93, 157, 9, 1377, 10 },
1480  { 1301, 93, 157, 9, 1377, 10 },
1481  { 1327, 93, 157, 9, 1377, 10 },
1482  { 969, 93, 157, 9, 1377, 10 },
1483  { 1047, 93, 157, 9, 1377, 10 },
1484  { 1104, 93, 157, 9, 1377, 10 },
1485  { 1142, 93, 157, 9, 1377, 10 },
1486  { 1180, 93, 157, 9, 1377, 10 },
1487  { 1212, 93, 157, 9, 1377, 10 },
1488  { 1244, 93, 157, 9, 1377, 10 },
1489  { 1276, 93, 157, 9, 1377, 10 },
1490  { 1308, 93, 157, 9, 1377, 10 },
1491  { 1334, 93, 157, 9, 1377, 10 },
1492  { 976, 93, 157, 9, 1377, 10 },
1493  { 1054, 93, 157, 9, 1377, 10 },
1494  { 2077, 1, 116, 1, 1120, 0 },
1495  { 1002, 138, 236, 0, 1344, 2 },
1496  { 1009, 150, 1, 0, 2337, 2 },
1497  { 1073, 150, 1, 0, 2337, 2 },
1498  { 1015, 150, 232, 0, 1312, 2 },
1499  { 1022, 152, 1, 0, 2369, 2 },
1500  { 1079, 152, 1, 0, 2369, 2 },
1501  { 1123, 152, 1, 0, 2369, 2 },
1502  { 1161, 152, 1, 0, 2369, 2 },
1503  { 1193, 152, 1, 0, 2369, 2 },
1504  { 1225, 152, 1, 0, 2369, 2 },
1505  { 1257, 152, 1, 0, 2369, 2 },
1506  { 1289, 152, 1, 0, 2369, 2 },
1507  { 1028, 154, 1, 0, 2369, 2 },
1508  { 1085, 154, 1, 0, 2369, 2 },
1509  { 1129, 154, 1, 0, 2369, 2 },
1510  { 1167, 154, 1, 0, 2369, 2 },
1511  { 1199, 154, 1, 0, 2369, 2 },
1512  { 1231, 154, 1, 0, 2369, 2 },
1513  { 1263, 154, 1, 0, 2369, 2 },
1514  { 1295, 154, 1, 0, 2369, 2 },
1515  { 1321, 154, 1, 0, 2369, 2 },
1516  { 1347, 154, 1, 0, 2369, 2 },
1517  { 1034, 154, 1, 0, 2369, 2 },
1518  { 1091, 154, 1, 0, 2369, 2 },
1519};
1520
1521extern const MCPhysReg MipsRegUnitRoots[][2] = {
1522  { Mips::AT },
1523  { Mips::DSPCCond },
1524  { Mips::DSPCarry },
1525  { Mips::DSPEFI },
1526  { Mips::DSPOutFlag16_19 },
1527  { Mips::DSPOutFlag20 },
1528  { Mips::DSPOutFlag21 },
1529  { Mips::DSPOutFlag22 },
1530  { Mips::DSPOutFlag23 },
1531  { Mips::DSPPos },
1532  { Mips::DSPSCount },
1533  { Mips::FP },
1534  { Mips::GP },
1535  { Mips::MSAAccess },
1536  { Mips::MSACSR },
1537  { Mips::MSAIR },
1538  { Mips::MSAMap },
1539  { Mips::MSAModify },
1540  { Mips::MSARequest },
1541  { Mips::MSASave },
1542  { Mips::MSAUnmap },
1543  { Mips::PC },
1544  { Mips::RA },
1545  { Mips::SP },
1546  { Mips::ZERO },
1547  { Mips::A0 },
1548  { Mips::A1 },
1549  { Mips::A2 },
1550  { Mips::A3 },
1551  { Mips::LO0 },
1552  { Mips::HI0 },
1553  { Mips::LO1 },
1554  { Mips::HI1 },
1555  { Mips::LO2 },
1556  { Mips::HI2 },
1557  { Mips::LO3 },
1558  { Mips::HI3 },
1559  { Mips::COP00 },
1560  { Mips::COP01 },
1561  { Mips::COP02 },
1562  { Mips::COP03 },
1563  { Mips::COP04 },
1564  { Mips::COP05 },
1565  { Mips::COP06 },
1566  { Mips::COP07 },
1567  { Mips::COP08 },
1568  { Mips::COP09 },
1569  { Mips::COP20 },
1570  { Mips::COP21 },
1571  { Mips::COP22 },
1572  { Mips::COP23 },
1573  { Mips::COP24 },
1574  { Mips::COP25 },
1575  { Mips::COP26 },
1576  { Mips::COP27 },
1577  { Mips::COP28 },
1578  { Mips::COP29 },
1579  { Mips::COP30 },
1580  { Mips::COP31 },
1581  { Mips::COP32 },
1582  { Mips::COP33 },
1583  { Mips::COP34 },
1584  { Mips::COP35 },
1585  { Mips::COP36 },
1586  { Mips::COP37 },
1587  { Mips::COP38 },
1588  { Mips::COP39 },
1589  { Mips::COP010 },
1590  { Mips::COP011 },
1591  { Mips::COP012 },
1592  { Mips::COP013 },
1593  { Mips::COP014 },
1594  { Mips::COP015 },
1595  { Mips::COP016 },
1596  { Mips::COP017 },
1597  { Mips::COP018 },
1598  { Mips::COP019 },
1599  { Mips::COP020 },
1600  { Mips::COP021 },
1601  { Mips::COP022 },
1602  { Mips::COP023 },
1603  { Mips::COP024 },
1604  { Mips::COP025 },
1605  { Mips::COP026 },
1606  { Mips::COP027 },
1607  { Mips::COP028 },
1608  { Mips::COP029 },
1609  { Mips::COP030 },
1610  { Mips::COP031 },
1611  { Mips::COP210 },
1612  { Mips::COP211 },
1613  { Mips::COP212 },
1614  { Mips::COP213 },
1615  { Mips::COP214 },
1616  { Mips::COP215 },
1617  { Mips::COP216 },
1618  { Mips::COP217 },
1619  { Mips::COP218 },
1620  { Mips::COP219 },
1621  { Mips::COP220 },
1622  { Mips::COP221 },
1623  { Mips::COP222 },
1624  { Mips::COP223 },
1625  { Mips::COP224 },
1626  { Mips::COP225 },
1627  { Mips::COP226 },
1628  { Mips::COP227 },
1629  { Mips::COP228 },
1630  { Mips::COP229 },
1631  { Mips::COP230 },
1632  { Mips::COP231 },
1633  { Mips::COP310 },
1634  { Mips::COP311 },
1635  { Mips::COP312 },
1636  { Mips::COP313 },
1637  { Mips::COP314 },
1638  { Mips::COP315 },
1639  { Mips::COP316 },
1640  { Mips::COP317 },
1641  { Mips::COP318 },
1642  { Mips::COP319 },
1643  { Mips::COP320 },
1644  { Mips::COP321 },
1645  { Mips::COP322 },
1646  { Mips::COP323 },
1647  { Mips::COP324 },
1648  { Mips::COP325 },
1649  { Mips::COP326 },
1650  { Mips::COP327 },
1651  { Mips::COP328 },
1652  { Mips::COP329 },
1653  { Mips::COP330 },
1654  { Mips::COP331 },
1655  { Mips::F0 },
1656  { Mips::F1 },
1657  { Mips::F2 },
1658  { Mips::F3 },
1659  { Mips::F4 },
1660  { Mips::F5 },
1661  { Mips::F6 },
1662  { Mips::F7 },
1663  { Mips::F8 },
1664  { Mips::F9 },
1665  { Mips::F10 },
1666  { Mips::F11 },
1667  { Mips::F12 },
1668  { Mips::F13 },
1669  { Mips::F14 },
1670  { Mips::F15 },
1671  { Mips::F16 },
1672  { Mips::F17 },
1673  { Mips::F18 },
1674  { Mips::F19 },
1675  { Mips::F20 },
1676  { Mips::F21 },
1677  { Mips::F22 },
1678  { Mips::F23 },
1679  { Mips::F24 },
1680  { Mips::F25 },
1681  { Mips::F26 },
1682  { Mips::F27 },
1683  { Mips::F28 },
1684  { Mips::F29 },
1685  { Mips::F30 },
1686  { Mips::F31 },
1687  { Mips::FCC0 },
1688  { Mips::FCC1 },
1689  { Mips::FCC2 },
1690  { Mips::FCC3 },
1691  { Mips::FCC4 },
1692  { Mips::FCC5 },
1693  { Mips::FCC6 },
1694  { Mips::FCC7 },
1695  { Mips::FCR0 },
1696  { Mips::FCR1 },
1697  { Mips::FCR2 },
1698  { Mips::FCR3 },
1699  { Mips::FCR4 },
1700  { Mips::FCR5 },
1701  { Mips::FCR6 },
1702  { Mips::FCR7 },
1703  { Mips::FCR8 },
1704  { Mips::FCR9 },
1705  { Mips::FCR10 },
1706  { Mips::FCR11 },
1707  { Mips::FCR12 },
1708  { Mips::FCR13 },
1709  { Mips::FCR14 },
1710  { Mips::FCR15 },
1711  { Mips::FCR16 },
1712  { Mips::FCR17 },
1713  { Mips::FCR18 },
1714  { Mips::FCR19 },
1715  { Mips::FCR20 },
1716  { Mips::FCR21 },
1717  { Mips::FCR22 },
1718  { Mips::FCR23 },
1719  { Mips::FCR24 },
1720  { Mips::FCR25 },
1721  { Mips::FCR26 },
1722  { Mips::FCR27 },
1723  { Mips::FCR28 },
1724  { Mips::FCR29 },
1725  { Mips::FCR30 },
1726  { Mips::FCR31 },
1727  { Mips::F_HI0 },
1728  { Mips::F_HI1 },
1729  { Mips::F_HI2 },
1730  { Mips::F_HI3 },
1731  { Mips::F_HI4 },
1732  { Mips::F_HI5 },
1733  { Mips::F_HI6 },
1734  { Mips::F_HI7 },
1735  { Mips::F_HI8 },
1736  { Mips::F_HI9 },
1737  { Mips::F_HI10 },
1738  { Mips::F_HI11 },
1739  { Mips::F_HI12 },
1740  { Mips::F_HI13 },
1741  { Mips::F_HI14 },
1742  { Mips::F_HI15 },
1743  { Mips::F_HI16 },
1744  { Mips::F_HI17 },
1745  { Mips::F_HI18 },
1746  { Mips::F_HI19 },
1747  { Mips::F_HI20 },
1748  { Mips::F_HI21 },
1749  { Mips::F_HI22 },
1750  { Mips::F_HI23 },
1751  { Mips::F_HI24 },
1752  { Mips::F_HI25 },
1753  { Mips::F_HI26 },
1754  { Mips::F_HI27 },
1755  { Mips::F_HI28 },
1756  { Mips::F_HI29 },
1757  { Mips::F_HI30 },
1758  { Mips::F_HI31 },
1759  { Mips::HWR0 },
1760  { Mips::HWR1 },
1761  { Mips::HWR2 },
1762  { Mips::HWR3 },
1763  { Mips::HWR4 },
1764  { Mips::HWR5 },
1765  { Mips::HWR6 },
1766  { Mips::HWR7 },
1767  { Mips::HWR8 },
1768  { Mips::HWR9 },
1769  { Mips::HWR10 },
1770  { Mips::HWR11 },
1771  { Mips::HWR12 },
1772  { Mips::HWR13 },
1773  { Mips::HWR14 },
1774  { Mips::HWR15 },
1775  { Mips::HWR16 },
1776  { Mips::HWR17 },
1777  { Mips::HWR18 },
1778  { Mips::HWR19 },
1779  { Mips::HWR20 },
1780  { Mips::HWR21 },
1781  { Mips::HWR22 },
1782  { Mips::HWR23 },
1783  { Mips::HWR24 },
1784  { Mips::HWR25 },
1785  { Mips::HWR26 },
1786  { Mips::HWR27 },
1787  { Mips::HWR28 },
1788  { Mips::HWR29 },
1789  { Mips::HWR30 },
1790  { Mips::HWR31 },
1791  { Mips::K0 },
1792  { Mips::K1 },
1793  { Mips::MPL0 },
1794  { Mips::MPL1 },
1795  { Mips::MPL2 },
1796  { Mips::P0 },
1797  { Mips::P1 },
1798  { Mips::P2 },
1799  { Mips::S0 },
1800  { Mips::S1 },
1801  { Mips::S2 },
1802  { Mips::S3 },
1803  { Mips::S4 },
1804  { Mips::S5 },
1805  { Mips::S6 },
1806  { Mips::S7 },
1807  { Mips::T0 },
1808  { Mips::T1 },
1809  { Mips::T2 },
1810  { Mips::T3 },
1811  { Mips::T4 },
1812  { Mips::T5 },
1813  { Mips::T6 },
1814  { Mips::T7 },
1815  { Mips::T8 },
1816  { Mips::T9 },
1817  { Mips::V0 },
1818  { Mips::V1 },
1819};
1820
1821namespace {     // Register classes...
1822  // MSA128F16 Register Class...
1823  const MCPhysReg MSA128F16[] = {
1824    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
1825  };
1826
1827  // MSA128F16 Bit set.
1828  const uint8_t MSA128F16Bits[] = {
1829    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1830  };
1831
1832  // MSA128F16_with_sub_64_in_OddSP Register Class...
1833  const MCPhysReg MSA128F16_with_sub_64_in_OddSP[] = {
1834    Mips::W1, Mips::W3, Mips::W5, Mips::W7, Mips::W9, Mips::W11, Mips::W13, Mips::W15, Mips::W17, Mips::W19, Mips::W21, Mips::W23, Mips::W25, Mips::W27, Mips::W29, Mips::W31,
1835  };
1836
1837  // MSA128F16_with_sub_64_in_OddSP Bit set.
1838  const uint8_t MSA128F16_with_sub_64_in_OddSPBits[] = {
1839    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
1840  };
1841
1842  // OddSP Register Class...
1843  const MCPhysReg OddSP[] = {
1844    Mips::F1, Mips::F3, Mips::F5, Mips::F7, Mips::F9, Mips::F11, Mips::F13, Mips::F15, Mips::F17, Mips::F19, Mips::F21, Mips::F23, Mips::F25, Mips::F27, Mips::F29, Mips::F31, Mips::F_HI1, Mips::F_HI3, Mips::F_HI5, Mips::F_HI7, Mips::F_HI9, Mips::F_HI11, Mips::F_HI13, Mips::F_HI15, Mips::F_HI17, Mips::F_HI19, Mips::F_HI21, Mips::F_HI23, Mips::F_HI25, Mips::F_HI27, Mips::F_HI29, Mips::F_HI31, Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64,
1845  };
1846
1847  // OddSP Bit set.
1848  const uint8_t OddSPBits[] = {
1849    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
1850  };
1851
1852  // CCR Register Class...
1853  const MCPhysReg CCR[] = {
1854    Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31,
1855  };
1856
1857  // CCR Bit set.
1858  const uint8_t CCRBits[] = {
1859    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1860  };
1861
1862  // COP0 Register Class...
1863  const MCPhysReg COP0[] = {
1864    Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031,
1865  };
1866
1867  // COP0 Bit set.
1868  const uint8_t COP0Bits[] = {
1869    0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07,
1870  };
1871
1872  // COP2 Register Class...
1873  const MCPhysReg COP2[] = {
1874    Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231,
1875  };
1876
1877  // COP2 Bit set.
1878  const uint8_t COP2Bits[] = {
1879    0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01,
1880  };
1881
1882  // COP3 Register Class...
1883  const MCPhysReg COP3[] = {
1884    Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331,
1885  };
1886
1887  // COP3 Bit set.
1888  const uint8_t COP3Bits[] = {
1889    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f,
1890  };
1891
1892  // DSPR Register Class...
1893  const MCPhysReg DSPR[] = {
1894    Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
1895  };
1896
1897  // DSPR Bit set.
1898  const uint8_t DSPRBits[] = {
1899    0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
1900  };
1901
1902  // FGR32 Register Class...
1903  const MCPhysReg FGR32[] = {
1904    Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
1905  };
1906
1907  // FGR32 Bit set.
1908  const uint8_t FGR32Bits[] = {
1909    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1910  };
1911
1912  // FGRCC Register Class...
1913  const MCPhysReg FGRCC[] = {
1914    Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
1915  };
1916
1917  // FGRCC Bit set.
1918  const uint8_t FGRCCBits[] = {
1919    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1920  };
1921
1922  // FGRH32 Register Class...
1923  const MCPhysReg FGRH32[] = {
1924    Mips::F_HI0, Mips::F_HI1, Mips::F_HI2, Mips::F_HI3, Mips::F_HI4, Mips::F_HI5, Mips::F_HI6, Mips::F_HI7, Mips::F_HI8, Mips::F_HI9, Mips::F_HI10, Mips::F_HI11, Mips::F_HI12, Mips::F_HI13, Mips::F_HI14, Mips::F_HI15, Mips::F_HI16, Mips::F_HI17, Mips::F_HI18, Mips::F_HI19, Mips::F_HI20, Mips::F_HI21, Mips::F_HI22, Mips::F_HI23, Mips::F_HI24, Mips::F_HI25, Mips::F_HI26, Mips::F_HI27, Mips::F_HI28, Mips::F_HI29, Mips::F_HI30, Mips::F_HI31,
1925  };
1926
1927  // FGRH32 Bit set.
1928  const uint8_t FGRH32Bits[] = {
1929    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
1930  };
1931
1932  // GPR32 Register Class...
1933  const MCPhysReg GPR32[] = {
1934    Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
1935  };
1936
1937  // GPR32 Bit set.
1938  const uint8_t GPR32Bits[] = {
1939    0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
1940  };
1941
1942  // HWRegs Register Class...
1943  const MCPhysReg HWRegs[] = {
1944    Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31,
1945  };
1946
1947  // HWRegs Bit set.
1948  const uint8_t HWRegsBits[] = {
1949    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
1950  };
1951
1952  // GPR32NONZERO Register Class...
1953  const MCPhysReg GPR32NONZERO[] = {
1954    Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
1955  };
1956
1957  // GPR32NONZERO Bit set.
1958  const uint8_t GPR32NONZEROBits[] = {
1959    0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
1960  };
1961
1962  // OddSP_with_sub_hi Register Class...
1963  const MCPhysReg OddSP_with_sub_hi[] = {
1964    Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64,
1965  };
1966
1967  // OddSP_with_sub_hi Bit set.
1968  const uint8_t OddSP_with_sub_hiBits[] = {
1969    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
1970  };
1971
1972  // FGR32_and_OddSP Register Class...
1973  const MCPhysReg FGR32_and_OddSP[] = {
1974    Mips::F1, Mips::F3, Mips::F5, Mips::F7, Mips::F9, Mips::F11, Mips::F13, Mips::F15, Mips::F17, Mips::F19, Mips::F21, Mips::F23, Mips::F25, Mips::F27, Mips::F29, Mips::F31,
1975  };
1976
1977  // FGR32_and_OddSP Bit set.
1978  const uint8_t FGR32_and_OddSPBits[] = {
1979    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
1980  };
1981
1982  // FGRH32_and_OddSP Register Class...
1983  const MCPhysReg FGRH32_and_OddSP[] = {
1984    Mips::F_HI1, Mips::F_HI3, Mips::F_HI5, Mips::F_HI7, Mips::F_HI9, Mips::F_HI11, Mips::F_HI13, Mips::F_HI15, Mips::F_HI17, Mips::F_HI19, Mips::F_HI21, Mips::F_HI23, Mips::F_HI25, Mips::F_HI27, Mips::F_HI29, Mips::F_HI31,
1985  };
1986
1987  // FGRH32_and_OddSP Bit set.
1988  const uint8_t FGRH32_and_OddSPBits[] = {
1989    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a,
1990  };
1991
1992  // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class...
1993  const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = {
1994    Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64,
1995  };
1996
1997  // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set.
1998  const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = {
1999    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
2000  };
2001
2002  // CPU16RegsPlusSP Register Class...
2003  const MCPhysReg CPU16RegsPlusSP[] = {
2004    Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP,
2005  };
2006
2007  // CPU16RegsPlusSP Bit set.
2008  const uint8_t CPU16RegsPlusSPBits[] = {
2009    0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2010  };
2011
2012  // CPU16Regs Register Class...
2013  const MCPhysReg CPU16Regs[] = {
2014    Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1,
2015  };
2016
2017  // CPU16Regs Bit set.
2018  const uint8_t CPU16RegsBits[] = {
2019    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2020  };
2021
2022  // FCC Register Class...
2023  const MCPhysReg FCC[] = {
2024    Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7,
2025  };
2026
2027  // FCC Bit set.
2028  const uint8_t FCCBits[] = {
2029    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2030  };
2031
2032  // GPRMM16 Register Class...
2033  const MCPhysReg GPRMM16[] = {
2034    Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2035  };
2036
2037  // GPRMM16 Bit set.
2038  const uint8_t GPRMM16Bits[] = {
2039    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2040  };
2041
2042  // GPRMM16MoveP Register Class...
2043  const MCPhysReg GPRMM16MoveP[] = {
2044    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
2045  };
2046
2047  // GPRMM16MoveP Bit set.
2048  const uint8_t GPRMM16MovePBits[] = {
2049    0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
2050  };
2051
2052  // GPRMM16Zero Register Class...
2053  const MCPhysReg GPRMM16Zero[] = {
2054    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2055  };
2056
2057  // GPRMM16Zero Bit set.
2058  const uint8_t GPRMM16ZeroBits[] = {
2059    0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2060  };
2061
2062  // MSACtrl Register Class...
2063  const MCPhysReg MSACtrl[] = {
2064    Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap,
2065  };
2066
2067  // MSACtrl Bit set.
2068  const uint8_t MSACtrlBits[] = {
2069    0x00, 0xfc, 0x03,
2070  };
2071
2072  // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class...
2073  const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = {
2074    Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15,
2075  };
2076
2077  // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set.
2078  const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = {
2079    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
2080  };
2081
2082  // CPU16Regs_and_GPRMM16Zero Register Class...
2083  const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
2084    Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2085  };
2086
2087  // CPU16Regs_and_GPRMM16Zero Bit set.
2088  const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
2089    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2090  };
2091
2092  // GPR32NONZERO_and_GPRMM16MoveP Register Class...
2093  const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {
2094    Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
2095  };
2096
2097  // GPR32NONZERO_and_GPRMM16MoveP Bit set.
2098  const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = {
2099    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
2100  };
2101
2102  // CPU16Regs_and_GPRMM16MoveP Register Class...
2103  const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
2104    Mips::S1, Mips::V0, Mips::V1, Mips::S0,
2105  };
2106
2107  // CPU16Regs_and_GPRMM16MoveP Bit set.
2108  const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
2109    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2110  };
2111
2112  // GPRMM16MoveP_and_GPRMM16Zero Register Class...
2113  const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
2114    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1,
2115  };
2116
2117  // GPRMM16MoveP_and_GPRMM16Zero Bit set.
2118  const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2119    0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2120  };
2121
2122  // HI32DSP Register Class...
2123  const MCPhysReg HI32DSP[] = {
2124    Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3,
2125  };
2126
2127  // HI32DSP Bit set.
2128  const uint8_t HI32DSPBits[] = {
2129    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
2130  };
2131
2132  // LO32DSP Register Class...
2133  const MCPhysReg LO32DSP[] = {
2134    Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3,
2135  };
2136
2137  // LO32DSP Bit set.
2138  const uint8_t LO32DSPBits[] = {
2139    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
2140  };
2141
2142  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2143  const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2144    Mips::S1, Mips::V0, Mips::V1,
2145  };
2146
2147  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2148  const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2149    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2150  };
2151
2152  // CPURAReg Register Class...
2153  const MCPhysReg CPURAReg[] = {
2154    Mips::RA,
2155  };
2156
2157  // CPURAReg Bit set.
2158  const uint8_t CPURARegBits[] = {
2159    0x00, 0x00, 0x08,
2160  };
2161
2162  // CPUSPReg Register Class...
2163  const MCPhysReg CPUSPReg[] = {
2164    Mips::SP,
2165  };
2166
2167  // CPUSPReg Bit set.
2168  const uint8_t CPUSPRegBits[] = {
2169    0x00, 0x00, 0x10,
2170  };
2171
2172  // DSPCC Register Class...
2173  const MCPhysReg DSPCC[] = {
2174    Mips::DSPCCond,
2175  };
2176
2177  // DSPCC Bit set.
2178  const uint8_t DSPCCBits[] = {
2179    0x04,
2180  };
2181
2182  // GP32 Register Class...
2183  const MCPhysReg GP32[] = {
2184    Mips::GP,
2185  };
2186
2187  // GP32 Bit set.
2188  const uint8_t GP32Bits[] = {
2189    0x00, 0x02,
2190  };
2191
2192  // GPR32ZERO Register Class...
2193  const MCPhysReg GPR32ZERO[] = {
2194    Mips::ZERO,
2195  };
2196
2197  // GPR32ZERO Bit set.
2198  const uint8_t GPR32ZEROBits[] = {
2199    0x00, 0x00, 0x20,
2200  };
2201
2202  // HI32 Register Class...
2203  const MCPhysReg HI32[] = {
2204    Mips::HI0,
2205  };
2206
2207  // HI32 Bit set.
2208  const uint8_t HI32Bits[] = {
2209    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2210  };
2211
2212  // LO32 Register Class...
2213  const MCPhysReg LO32[] = {
2214    Mips::LO0,
2215  };
2216
2217  // LO32 Bit set.
2218  const uint8_t LO32Bits[] = {
2219    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2220  };
2221
2222  // SP32 Register Class...
2223  const MCPhysReg SP32[] = {
2224    Mips::SP,
2225  };
2226
2227  // SP32 Bit set.
2228  const uint8_t SP32Bits[] = {
2229    0x00, 0x00, 0x10,
2230  };
2231
2232  // FGR64 Register Class...
2233  const MCPhysReg FGR64[] = {
2234    Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64,
2235  };
2236
2237  // FGR64 Bit set.
2238  const uint8_t FGR64Bits[] = {
2239    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2240  };
2241
2242  // GPR64 Register Class...
2243  const MCPhysReg GPR64[] = {
2244    Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
2245  };
2246
2247  // GPR64 Bit set.
2248  const uint8_t GPR64Bits[] = {
2249    0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
2250  };
2251
2252  // GPR64_with_sub_32_in_GPR32NONZERO Register Class...
2253  const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {
2254    Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
2255  };
2256
2257  // GPR64_with_sub_32_in_GPR32NONZERO Bit set.
2258  const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = {
2259    0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
2260  };
2261
2262  // AFGR64 Register Class...
2263  const MCPhysReg AFGR64[] = {
2264    Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,
2265  };
2266
2267  // AFGR64 Bit set.
2268  const uint8_t AFGR64Bits[] = {
2269    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2270  };
2271
2272  // FGR64_and_OddSP Register Class...
2273  const MCPhysReg FGR64_and_OddSP[] = {
2274    Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64,
2275  };
2276
2277  // FGR64_and_OddSP Bit set.
2278  const uint8_t FGR64_and_OddSPBits[] = {
2279    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
2280  };
2281
2282  // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
2283  const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
2284    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64,
2285  };
2286
2287  // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
2288  const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
2289    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2290  };
2291
2292  // AFGR64_and_OddSP Register Class...
2293  const MCPhysReg AFGR64_and_OddSP[] = {
2294    Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15,
2295  };
2296
2297  // AFGR64_and_OddSP Bit set.
2298  const uint8_t AFGR64_and_OddSPBits[] = {
2299    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
2300  };
2301
2302  // GPR64_with_sub_32_in_CPU16Regs Register Class...
2303  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
2304    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64,
2305  };
2306
2307  // GPR64_with_sub_32_in_CPU16Regs Bit set.
2308  const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
2309    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2310  };
2311
2312  // GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
2313  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
2314    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
2315  };
2316
2317  // GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
2318  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
2319    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
2320  };
2321
2322  // GPR64_with_sub_32_in_GPRMM16Zero Register Class...
2323  const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
2324    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
2325  };
2326
2327  // GPR64_with_sub_32_in_GPRMM16Zero Bit set.
2328  const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
2329    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2330  };
2331
2332  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
2333  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
2334    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
2335  };
2336
2337  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
2338  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
2339    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2340  };
2341
2342  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class...
2343  const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {
2344    Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
2345  };
2346
2347  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set.
2348  const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = {
2349    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
2350  };
2351
2352  // ACC64DSP Register Class...
2353  const MCPhysReg ACC64DSP[] = {
2354    Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3,
2355  };
2356
2357  // ACC64DSP Bit set.
2358  const uint8_t ACC64DSPBits[] = {
2359    0x00, 0x00, 0x00, 0x3c,
2360  };
2361
2362  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
2363  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
2364    Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64,
2365  };
2366
2367  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
2368  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
2369    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2370  };
2371
2372  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
2373  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
2374    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64,
2375  };
2376
2377  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
2378  const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2379    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2380  };
2381
2382  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2383  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2384    Mips::V0_64, Mips::V1_64, Mips::S1_64,
2385  };
2386
2387  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2388  const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2389    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2390  };
2391
2392  // OCTEON_MPL Register Class...
2393  const MCPhysReg OCTEON_MPL[] = {
2394    Mips::MPL0, Mips::MPL1, Mips::MPL2,
2395  };
2396
2397  // OCTEON_MPL Bit set.
2398  const uint8_t OCTEON_MPLBits[] = {
2399    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
2400  };
2401
2402  // OCTEON_P Register Class...
2403  const MCPhysReg OCTEON_P[] = {
2404    Mips::P0, Mips::P1, Mips::P2,
2405  };
2406
2407  // OCTEON_P Bit set.
2408  const uint8_t OCTEON_PBits[] = {
2409    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
2410  };
2411
2412  // ACC64 Register Class...
2413  const MCPhysReg ACC64[] = {
2414    Mips::AC0,
2415  };
2416
2417  // ACC64 Bit set.
2418  const uint8_t ACC64Bits[] = {
2419    0x00, 0x00, 0x00, 0x04,
2420  };
2421
2422  // GP64 Register Class...
2423  const MCPhysReg GP64[] = {
2424    Mips::GP_64,
2425  };
2426
2427  // GP64 Bit set.
2428  const uint8_t GP64Bits[] = {
2429    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2430  };
2431
2432  // GPR64_with_sub_32_in_CPURAReg Register Class...
2433  const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
2434    Mips::RA_64,
2435  };
2436
2437  // GPR64_with_sub_32_in_CPURAReg Bit set.
2438  const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
2439    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2440  };
2441
2442  // GPR64_with_sub_32_in_GPR32ZERO Register Class...
2443  const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {
2444    Mips::ZERO_64,
2445  };
2446
2447  // GPR64_with_sub_32_in_GPR32ZERO Bit set.
2448  const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = {
2449    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2450  };
2451
2452  // HI64 Register Class...
2453  const MCPhysReg HI64[] = {
2454    Mips::HI0_64,
2455  };
2456
2457  // HI64 Bit set.
2458  const uint8_t HI64Bits[] = {
2459    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2460  };
2461
2462  // LO64 Register Class...
2463  const MCPhysReg LO64[] = {
2464    Mips::LO0_64,
2465  };
2466
2467  // LO64 Bit set.
2468  const uint8_t LO64Bits[] = {
2469    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2470  };
2471
2472  // SP64 Register Class...
2473  const MCPhysReg SP64[] = {
2474    Mips::SP_64,
2475  };
2476
2477  // SP64 Bit set.
2478  const uint8_t SP64Bits[] = {
2479    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2480  };
2481
2482  // MSA128B Register Class...
2483  const MCPhysReg MSA128B[] = {
2484    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2485  };
2486
2487  // MSA128B Bit set.
2488  const uint8_t MSA128BBits[] = {
2489    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2490  };
2491
2492  // MSA128D Register Class...
2493  const MCPhysReg MSA128D[] = {
2494    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2495  };
2496
2497  // MSA128D Bit set.
2498  const uint8_t MSA128DBits[] = {
2499    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2500  };
2501
2502  // MSA128H Register Class...
2503  const MCPhysReg MSA128H[] = {
2504    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2505  };
2506
2507  // MSA128H Bit set.
2508  const uint8_t MSA128HBits[] = {
2509    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2510  };
2511
2512  // MSA128W Register Class...
2513  const MCPhysReg MSA128W[] = {
2514    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2515  };
2516
2517  // MSA128W Bit set.
2518  const uint8_t MSA128WBits[] = {
2519    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2520  };
2521
2522  // MSA128B_with_sub_64_in_OddSP Register Class...
2523  const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = {
2524    Mips::W1, Mips::W3, Mips::W5, Mips::W7, Mips::W9, Mips::W11, Mips::W13, Mips::W15, Mips::W17, Mips::W19, Mips::W21, Mips::W23, Mips::W25, Mips::W27, Mips::W29, Mips::W31,
2525  };
2526
2527  // MSA128B_with_sub_64_in_OddSP Bit set.
2528  const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = {
2529    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
2530  };
2531
2532  // MSA128WEvens Register Class...
2533  const MCPhysReg MSA128WEvens[] = {
2534    Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30,
2535  };
2536
2537  // MSA128WEvens Bit set.
2538  const uint8_t MSA128WEvensBits[] = {
2539    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,
2540  };
2541
2542  // ACC128 Register Class...
2543  const MCPhysReg ACC128[] = {
2544    Mips::AC0_64,
2545  };
2546
2547  // ACC128 Bit set.
2548  const uint8_t ACC128Bits[] = {
2549    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
2550  };
2551
2552} // end anonymous namespace
2553
2554extern const char MipsRegClassStrings[] = {
2555  /* 0 */ 'C', 'O', 'P', '0', 0,
2556  /* 5 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', 'H', '3', '2', 0,
2557  /* 45 */ 'H', 'I', '3', '2', 0,
2558  /* 50 */ 'L', 'O', '3', '2', 0,
2559  /* 55 */ 'G', 'P', '3', '2', 0,
2560  /* 60 */ 'S', 'P', '3', '2', 0,
2561  /* 65 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', '3', '2', 0,
2562  /* 104 */ 'G', 'P', 'R', '3', '2', 0,
2563  /* 110 */ 'C', 'O', 'P', '2', 0,
2564  /* 115 */ 'C', 'O', 'P', '3', 0,
2565  /* 120 */ 'A', 'C', 'C', '6', '4', 0,
2566  /* 126 */ 'H', 'I', '6', '4', 0,
2567  /* 131 */ 'L', 'O', '6', '4', 0,
2568  /* 136 */ 'G', 'P', '6', '4', 0,
2569  /* 141 */ 'S', 'P', '6', '4', 0,
2570  /* 146 */ 'A', 'F', 'G', 'R', '6', '4', 0,
2571  /* 153 */ 'G', 'P', 'R', '6', '4', 0,
2572  /* 159 */ 'M', 'S', 'A', '1', '2', '8', 'F', '1', '6', 0,
2573  /* 169 */ 'G', 'P', 'R', 'M', 'M', '1', '6', 0,
2574  /* 177 */ 'A', 'C', 'C', '1', '2', '8', 0,
2575  /* 184 */ 'M', 'S', 'A', '1', '2', '8', 'B', 0,
2576  /* 192 */ 'F', 'C', 'C', 0,
2577  /* 196 */ 'D', 'S', 'P', 'C', 'C', 0,
2578  /* 202 */ 'F', 'G', 'R', 'C', 'C', 0,
2579  /* 208 */ 'M', 'S', 'A', '1', '2', '8', 'D', 0,
2580  /* 216 */ 'M', 'S', 'A', '1', '2', '8', 'H', 0,
2581  /* 224 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'M', 'P', 'L', 0,
2582  /* 235 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'Z', 'E', 'R', 'O', 0,
2583  /* 266 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', 0,
2584  /* 300 */ 'H', 'I', '3', '2', 'D', 'S', 'P', 0,
2585  /* 308 */ 'L', 'O', '3', '2', 'D', 'S', 'P', 0,
2586  /* 316 */ 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0,
2587  /* 325 */ 'F', 'G', 'R', 'H', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
2588  /* 342 */ 'F', 'G', 'R', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
2589  /* 358 */ 'A', 'F', 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
2590  /* 375 */ 'M', 'S', 'A', '1', '2', '8', 'F', '1', '6', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'O', 'd', 'd', 'S', 'P', 0,
2591  /* 406 */ 'M', 'S', 'A', '1', '2', '8', 'B', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'O', 'd', 'd', 'S', 'P', 0,
2592  /* 435 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 'P', 'l', 'u', 's', 'S', 'P', 0,
2593  /* 472 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'P', 0,
2594  /* 481 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
2595  /* 532 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
2596  /* 580 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
2597  /* 614 */ 'C', 'C', 'R', 0,
2598  /* 618 */ 'D', 'S', 'P', 'R', 0,
2599  /* 623 */ 'M', 'S', 'A', '1', '2', '8', 'W', 0,
2600  /* 631 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', 'R', 'A', 'R', 'e', 'g', 0,
2601  /* 661 */ 'C', 'P', 'U', 'S', 'P', 'R', 'e', 'g', 0,
2602  /* 670 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', 0,
2603  /* 688 */ 'M', 'S', 'A', 'C', 't', 'r', 'l', 0,
2604  /* 696 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2605  /* 746 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2606  /* 810 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2607  /* 857 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2608  /* 890 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 0,
2609  /* 921 */ 'H', 'W', 'R', 'e', 'g', 's', 0,
2610  /* 928 */ 'M', 'S', 'A', '1', '2', '8', 'W', 'E', 'v', 'e', 'n', 's', 0,
2611};
2612
2613extern const MCRegisterClass MipsMCRegisterClasses[] = {
2614  { MSA128F16, MSA128F16Bits, 159, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 2, 1, true },
2615  { MSA128F16_with_sub_64_in_OddSP, MSA128F16_with_sub_64_in_OddSPBits, 375, 16, sizeof(MSA128F16_with_sub_64_in_OddSPBits), Mips::MSA128F16_with_sub_64_in_OddSPRegClassID, 2, 1, true },
2616  { OddSP, OddSPBits, 336, 56, sizeof(OddSPBits), Mips::OddSPRegClassID, 4, 1, false },
2617  { CCR, CCRBits, 614, 32, sizeof(CCRBits), Mips::CCRRegClassID, 4, 1, false },
2618  { COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 4, 1, false },
2619  { COP2, COP2Bits, 110, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 4, 1, false },
2620  { COP3, COP3Bits, 115, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 4, 1, false },
2621  { DSPR, DSPRBits, 618, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 4, 1, true },
2622  { FGR32, FGR32Bits, 98, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 4, 1, true },
2623  { FGRCC, FGRCCBits, 202, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 4, 1, true },
2624  { FGRH32, FGRH32Bits, 38, 32, sizeof(FGRH32Bits), Mips::FGRH32RegClassID, 4, 1, false },
2625  { GPR32, GPR32Bits, 104, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 4, 1, true },
2626  { HWRegs, HWRegsBits, 921, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 4, 1, false },
2627  { GPR32NONZERO, GPR32NONZEROBits, 287, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 4, 1, true },
2628  { OddSP_with_sub_hi, OddSP_with_sub_hiBits, 670, 24, sizeof(OddSP_with_sub_hiBits), Mips::OddSP_with_sub_hiRegClassID, 4, 1, false },
2629  { FGR32_and_OddSP, FGR32_and_OddSPBits, 342, 16, sizeof(FGR32_and_OddSPBits), Mips::FGR32_and_OddSPRegClassID, 4, 1, true },
2630  { FGRH32_and_OddSP, FGRH32_and_OddSPBits, 325, 16, sizeof(FGRH32_and_OddSPBits), Mips::FGRH32_and_OddSPRegClassID, 4, 1, false },
2631  { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, 5, 16, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits), Mips::OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID, 4, 1, false },
2632  { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 456, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 4, 1, true },
2633  { CPU16Regs, CPU16RegsBits, 911, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 4, 1, true },
2634  { FCC, FCCBits, 192, 8, sizeof(FCCBits), Mips::FCCRegClassID, 4, 1, false },
2635  { GPRMM16, GPRMM16Bits, 169, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 4, 1, true },
2636  { GPRMM16MoveP, GPRMM16MovePBits, 519, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 4, 1, true },
2637  { GPRMM16Zero, GPRMM16ZeroBits, 734, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 4, 1, true },
2638  { MSACtrl, MSACtrlBits, 688, 8, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 4, 1, true },
2639  { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, 65, 8, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits), Mips::OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID, 4, 1, false },
2640  { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 784, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 1, true },
2641  { GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 502, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 4, 1, true },
2642  { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 553, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 4, 1, true },
2643  { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 717, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 4, 1, true },
2644  { HI32DSP, HI32DSPBits, 300, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 4, 1, true },
2645  { LO32DSP, LO32DSPBits, 308, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 4, 1, true },
2646  { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 767, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 1, true },
2647  { CPURAReg, CPURARegBits, 652, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 4, 1, false },
2648  { CPUSPReg, CPUSPRegBits, 661, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 4, 1, false },
2649  { DSPCC, DSPCCBits, 196, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 4, 1, true },
2650  { GP32, GP32Bits, 55, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 4, 1, false },
2651  { GPR32ZERO, GPR32ZEROBits, 256, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 4, 1, true },
2652  { HI32, HI32Bits, 45, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 4, 1, true },
2653  { LO32, LO32Bits, 50, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 4, 1, true },
2654  { SP32, SP32Bits, 60, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 4, 1, false },
2655  { FGR64, FGR64Bits, 147, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 8, 1, true },
2656  { GPR64, GPR64Bits, 153, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 8, 1, true },
2657  { GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 266, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 8, 1, true },
2658  { AFGR64, AFGR64Bits, 146, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 8, 1, true },
2659  { FGR64_and_OddSP, FGR64_and_OddSPBits, 359, 16, sizeof(FGR64_and_OddSPBits), Mips::FGR64_and_OddSPRegClassID, 8, 1, true },
2660  { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 435, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 8, 1, true },
2661  { AFGR64_and_OddSP, AFGR64_and_OddSPBits, 358, 8, sizeof(AFGR64_and_OddSPBits), Mips::AFGR64_and_OddSPRegClassID, 8, 1, true },
2662  { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 890, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 8, 1, true },
2663  { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 580, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 8, 1, true },
2664  { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 857, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 8, 1, true },
2665  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 810, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 1, true },
2666  { GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 481, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 8, 1, true },
2667  { ACC64DSP, ACC64DSPBits, 316, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 8, 1, true },
2668  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 532, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 8, 1, true },
2669  { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 696, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 8, 1, true },
2670  { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 746, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 1, true },
2671  { OCTEON_MPL, OCTEON_MPLBits, 224, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 8, 1, false },
2672  { OCTEON_P, OCTEON_PBits, 472, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 8, 1, false },
2673  { ACC64, ACC64Bits, 120, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 8, 1, true },
2674  { GP64, GP64Bits, 136, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 8, 1, false },
2675  { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 631, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 8, 1, true },
2676  { GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 235, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 8, 1, true },
2677  { HI64, HI64Bits, 126, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 8, 1, true },
2678  { LO64, LO64Bits, 131, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 8, 1, true },
2679  { SP64, SP64Bits, 141, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 8, 1, false },
2680  { MSA128B, MSA128BBits, 184, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 16, 1, true },
2681  { MSA128D, MSA128DBits, 208, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 16, 1, true },
2682  { MSA128H, MSA128HBits, 216, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 16, 1, true },
2683  { MSA128W, MSA128WBits, 623, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 16, 1, true },
2684  { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, 406, 16, sizeof(MSA128B_with_sub_64_in_OddSPBits), Mips::MSA128B_with_sub_64_in_OddSPRegClassID, 16, 1, true },
2685  { MSA128WEvens, MSA128WEvensBits, 928, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 16, 1, true },
2686  { ACC128, ACC128Bits, 177, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 16, 1, true },
2687};
2688
2689// Mips Dwarf<->LLVM register mappings.
2690extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {
2691  { 0U, Mips::ZERO_64 },
2692  { 1U, Mips::AT_64 },
2693  { 2U, Mips::V0_64 },
2694  { 3U, Mips::V1_64 },
2695  { 4U, Mips::A0_64 },
2696  { 5U, Mips::A1_64 },
2697  { 6U, Mips::A2_64 },
2698  { 7U, Mips::A3_64 },
2699  { 8U, Mips::T0_64 },
2700  { 9U, Mips::T1_64 },
2701  { 10U, Mips::T2_64 },
2702  { 11U, Mips::T3_64 },
2703  { 12U, Mips::T4_64 },
2704  { 13U, Mips::T5_64 },
2705  { 14U, Mips::T6_64 },
2706  { 15U, Mips::T7_64 },
2707  { 16U, Mips::S0_64 },
2708  { 17U, Mips::S1_64 },
2709  { 18U, Mips::S2_64 },
2710  { 19U, Mips::S3_64 },
2711  { 20U, Mips::S4_64 },
2712  { 21U, Mips::S5_64 },
2713  { 22U, Mips::S6_64 },
2714  { 23U, Mips::S7_64 },
2715  { 24U, Mips::T8_64 },
2716  { 25U, Mips::T9_64 },
2717  { 26U, Mips::K0_64 },
2718  { 27U, Mips::K1_64 },
2719  { 28U, Mips::GP_64 },
2720  { 29U, Mips::SP_64 },
2721  { 30U, Mips::FP_64 },
2722  { 31U, Mips::RA_64 },
2723  { 32U, Mips::D0_64 },
2724  { 33U, Mips::D1_64 },
2725  { 34U, Mips::D2_64 },
2726  { 35U, Mips::D3_64 },
2727  { 36U, Mips::D4_64 },
2728  { 37U, Mips::D5_64 },
2729  { 38U, Mips::D6_64 },
2730  { 39U, Mips::D7_64 },
2731  { 40U, Mips::D8_64 },
2732  { 41U, Mips::D9_64 },
2733  { 42U, Mips::D10_64 },
2734  { 43U, Mips::D11_64 },
2735  { 44U, Mips::D12_64 },
2736  { 45U, Mips::D13_64 },
2737  { 46U, Mips::D14_64 },
2738  { 47U, Mips::D15_64 },
2739  { 48U, Mips::D16_64 },
2740  { 49U, Mips::D17_64 },
2741  { 50U, Mips::D18_64 },
2742  { 51U, Mips::D19_64 },
2743  { 52U, Mips::D20_64 },
2744  { 53U, Mips::D21_64 },
2745  { 54U, Mips::D22_64 },
2746  { 55U, Mips::D23_64 },
2747  { 56U, Mips::D24_64 },
2748  { 57U, Mips::D25_64 },
2749  { 58U, Mips::D26_64 },
2750  { 59U, Mips::D27_64 },
2751  { 60U, Mips::D28_64 },
2752  { 61U, Mips::D29_64 },
2753  { 62U, Mips::D30_64 },
2754  { 63U, Mips::D31_64 },
2755  { 64U, Mips::HI0 },
2756  { 65U, Mips::LO0 },
2757  { 176U, Mips::HI1 },
2758  { 177U, Mips::LO1 },
2759  { 178U, Mips::HI2 },
2760  { 179U, Mips::LO2 },
2761  { 180U, Mips::HI3 },
2762  { 181U, Mips::LO3 },
2763};
2764extern const unsigned MipsDwarfFlavour0Dwarf2LSize = array_lengthof(MipsDwarfFlavour0Dwarf2L);
2765
2766extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {
2767  { 0U, Mips::ZERO_64 },
2768  { 1U, Mips::AT_64 },
2769  { 2U, Mips::V0_64 },
2770  { 3U, Mips::V1_64 },
2771  { 4U, Mips::A0_64 },
2772  { 5U, Mips::A1_64 },
2773  { 6U, Mips::A2_64 },
2774  { 7U, Mips::A3_64 },
2775  { 8U, Mips::T0_64 },
2776  { 9U, Mips::T1_64 },
2777  { 10U, Mips::T2_64 },
2778  { 11U, Mips::T3_64 },
2779  { 12U, Mips::T4_64 },
2780  { 13U, Mips::T5_64 },
2781  { 14U, Mips::T6_64 },
2782  { 15U, Mips::T7_64 },
2783  { 16U, Mips::S0_64 },
2784  { 17U, Mips::S1_64 },
2785  { 18U, Mips::S2_64 },
2786  { 19U, Mips::S3_64 },
2787  { 20U, Mips::S4_64 },
2788  { 21U, Mips::S5_64 },
2789  { 22U, Mips::S6_64 },
2790  { 23U, Mips::S7_64 },
2791  { 24U, Mips::T8_64 },
2792  { 25U, Mips::T9_64 },
2793  { 26U, Mips::K0_64 },
2794  { 27U, Mips::K1_64 },
2795  { 28U, Mips::GP_64 },
2796  { 29U, Mips::SP_64 },
2797  { 30U, Mips::FP_64 },
2798  { 31U, Mips::RA_64 },
2799  { 32U, Mips::D0_64 },
2800  { 33U, Mips::D1_64 },
2801  { 34U, Mips::D2_64 },
2802  { 35U, Mips::D3_64 },
2803  { 36U, Mips::D4_64 },
2804  { 37U, Mips::D5_64 },
2805  { 38U, Mips::D6_64 },
2806  { 39U, Mips::D7_64 },
2807  { 40U, Mips::D8_64 },
2808  { 41U, Mips::D9_64 },
2809  { 42U, Mips::D10_64 },
2810  { 43U, Mips::D11_64 },
2811  { 44U, Mips::D12_64 },
2812  { 45U, Mips::D13_64 },
2813  { 46U, Mips::D14_64 },
2814  { 47U, Mips::D15_64 },
2815  { 48U, Mips::D16_64 },
2816  { 49U, Mips::D17_64 },
2817  { 50U, Mips::D18_64 },
2818  { 51U, Mips::D19_64 },
2819  { 52U, Mips::D20_64 },
2820  { 53U, Mips::D21_64 },
2821  { 54U, Mips::D22_64 },
2822  { 55U, Mips::D23_64 },
2823  { 56U, Mips::D24_64 },
2824  { 57U, Mips::D25_64 },
2825  { 58U, Mips::D26_64 },
2826  { 59U, Mips::D27_64 },
2827  { 60U, Mips::D28_64 },
2828  { 61U, Mips::D29_64 },
2829  { 62U, Mips::D30_64 },
2830  { 63U, Mips::D31_64 },
2831  { 64U, Mips::HI0 },
2832  { 65U, Mips::LO0 },
2833  { 176U, Mips::HI1 },
2834  { 177U, Mips::LO1 },
2835  { 178U, Mips::HI2 },
2836  { 179U, Mips::LO2 },
2837  { 180U, Mips::HI3 },
2838  { 181U, Mips::LO3 },
2839};
2840extern const unsigned MipsEHFlavour0Dwarf2LSize = array_lengthof(MipsEHFlavour0Dwarf2L);
2841
2842extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {
2843  { Mips::AT, 1U },
2844  { Mips::FP, 30U },
2845  { Mips::GP, 28U },
2846  { Mips::RA, 31U },
2847  { Mips::SP, 29U },
2848  { Mips::ZERO, 0U },
2849  { Mips::A0, 4U },
2850  { Mips::A1, 5U },
2851  { Mips::A2, 6U },
2852  { Mips::A3, 7U },
2853  { Mips::AT_64, 1U },
2854  { Mips::F0, 32U },
2855  { Mips::F1, 33U },
2856  { Mips::F2, 34U },
2857  { Mips::F3, 35U },
2858  { Mips::F4, 36U },
2859  { Mips::F5, 37U },
2860  { Mips::F6, 38U },
2861  { Mips::F7, 39U },
2862  { Mips::F8, 40U },
2863  { Mips::F9, 41U },
2864  { Mips::F10, 42U },
2865  { Mips::F11, 43U },
2866  { Mips::F12, 44U },
2867  { Mips::F13, 45U },
2868  { Mips::F14, 46U },
2869  { Mips::F15, 47U },
2870  { Mips::F16, 48U },
2871  { Mips::F17, 49U },
2872  { Mips::F18, 50U },
2873  { Mips::F19, 51U },
2874  { Mips::F20, 52U },
2875  { Mips::F21, 53U },
2876  { Mips::F22, 54U },
2877  { Mips::F23, 55U },
2878  { Mips::F24, 56U },
2879  { Mips::F25, 57U },
2880  { Mips::F26, 58U },
2881  { Mips::F27, 59U },
2882  { Mips::F28, 60U },
2883  { Mips::F29, 61U },
2884  { Mips::F30, 62U },
2885  { Mips::F31, 63U },
2886  { Mips::FP_64, 30U },
2887  { Mips::F_HI0, 32U },
2888  { Mips::F_HI1, 33U },
2889  { Mips::F_HI2, 34U },
2890  { Mips::F_HI3, 35U },
2891  { Mips::F_HI4, 36U },
2892  { Mips::F_HI5, 37U },
2893  { Mips::F_HI6, 38U },
2894  { Mips::F_HI7, 39U },
2895  { Mips::F_HI8, 40U },
2896  { Mips::F_HI9, 41U },
2897  { Mips::F_HI10, 42U },
2898  { Mips::F_HI11, 43U },
2899  { Mips::F_HI12, 44U },
2900  { Mips::F_HI13, 45U },
2901  { Mips::F_HI14, 46U },
2902  { Mips::F_HI15, 47U },
2903  { Mips::F_HI16, 48U },
2904  { Mips::F_HI17, 49U },
2905  { Mips::F_HI18, 50U },
2906  { Mips::F_HI19, 51U },
2907  { Mips::F_HI20, 52U },
2908  { Mips::F_HI21, 53U },
2909  { Mips::F_HI22, 54U },
2910  { Mips::F_HI23, 55U },
2911  { Mips::F_HI24, 56U },
2912  { Mips::F_HI25, 57U },
2913  { Mips::F_HI26, 58U },
2914  { Mips::F_HI27, 59U },
2915  { Mips::F_HI28, 60U },
2916  { Mips::F_HI29, 61U },
2917  { Mips::F_HI30, 62U },
2918  { Mips::F_HI31, 63U },
2919  { Mips::GP_64, 28U },
2920  { Mips::HI0, 64U },
2921  { Mips::HI1, 176U },
2922  { Mips::HI2, 178U },
2923  { Mips::HI3, 180U },
2924  { Mips::K0, 26U },
2925  { Mips::K1, 27U },
2926  { Mips::LO0, 65U },
2927  { Mips::LO1, 177U },
2928  { Mips::LO2, 179U },
2929  { Mips::LO3, 181U },
2930  { Mips::RA_64, 31U },
2931  { Mips::S0, 16U },
2932  { Mips::S1, 17U },
2933  { Mips::S2, 18U },
2934  { Mips::S3, 19U },
2935  { Mips::S4, 20U },
2936  { Mips::S5, 21U },
2937  { Mips::S6, 22U },
2938  { Mips::S7, 23U },
2939  { Mips::SP_64, 29U },
2940  { Mips::T0, 8U },
2941  { Mips::T1, 9U },
2942  { Mips::T2, 10U },
2943  { Mips::T3, 11U },
2944  { Mips::T4, 12U },
2945  { Mips::T5, 13U },
2946  { Mips::T6, 14U },
2947  { Mips::T7, 15U },
2948  { Mips::T8, 24U },
2949  { Mips::T9, 25U },
2950  { Mips::V0, 2U },
2951  { Mips::V1, 3U },
2952  { Mips::W0, 32U },
2953  { Mips::W1, 33U },
2954  { Mips::W2, 34U },
2955  { Mips::W3, 35U },
2956  { Mips::W4, 36U },
2957  { Mips::W5, 37U },
2958  { Mips::W6, 38U },
2959  { Mips::W7, 39U },
2960  { Mips::W8, 40U },
2961  { Mips::W9, 41U },
2962  { Mips::W10, 42U },
2963  { Mips::W11, 43U },
2964  { Mips::W12, 44U },
2965  { Mips::W13, 45U },
2966  { Mips::W14, 46U },
2967  { Mips::W15, 47U },
2968  { Mips::W16, 48U },
2969  { Mips::W17, 49U },
2970  { Mips::W18, 50U },
2971  { Mips::W19, 51U },
2972  { Mips::W20, 52U },
2973  { Mips::W21, 53U },
2974  { Mips::W22, 54U },
2975  { Mips::W23, 55U },
2976  { Mips::W24, 56U },
2977  { Mips::W25, 57U },
2978  { Mips::W26, 58U },
2979  { Mips::W27, 59U },
2980  { Mips::W28, 60U },
2981  { Mips::W29, 61U },
2982  { Mips::W30, 62U },
2983  { Mips::W31, 63U },
2984  { Mips::ZERO_64, 0U },
2985  { Mips::A0_64, 4U },
2986  { Mips::A1_64, 5U },
2987  { Mips::A2_64, 6U },
2988  { Mips::A3_64, 7U },
2989  { Mips::D0_64, 32U },
2990  { Mips::D1_64, 33U },
2991  { Mips::D2_64, 34U },
2992  { Mips::D3_64, 35U },
2993  { Mips::D4_64, 36U },
2994  { Mips::D5_64, 37U },
2995  { Mips::D6_64, 38U },
2996  { Mips::D7_64, 39U },
2997  { Mips::D8_64, 40U },
2998  { Mips::D9_64, 41U },
2999  { Mips::D10_64, 42U },
3000  { Mips::D11_64, 43U },
3001  { Mips::D12_64, 44U },
3002  { Mips::D13_64, 45U },
3003  { Mips::D14_64, 46U },
3004  { Mips::D15_64, 47U },
3005  { Mips::D16_64, 48U },
3006  { Mips::D17_64, 49U },
3007  { Mips::D18_64, 50U },
3008  { Mips::D19_64, 51U },
3009  { Mips::D20_64, 52U },
3010  { Mips::D21_64, 53U },
3011  { Mips::D22_64, 54U },
3012  { Mips::D23_64, 55U },
3013  { Mips::D24_64, 56U },
3014  { Mips::D25_64, 57U },
3015  { Mips::D26_64, 58U },
3016  { Mips::D27_64, 59U },
3017  { Mips::D28_64, 60U },
3018  { Mips::D29_64, 61U },
3019  { Mips::D30_64, 62U },
3020  { Mips::D31_64, 63U },
3021  { Mips::K0_64, 26U },
3022  { Mips::K1_64, 27U },
3023  { Mips::S0_64, 16U },
3024  { Mips::S1_64, 17U },
3025  { Mips::S2_64, 18U },
3026  { Mips::S3_64, 19U },
3027  { Mips::S4_64, 20U },
3028  { Mips::S5_64, 21U },
3029  { Mips::S6_64, 22U },
3030  { Mips::S7_64, 23U },
3031  { Mips::T0_64, 8U },
3032  { Mips::T1_64, 9U },
3033  { Mips::T2_64, 10U },
3034  { Mips::T3_64, 11U },
3035  { Mips::T4_64, 12U },
3036  { Mips::T5_64, 13U },
3037  { Mips::T6_64, 14U },
3038  { Mips::T7_64, 15U },
3039  { Mips::T8_64, 24U },
3040  { Mips::T9_64, 25U },
3041  { Mips::V0_64, 2U },
3042  { Mips::V1_64, 3U },
3043};
3044extern const unsigned MipsDwarfFlavour0L2DwarfSize = array_lengthof(MipsDwarfFlavour0L2Dwarf);
3045
3046extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {
3047  { Mips::AT, 1U },
3048  { Mips::FP, 30U },
3049  { Mips::GP, 28U },
3050  { Mips::RA, 31U },
3051  { Mips::SP, 29U },
3052  { Mips::ZERO, 0U },
3053  { Mips::A0, 4U },
3054  { Mips::A1, 5U },
3055  { Mips::A2, 6U },
3056  { Mips::A3, 7U },
3057  { Mips::AT_64, 1U },
3058  { Mips::F0, 32U },
3059  { Mips::F1, 33U },
3060  { Mips::F2, 34U },
3061  { Mips::F3, 35U },
3062  { Mips::F4, 36U },
3063  { Mips::F5, 37U },
3064  { Mips::F6, 38U },
3065  { Mips::F7, 39U },
3066  { Mips::F8, 40U },
3067  { Mips::F9, 41U },
3068  { Mips::F10, 42U },
3069  { Mips::F11, 43U },
3070  { Mips::F12, 44U },
3071  { Mips::F13, 45U },
3072  { Mips::F14, 46U },
3073  { Mips::F15, 47U },
3074  { Mips::F16, 48U },
3075  { Mips::F17, 49U },
3076  { Mips::F18, 50U },
3077  { Mips::F19, 51U },
3078  { Mips::F20, 52U },
3079  { Mips::F21, 53U },
3080  { Mips::F22, 54U },
3081  { Mips::F23, 55U },
3082  { Mips::F24, 56U },
3083  { Mips::F25, 57U },
3084  { Mips::F26, 58U },
3085  { Mips::F27, 59U },
3086  { Mips::F28, 60U },
3087  { Mips::F29, 61U },
3088  { Mips::F30, 62U },
3089  { Mips::F31, 63U },
3090  { Mips::FP_64, 30U },
3091  { Mips::F_HI0, 32U },
3092  { Mips::F_HI1, 33U },
3093  { Mips::F_HI2, 34U },
3094  { Mips::F_HI3, 35U },
3095  { Mips::F_HI4, 36U },
3096  { Mips::F_HI5, 37U },
3097  { Mips::F_HI6, 38U },
3098  { Mips::F_HI7, 39U },
3099  { Mips::F_HI8, 40U },
3100  { Mips::F_HI9, 41U },
3101  { Mips::F_HI10, 42U },
3102  { Mips::F_HI11, 43U },
3103  { Mips::F_HI12, 44U },
3104  { Mips::F_HI13, 45U },
3105  { Mips::F_HI14, 46U },
3106  { Mips::F_HI15, 47U },
3107  { Mips::F_HI16, 48U },
3108  { Mips::F_HI17, 49U },
3109  { Mips::F_HI18, 50U },
3110  { Mips::F_HI19, 51U },
3111  { Mips::F_HI20, 52U },
3112  { Mips::F_HI21, 53U },
3113  { Mips::F_HI22, 54U },
3114  { Mips::F_HI23, 55U },
3115  { Mips::F_HI24, 56U },
3116  { Mips::F_HI25, 57U },
3117  { Mips::F_HI26, 58U },
3118  { Mips::F_HI27, 59U },
3119  { Mips::F_HI28, 60U },
3120  { Mips::F_HI29, 61U },
3121  { Mips::F_HI30, 62U },
3122  { Mips::F_HI31, 63U },
3123  { Mips::GP_64, 28U },
3124  { Mips::HI0, 64U },
3125  { Mips::HI1, 176U },
3126  { Mips::HI2, 178U },
3127  { Mips::HI3, 180U },
3128  { Mips::K0, 26U },
3129  { Mips::K1, 27U },
3130  { Mips::LO0, 65U },
3131  { Mips::LO1, 177U },
3132  { Mips::LO2, 179U },
3133  { Mips::LO3, 181U },
3134  { Mips::RA_64, 31U },
3135  { Mips::S0, 16U },
3136  { Mips::S1, 17U },
3137  { Mips::S2, 18U },
3138  { Mips::S3, 19U },
3139  { Mips::S4, 20U },
3140  { Mips::S5, 21U },
3141  { Mips::S6, 22U },
3142  { Mips::S7, 23U },
3143  { Mips::SP_64, 29U },
3144  { Mips::T0, 8U },
3145  { Mips::T1, 9U },
3146  { Mips::T2, 10U },
3147  { Mips::T3, 11U },
3148  { Mips::T4, 12U },
3149  { Mips::T5, 13U },
3150  { Mips::T6, 14U },
3151  { Mips::T7, 15U },
3152  { Mips::T8, 24U },
3153  { Mips::T9, 25U },
3154  { Mips::V0, 2U },
3155  { Mips::V1, 3U },
3156  { Mips::W0, 32U },
3157  { Mips::W1, 33U },
3158  { Mips::W2, 34U },
3159  { Mips::W3, 35U },
3160  { Mips::W4, 36U },
3161  { Mips::W5, 37U },
3162  { Mips::W6, 38U },
3163  { Mips::W7, 39U },
3164  { Mips::W8, 40U },
3165  { Mips::W9, 41U },
3166  { Mips::W10, 42U },
3167  { Mips::W11, 43U },
3168  { Mips::W12, 44U },
3169  { Mips::W13, 45U },
3170  { Mips::W14, 46U },
3171  { Mips::W15, 47U },
3172  { Mips::W16, 48U },
3173  { Mips::W17, 49U },
3174  { Mips::W18, 50U },
3175  { Mips::W19, 51U },
3176  { Mips::W20, 52U },
3177  { Mips::W21, 53U },
3178  { Mips::W22, 54U },
3179  { Mips::W23, 55U },
3180  { Mips::W24, 56U },
3181  { Mips::W25, 57U },
3182  { Mips::W26, 58U },
3183  { Mips::W27, 59U },
3184  { Mips::W28, 60U },
3185  { Mips::W29, 61U },
3186  { Mips::W30, 62U },
3187  { Mips::W31, 63U },
3188  { Mips::ZERO_64, 0U },
3189  { Mips::A0_64, 4U },
3190  { Mips::A1_64, 5U },
3191  { Mips::A2_64, 6U },
3192  { Mips::A3_64, 7U },
3193  { Mips::D0_64, 32U },
3194  { Mips::D1_64, 33U },
3195  { Mips::D2_64, 34U },
3196  { Mips::D3_64, 35U },
3197  { Mips::D4_64, 36U },
3198  { Mips::D5_64, 37U },
3199  { Mips::D6_64, 38U },
3200  { Mips::D7_64, 39U },
3201  { Mips::D8_64, 40U },
3202  { Mips::D9_64, 41U },
3203  { Mips::D10_64, 42U },
3204  { Mips::D11_64, 43U },
3205  { Mips::D12_64, 44U },
3206  { Mips::D13_64, 45U },
3207  { Mips::D14_64, 46U },
3208  { Mips::D15_64, 47U },
3209  { Mips::D16_64, 48U },
3210  { Mips::D17_64, 49U },
3211  { Mips::D18_64, 50U },
3212  { Mips::D19_64, 51U },
3213  { Mips::D20_64, 52U },
3214  { Mips::D21_64, 53U },
3215  { Mips::D22_64, 54U },
3216  { Mips::D23_64, 55U },
3217  { Mips::D24_64, 56U },
3218  { Mips::D25_64, 57U },
3219  { Mips::D26_64, 58U },
3220  { Mips::D27_64, 59U },
3221  { Mips::D28_64, 60U },
3222  { Mips::D29_64, 61U },
3223  { Mips::D30_64, 62U },
3224  { Mips::D31_64, 63U },
3225  { Mips::K0_64, 26U },
3226  { Mips::K1_64, 27U },
3227  { Mips::S0_64, 16U },
3228  { Mips::S1_64, 17U },
3229  { Mips::S2_64, 18U },
3230  { Mips::S3_64, 19U },
3231  { Mips::S4_64, 20U },
3232  { Mips::S5_64, 21U },
3233  { Mips::S6_64, 22U },
3234  { Mips::S7_64, 23U },
3235  { Mips::T0_64, 8U },
3236  { Mips::T1_64, 9U },
3237  { Mips::T2_64, 10U },
3238  { Mips::T3_64, 11U },
3239  { Mips::T4_64, 12U },
3240  { Mips::T5_64, 13U },
3241  { Mips::T6_64, 14U },
3242  { Mips::T7_64, 15U },
3243  { Mips::T8_64, 24U },
3244  { Mips::T9_64, 25U },
3245  { Mips::V0_64, 2U },
3246  { Mips::V1_64, 3U },
3247};
3248extern const unsigned MipsEHFlavour0L2DwarfSize = array_lengthof(MipsEHFlavour0L2Dwarf);
3249
3250extern const uint16_t MipsRegEncodingTable[] = {
3251  0,
3252  1,
3253  0,
3254  0,
3255  0,
3256  0,
3257  0,
3258  0,
3259  30,
3260  28,
3261  2,
3262  1,
3263  0,
3264  6,
3265  4,
3266  5,
3267  3,
3268  7,
3269  0,
3270  31,
3271  29,
3272  0,
3273  4,
3274  5,
3275  6,
3276  7,
3277  0,
3278  1,
3279  2,
3280  3,
3281  1,
3282  0,
3283  1,
3284  2,
3285  3,
3286  4,
3287  5,
3288  6,
3289  7,
3290  8,
3291  9,
3292  0,
3293  1,
3294  2,
3295  3,
3296  4,
3297  5,
3298  6,
3299  7,
3300  8,
3301  9,
3302  0,
3303  1,
3304  2,
3305  3,
3306  4,
3307  5,
3308  6,
3309  7,
3310  8,
3311  9,
3312  10,
3313  11,
3314  12,
3315  13,
3316  14,
3317  15,
3318  16,
3319  17,
3320  18,
3321  19,
3322  20,
3323  21,
3324  22,
3325  23,
3326  24,
3327  25,
3328  26,
3329  27,
3330  28,
3331  29,
3332  30,
3333  31,
3334  10,
3335  11,
3336  12,
3337  13,
3338  14,
3339  15,
3340  16,
3341  17,
3342  18,
3343  19,
3344  20,
3345  21,
3346  22,
3347  23,
3348  24,
3349  25,
3350  26,
3351  27,
3352  28,
3353  29,
3354  30,
3355  31,
3356  10,
3357  11,
3358  12,
3359  13,
3360  14,
3361  15,
3362  16,
3363  17,
3364  18,
3365  19,
3366  20,
3367  21,
3368  22,
3369  23,
3370  24,
3371  25,
3372  26,
3373  27,
3374  28,
3375  29,
3376  30,
3377  31,
3378  0,
3379  2,
3380  4,
3381  6,
3382  8,
3383  10,
3384  12,
3385  14,
3386  16,
3387  18,
3388  20,
3389  22,
3390  24,
3391  26,
3392  28,
3393  30,
3394  0,
3395  0,
3396  0,
3397  0,
3398  0,
3399  1,
3400  2,
3401  3,
3402  4,
3403  5,
3404  6,
3405  7,
3406  8,
3407  9,
3408  10,
3409  11,
3410  12,
3411  13,
3412  14,
3413  15,
3414  16,
3415  17,
3416  18,
3417  19,
3418  20,
3419  21,
3420  22,
3421  23,
3422  24,
3423  25,
3424  26,
3425  27,
3426  28,
3427  29,
3428  30,
3429  31,
3430  0,
3431  1,
3432  2,
3433  3,
3434  4,
3435  5,
3436  6,
3437  7,
3438  0,
3439  1,
3440  2,
3441  3,
3442  4,
3443  5,
3444  6,
3445  7,
3446  8,
3447  9,
3448  10,
3449  11,
3450  12,
3451  13,
3452  14,
3453  15,
3454  16,
3455  17,
3456  18,
3457  19,
3458  20,
3459  21,
3460  22,
3461  23,
3462  24,
3463  25,
3464  26,
3465  27,
3466  28,
3467  29,
3468  30,
3469  31,
3470  30,
3471  0,
3472  1,
3473  2,
3474  3,
3475  4,
3476  5,
3477  6,
3478  7,
3479  8,
3480  9,
3481  10,
3482  11,
3483  12,
3484  13,
3485  14,
3486  15,
3487  16,
3488  17,
3489  18,
3490  19,
3491  20,
3492  21,
3493  22,
3494  23,
3495  24,
3496  25,
3497  26,
3498  27,
3499  28,
3500  29,
3501  30,
3502  31,
3503  28,
3504  0,
3505  1,
3506  2,
3507  3,
3508  0,
3509  1,
3510  2,
3511  3,
3512  4,
3513  5,
3514  6,
3515  7,
3516  8,
3517  9,
3518  10,
3519  11,
3520  12,
3521  13,
3522  14,
3523  15,
3524  16,
3525  17,
3526  18,
3527  19,
3528  20,
3529  21,
3530  22,
3531  23,
3532  24,
3533  25,
3534  26,
3535  27,
3536  28,
3537  29,
3538  30,
3539  31,
3540  26,
3541  27,
3542  0,
3543  1,
3544  2,
3545  3,
3546  0,
3547  1,
3548  2,
3549  0,
3550  1,
3551  2,
3552  31,
3553  16,
3554  17,
3555  18,
3556  19,
3557  20,
3558  21,
3559  22,
3560  23,
3561  29,
3562  8,
3563  9,
3564  10,
3565  11,
3566  12,
3567  13,
3568  14,
3569  15,
3570  24,
3571  25,
3572  2,
3573  3,
3574  0,
3575  1,
3576  2,
3577  3,
3578  4,
3579  5,
3580  6,
3581  7,
3582  8,
3583  9,
3584  10,
3585  11,
3586  12,
3587  13,
3588  14,
3589  15,
3590  16,
3591  17,
3592  18,
3593  19,
3594  20,
3595  21,
3596  22,
3597  23,
3598  24,
3599  25,
3600  26,
3601  27,
3602  28,
3603  29,
3604  30,
3605  31,
3606  0,
3607  4,
3608  5,
3609  6,
3610  7,
3611  0,
3612  0,
3613  1,
3614  2,
3615  3,
3616  4,
3617  5,
3618  6,
3619  7,
3620  8,
3621  9,
3622  10,
3623  11,
3624  12,
3625  13,
3626  14,
3627  15,
3628  16,
3629  17,
3630  18,
3631  19,
3632  20,
3633  21,
3634  22,
3635  23,
3636  24,
3637  25,
3638  26,
3639  27,
3640  28,
3641  29,
3642  30,
3643  31,
3644  0,
3645  0,
3646  26,
3647  27,
3648  0,
3649  16,
3650  17,
3651  18,
3652  19,
3653  20,
3654  21,
3655  22,
3656  23,
3657  8,
3658  9,
3659  10,
3660  11,
3661  12,
3662  13,
3663  14,
3664  15,
3665  24,
3666  25,
3667  2,
3668  3,
3669};
3670static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3671  RI->InitMCRegisterInfo(MipsRegDesc, 418, RA, PC, MipsMCRegisterClasses, 73, MipsRegUnitRoots, 297, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,
3672MipsSubRegIdxRanges, MipsRegEncodingTable);
3673
3674  switch (DwarfFlavour) {
3675  default:
3676    llvm_unreachable("Unknown DWARF flavour");
3677  case 0:
3678    RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
3679    break;
3680  }
3681  switch (EHFlavour) {
3682  default:
3683    llvm_unreachable("Unknown DWARF flavour");
3684  case 0:
3685    RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
3686    break;
3687  }
3688  switch (DwarfFlavour) {
3689  default:
3690    llvm_unreachable("Unknown DWARF flavour");
3691  case 0:
3692    RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
3693    break;
3694  }
3695  switch (EHFlavour) {
3696  default:
3697    llvm_unreachable("Unknown DWARF flavour");
3698  case 0:
3699    RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
3700    break;
3701  }
3702}
3703
3704} // end namespace llvm
3705
3706#endif // GET_REGINFO_MC_DESC
3707
3708/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3709|*                                                                            *|
3710|* Register Information Header Fragment                                       *|
3711|*                                                                            *|
3712|* Automatically generated file, do not edit!                                 *|
3713|*                                                                            *|
3714\*===----------------------------------------------------------------------===*/
3715
3716
3717#ifdef GET_REGINFO_HEADER
3718#undef GET_REGINFO_HEADER
3719
3720#include "llvm/CodeGen/TargetRegisterInfo.h"
3721
3722namespace llvm {
3723
3724class MipsFrameLowering;
3725
3726struct MipsGenRegisterInfo : public TargetRegisterInfo {
3727  explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
3728      unsigned PC = 0, unsigned HwMode = 0);
3729  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
3730  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3731  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3732  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3733  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3734  unsigned getRegUnitWeight(unsigned RegUnit) const override;
3735  unsigned getNumRegPressureSets() const override;
3736  const char *getRegPressureSetName(unsigned Idx) const override;
3737  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
3738  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3739  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
3740  ArrayRef<const char *> getRegMaskNames() const override;
3741  ArrayRef<const uint32_t *> getRegMasks() const override;
3742  /// Devirtualized TargetFrameLowering.
3743  static const MipsFrameLowering *getFrameLowering(
3744      const MachineFunction &MF);
3745};
3746
3747namespace Mips { // Register classes
3748  extern const TargetRegisterClass MSA128F16RegClass;
3749  extern const TargetRegisterClass MSA128F16_with_sub_64_in_OddSPRegClass;
3750  extern const TargetRegisterClass OddSPRegClass;
3751  extern const TargetRegisterClass CCRRegClass;
3752  extern const TargetRegisterClass COP0RegClass;
3753  extern const TargetRegisterClass COP2RegClass;
3754  extern const TargetRegisterClass COP3RegClass;
3755  extern const TargetRegisterClass DSPRRegClass;
3756  extern const TargetRegisterClass FGR32RegClass;
3757  extern const TargetRegisterClass FGRCCRegClass;
3758  extern const TargetRegisterClass FGRH32RegClass;
3759  extern const TargetRegisterClass GPR32RegClass;
3760  extern const TargetRegisterClass HWRegsRegClass;
3761  extern const TargetRegisterClass GPR32NONZERORegClass;
3762  extern const TargetRegisterClass OddSP_with_sub_hiRegClass;
3763  extern const TargetRegisterClass FGR32_and_OddSPRegClass;
3764  extern const TargetRegisterClass FGRH32_and_OddSPRegClass;
3765  extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass;
3766  extern const TargetRegisterClass CPU16RegsPlusSPRegClass;
3767  extern const TargetRegisterClass CPU16RegsRegClass;
3768  extern const TargetRegisterClass FCCRegClass;
3769  extern const TargetRegisterClass GPRMM16RegClass;
3770  extern const TargetRegisterClass GPRMM16MovePRegClass;
3771  extern const TargetRegisterClass GPRMM16ZeroRegClass;
3772  extern const TargetRegisterClass MSACtrlRegClass;
3773  extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass;
3774  extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;
3775  extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;
3776  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;
3777  extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3778  extern const TargetRegisterClass HI32DSPRegClass;
3779  extern const TargetRegisterClass LO32DSPRegClass;
3780  extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3781  extern const TargetRegisterClass CPURARegRegClass;
3782  extern const TargetRegisterClass CPUSPRegRegClass;
3783  extern const TargetRegisterClass DSPCCRegClass;
3784  extern const TargetRegisterClass GP32RegClass;
3785  extern const TargetRegisterClass GPR32ZERORegClass;
3786  extern const TargetRegisterClass HI32RegClass;
3787  extern const TargetRegisterClass LO32RegClass;
3788  extern const TargetRegisterClass SP32RegClass;
3789  extern const TargetRegisterClass FGR64RegClass;
3790  extern const TargetRegisterClass GPR64RegClass;
3791  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;
3792  extern const TargetRegisterClass AFGR64RegClass;
3793  extern const TargetRegisterClass FGR64_and_OddSPRegClass;
3794  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;
3795  extern const TargetRegisterClass AFGR64_and_OddSPRegClass;
3796  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;
3797  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;
3798  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;
3799  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;
3800  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;
3801  extern const TargetRegisterClass ACC64DSPRegClass;
3802  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;
3803  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3804  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3805  extern const TargetRegisterClass OCTEON_MPLRegClass;
3806  extern const TargetRegisterClass OCTEON_PRegClass;
3807  extern const TargetRegisterClass ACC64RegClass;
3808  extern const TargetRegisterClass GP64RegClass;
3809  extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;
3810  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;
3811  extern const TargetRegisterClass HI64RegClass;
3812  extern const TargetRegisterClass LO64RegClass;
3813  extern const TargetRegisterClass SP64RegClass;
3814  extern const TargetRegisterClass MSA128BRegClass;
3815  extern const TargetRegisterClass MSA128DRegClass;
3816  extern const TargetRegisterClass MSA128HRegClass;
3817  extern const TargetRegisterClass MSA128WRegClass;
3818  extern const TargetRegisterClass MSA128B_with_sub_64_in_OddSPRegClass;
3819  extern const TargetRegisterClass MSA128WEvensRegClass;
3820  extern const TargetRegisterClass ACC128RegClass;
3821} // end namespace Mips
3822
3823} // end namespace llvm
3824
3825#endif // GET_REGINFO_HEADER
3826
3827/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3828|*                                                                            *|
3829|* Target Register and Register Classes Information                           *|
3830|*                                                                            *|
3831|* Automatically generated file, do not edit!                                 *|
3832|*                                                                            *|
3833\*===----------------------------------------------------------------------===*/
3834
3835
3836#ifdef GET_REGINFO_TARGET_DESC
3837#undef GET_REGINFO_TARGET_DESC
3838
3839namespace llvm {
3840
3841extern const MCRegisterClass MipsMCRegisterClasses[];
3842
3843static const MVT::SimpleValueType VTLists[] = {
3844  /* 0 */ MVT::i32, MVT::Other,
3845  /* 2 */ MVT::i64, MVT::Other,
3846  /* 4 */ MVT::f16, MVT::Other,
3847  /* 6 */ MVT::f32, MVT::Other,
3848  /* 8 */ MVT::f64, MVT::Other,
3849  /* 10 */ MVT::v16i8, MVT::Other,
3850  /* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,
3851  /* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other,
3852  /* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other,
3853  /* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other,
3854  /* 24 */ MVT::Untyped, MVT::Other,
3855};
3856
3857static const char *const SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };
3858
3859
3860static const LaneBitmask SubRegIndexLaneMaskTable[] = {
3861  LaneBitmask::getAll(),
3862  LaneBitmask(0x00000001), // sub_32
3863  LaneBitmask(0x00000041), // sub_64
3864  LaneBitmask(0x00000002), // sub_dsp16_19
3865  LaneBitmask(0x00000004), // sub_dsp20
3866  LaneBitmask(0x00000008), // sub_dsp21
3867  LaneBitmask(0x00000010), // sub_dsp22
3868  LaneBitmask(0x00000020), // sub_dsp23
3869  LaneBitmask(0x00000040), // sub_hi
3870  LaneBitmask(0x00000001), // sub_lo
3871  LaneBitmask(0x00000040), // sub_hi_then_sub_32
3872  LaneBitmask(0x00000041), // sub_32_sub_hi_then_sub_32
3873 };
3874
3875
3876
3877static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
3878  // Mode = 0 (Default)
3879  { 16, 16, 128, VTLists+4 },    // MSA128F16
3880  { 16, 16, 128, VTLists+4 },    // MSA128F16_with_sub_64_in_OddSP
3881  { 32, 32, 32, VTLists+6 },    // OddSP
3882  { 32, 32, 32, VTLists+0 },    // CCR
3883  { 32, 32, 32, VTLists+0 },    // COP0
3884  { 32, 32, 32, VTLists+0 },    // COP2
3885  { 32, 32, 32, VTLists+0 },    // COP3
3886  { 32, 32, 32, VTLists+12 },    // DSPR
3887  { 32, 32, 32, VTLists+6 },    // FGR32
3888  { 32, 32, 32, VTLists+0 },    // FGRCC
3889  { 32, 32, 32, VTLists+6 },    // FGRH32
3890  { 32, 32, 32, VTLists+0 },    // GPR32
3891  { 32, 32, 32, VTLists+0 },    // HWRegs
3892  { 32, 32, 32, VTLists+0 },    // GPR32NONZERO
3893  { 32, 32, 32, VTLists+6 },    // OddSP_with_sub_hi
3894  { 32, 32, 32, VTLists+0 },    // FGR32_and_OddSP
3895  { 32, 32, 32, VTLists+6 },    // FGRH32_and_OddSP
3896  { 32, 32, 32, VTLists+6 },    // OddSP_with_sub_hi_with_sub_hi_in_FGRH32
3897  { 32, 32, 32, VTLists+0 },    // CPU16RegsPlusSP
3898  { 32, 32, 32, VTLists+0 },    // CPU16Regs
3899  { 32, 32, 32, VTLists+0 },    // FCC
3900  { 32, 32, 32, VTLists+0 },    // GPRMM16
3901  { 32, 32, 32, VTLists+0 },    // GPRMM16MoveP
3902  { 32, 32, 32, VTLists+0 },    // GPRMM16Zero
3903  { 32, 32, 32, VTLists+0 },    // MSACtrl
3904  { 32, 32, 32, VTLists+6 },    // OddSP_with_sub_hi_with_sub_hi_in_FGR32
3905  { 32, 32, 32, VTLists+0 },    // CPU16Regs_and_GPRMM16Zero
3906  { 32, 32, 32, VTLists+0 },    // GPR32NONZERO_and_GPRMM16MoveP
3907  { 32, 32, 32, VTLists+0 },    // CPU16Regs_and_GPRMM16MoveP
3908  { 32, 32, 32, VTLists+0 },    // GPRMM16MoveP_and_GPRMM16Zero
3909  { 32, 32, 32, VTLists+0 },    // HI32DSP
3910  { 32, 32, 32, VTLists+0 },    // LO32DSP
3911  { 32, 32, 32, VTLists+0 },    // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
3912  { 32, 32, 32, VTLists+0 },    // CPURAReg
3913  { 32, 32, 32, VTLists+0 },    // CPUSPReg
3914  { 32, 32, 32, VTLists+12 },    // DSPCC
3915  { 32, 32, 32, VTLists+0 },    // GP32
3916  { 32, 32, 32, VTLists+0 },    // GPR32ZERO
3917  { 32, 32, 32, VTLists+0 },    // HI32
3918  { 32, 32, 32, VTLists+0 },    // LO32
3919  { 32, 32, 32, VTLists+0 },    // SP32
3920  { 64, 64, 64, VTLists+8 },    // FGR64
3921  { 64, 64, 64, VTLists+2 },    // GPR64
3922  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPR32NONZERO
3923  { 64, 64, 64, VTLists+8 },    // AFGR64
3924  { 64, 64, 64, VTLists+8 },    // FGR64_and_OddSP
3925  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16RegsPlusSP
3926  { 64, 64, 64, VTLists+8 },    // AFGR64_and_OddSP
3927  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs
3928  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MoveP
3929  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16Zero
3930  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
3931  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
3932  { 64, 64, 64, VTLists+24 },    // ACC64DSP
3933  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
3934  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
3935  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
3936  { 64, 64, 64, VTLists+2 },    // OCTEON_MPL
3937  { 64, 64, 64, VTLists+2 },    // OCTEON_P
3938  { 64, 64, 64, VTLists+24 },    // ACC64
3939  { 64, 64, 64, VTLists+2 },    // GP64
3940  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPURAReg
3941  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPR32ZERO
3942  { 64, 64, 64, VTLists+2 },    // HI64
3943  { 64, 64, 64, VTLists+2 },    // LO64
3944  { 64, 64, 64, VTLists+2 },    // SP64
3945  { 128, 128, 128, VTLists+10 },    // MSA128B
3946  { 128, 128, 128, VTLists+21 },    // MSA128D
3947  { 128, 128, 128, VTLists+15 },    // MSA128H
3948  { 128, 128, 128, VTLists+18 },    // MSA128W
3949  { 128, 128, 128, VTLists+18 },    // MSA128B_with_sub_64_in_OddSP
3950  { 128, 128, 128, VTLists+18 },    // MSA128WEvens
3951  { 128, 128, 128, VTLists+24 },    // ACC128
3952};
3953
3954static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
3955
3956static const uint32_t MSA128F16SubClassMask[] = {
3957  0x00000003, 0x00000000, 0x000000fc,
3958};
3959
3960static const uint32_t MSA128F16_with_sub_64_in_OddSPSubClassMask[] = {
3961  0x00000002, 0x00000000, 0x00000040,
3962};
3963
3964static const uint32_t OddSPSubClassMask[] = {
3965  0x0203c004, 0x0000a000, 0x00000000,
3966  0x00000002, 0x00000000, 0x00000040, // sub_64
3967  0x02024002, 0x0000b000, 0x00000040, // sub_hi
3968  0x00020002, 0x00002000, 0x00000040, // sub_lo
3969};
3970
3971static const uint32_t CCRSubClassMask[] = {
3972  0x00000008, 0x00000000, 0x00000000,
3973};
3974
3975static const uint32_t COP0SubClassMask[] = {
3976  0x00000010, 0x00000000, 0x00000000,
3977};
3978
3979static const uint32_t COP2SubClassMask[] = {
3980  0x00000020, 0x00000000, 0x00000000,
3981};
3982
3983static const uint32_t COP3SubClassMask[] = {
3984  0x00000040, 0x00000000, 0x00000000,
3985};
3986
3987static const uint32_t DSPRSubClassMask[] = {
3988  0x3cec2880, 0x00000137, 0x00000000,
3989  0x00000000, 0x71df4c00, 0x00000002, // sub_32
3990};
3991
3992static const uint32_t FGR32SubClassMask[] = {
3993  0x00008300, 0x00000000, 0x00000000,
3994  0x02000000, 0x00009000, 0x00000000, // sub_hi
3995  0x02024003, 0x0000b200, 0x000000fc, // sub_lo
3996};
3997
3998static const uint32_t FGRCCSubClassMask[] = {
3999  0x00008300, 0x00000000, 0x00000000,
4000  0x02000000, 0x00009000, 0x00000000, // sub_hi
4001  0x02024003, 0x0000b200, 0x000000fc, // sub_lo
4002};
4003
4004static const uint32_t FGRH32SubClassMask[] = {
4005  0x00010400, 0x00000000, 0x00000000,
4006  0x00020003, 0x00002200, 0x000000fc, // sub_hi
4007};
4008
4009static const uint32_t GPR32SubClassMask[] = {
4010  0x3cec2800, 0x00000137, 0x00000000,
4011  0x00000000, 0x71df4c00, 0x00000002, // sub_32
4012};
4013
4014static const uint32_t HWRegsSubClassMask[] = {
4015  0x00001000, 0x00000000, 0x00000000,
4016};
4017
4018static const uint32_t GPR32NONZEROSubClassMask[] = {
4019  0x1c2c2000, 0x00000117, 0x00000000,
4020  0x00000000, 0x31594800, 0x00000002, // sub_32
4021};
4022
4023static const uint32_t OddSP_with_sub_hiSubClassMask[] = {
4024  0x02024000, 0x0000a000, 0x00000000,
4025  0x00000002, 0x00000000, 0x00000040, // sub_64
4026};
4027
4028static const uint32_t FGR32_and_OddSPSubClassMask[] = {
4029  0x00008000, 0x00000000, 0x00000000,
4030  0x02000000, 0x00009000, 0x00000000, // sub_hi
4031  0x00020002, 0x00002000, 0x00000040, // sub_lo
4032};
4033
4034static const uint32_t FGRH32_and_OddSPSubClassMask[] = {
4035  0x00010000, 0x00000000, 0x00000000,
4036  0x00020002, 0x00002000, 0x00000040, // sub_hi
4037};
4038
4039static const uint32_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32SubClassMask[] = {
4040  0x00020000, 0x00002000, 0x00000000,
4041  0x00000002, 0x00000000, 0x00000040, // sub_64
4042};
4043
4044static const uint32_t CPU16RegsPlusSPSubClassMask[] = {
4045  0x142c0000, 0x00000105, 0x00000000,
4046  0x00000000, 0x01494000, 0x00000002, // sub_32
4047};
4048
4049static const uint32_t CPU16RegsSubClassMask[] = {
4050  0x14280000, 0x00000001, 0x00000000,
4051  0x00000000, 0x01490000, 0x00000000, // sub_32
4052};
4053
4054static const uint32_t FCCSubClassMask[] = {
4055  0x00100000, 0x00000000, 0x00000000,
4056};
4057
4058static const uint32_t GPRMM16SubClassMask[] = {
4059  0x14200000, 0x00000001, 0x00000000,
4060  0x00000000, 0x01490000, 0x00000000, // sub_32
4061};
4062
4063static const uint32_t GPRMM16MovePSubClassMask[] = {
4064  0x38400000, 0x00000021, 0x00000000,
4065  0x00000000, 0x41d20000, 0x00000000, // sub_32
4066};
4067
4068static const uint32_t GPRMM16ZeroSubClassMask[] = {
4069  0x24800000, 0x00000021, 0x00000000,
4070  0x00000000, 0x418c0000, 0x00000000, // sub_32
4071};
4072
4073static const uint32_t MSACtrlSubClassMask[] = {
4074  0x01000000, 0x00000000, 0x00000000,
4075};
4076
4077static const uint32_t OddSP_with_sub_hi_with_sub_hi_in_FGR32SubClassMask[] = {
4078  0x02000000, 0x00008000, 0x00000000,
4079};
4080
4081static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4082  0x04000000, 0x00000001, 0x00000000,
4083  0x00000000, 0x01080000, 0x00000000, // sub_32
4084};
4085
4086static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4087  0x18000000, 0x00000001, 0x00000000,
4088  0x00000000, 0x01500000, 0x00000000, // sub_32
4089};
4090
4091static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4092  0x10000000, 0x00000001, 0x00000000,
4093  0x00000000, 0x01400000, 0x00000000, // sub_32
4094};
4095
4096static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4097  0x20000000, 0x00000021, 0x00000000,
4098  0x00000000, 0x41800000, 0x00000000, // sub_32
4099};
4100
4101static const uint32_t HI32DSPSubClassMask[] = {
4102  0x40000000, 0x00000040, 0x00000000,
4103  0x00000000, 0x80000000, 0x00000000, // sub_32
4104  0x00000000, 0x08200000, 0x00000000, // sub_hi
4105  0x00000000, 0x00000000, 0x00000100, // sub_hi_then_sub_32
4106};
4107
4108static const uint32_t LO32DSPSubClassMask[] = {
4109  0x80000000, 0x00000080, 0x00000000,
4110  0x00000000, 0x00000000, 0x00000101, // sub_32
4111  0x00000000, 0x08200000, 0x00000000, // sub_lo
4112};
4113
4114static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4115  0x00000000, 0x00000001, 0x00000000,
4116  0x00000000, 0x01000000, 0x00000000, // sub_32
4117};
4118
4119static const uint32_t CPURARegSubClassMask[] = {
4120  0x00000000, 0x00000002, 0x00000000,
4121  0x00000000, 0x20000000, 0x00000000, // sub_32
4122};
4123
4124static const uint32_t CPUSPRegSubClassMask[] = {
4125  0x00000000, 0x00000104, 0x00000000,
4126  0x00000000, 0x00000000, 0x00000002, // sub_32
4127};
4128
4129static const uint32_t DSPCCSubClassMask[] = {
4130  0x00000000, 0x00000008, 0x00000000,
4131};
4132
4133static const uint32_t GP32SubClassMask[] = {
4134  0x00000000, 0x00000010, 0x00000000,
4135  0x00000000, 0x10000000, 0x00000000, // sub_32
4136};
4137
4138static const uint32_t GPR32ZEROSubClassMask[] = {
4139  0x00000000, 0x00000020, 0x00000000,
4140  0x00000000, 0x40000000, 0x00000000, // sub_32
4141};
4142
4143static const uint32_t HI32SubClassMask[] = {
4144  0x00000000, 0x00000040, 0x00000000,
4145  0x00000000, 0x80000000, 0x00000000, // sub_32
4146  0x00000000, 0x08000000, 0x00000000, // sub_hi
4147  0x00000000, 0x00000000, 0x00000100, // sub_hi_then_sub_32
4148};
4149
4150static const uint32_t LO32SubClassMask[] = {
4151  0x00000000, 0x00000080, 0x00000000,
4152  0x00000000, 0x00000000, 0x00000101, // sub_32
4153  0x00000000, 0x08000000, 0x00000000, // sub_lo
4154};
4155
4156static const uint32_t SP32SubClassMask[] = {
4157  0x00000000, 0x00000100, 0x00000000,
4158  0x00000000, 0x00000000, 0x00000002, // sub_32
4159};
4160
4161static const uint32_t FGR64SubClassMask[] = {
4162  0x00000000, 0x00002200, 0x00000000,
4163  0x00000003, 0x00000000, 0x000000fc, // sub_64
4164};
4165
4166static const uint32_t GPR64SubClassMask[] = {
4167  0x00000000, 0x71df4c00, 0x00000002,
4168};
4169
4170static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {
4171  0x00000000, 0x31594800, 0x00000002,
4172};
4173
4174static const uint32_t AFGR64SubClassMask[] = {
4175  0x00000000, 0x00009000, 0x00000000,
4176};
4177
4178static const uint32_t FGR64_and_OddSPSubClassMask[] = {
4179  0x00000000, 0x00002000, 0x00000000,
4180  0x00000002, 0x00000000, 0x00000040, // sub_64
4181};
4182
4183static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {
4184  0x00000000, 0x01494000, 0x00000002,
4185};
4186
4187static const uint32_t AFGR64_and_OddSPSubClassMask[] = {
4188  0x00000000, 0x00008000, 0x00000000,
4189};
4190
4191static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {
4192  0x00000000, 0x01490000, 0x00000000,
4193};
4194
4195static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {
4196  0x00000000, 0x41d20000, 0x00000000,
4197};
4198
4199static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {
4200  0x00000000, 0x418c0000, 0x00000000,
4201};
4202
4203static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4204  0x00000000, 0x01080000, 0x00000000,
4205};
4206
4207static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4208  0x00000000, 0x01500000, 0x00000000,
4209};
4210
4211static const uint32_t ACC64DSPSubClassMask[] = {
4212  0x00000000, 0x08200000, 0x00000000,
4213  0x00000000, 0x00000000, 0x00000100, // sub_32_sub_hi_then_sub_32
4214};
4215
4216static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4217  0x00000000, 0x01400000, 0x00000000,
4218};
4219
4220static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4221  0x00000000, 0x41800000, 0x00000000,
4222};
4223
4224static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4225  0x00000000, 0x01000000, 0x00000000,
4226};
4227
4228static const uint32_t OCTEON_MPLSubClassMask[] = {
4229  0x00000000, 0x02000000, 0x00000000,
4230};
4231
4232static const uint32_t OCTEON_PSubClassMask[] = {
4233  0x00000000, 0x04000000, 0x00000000,
4234};
4235
4236static const uint32_t ACC64SubClassMask[] = {
4237  0x00000000, 0x08000000, 0x00000000,
4238  0x00000000, 0x00000000, 0x00000100, // sub_32_sub_hi_then_sub_32
4239};
4240
4241static const uint32_t GP64SubClassMask[] = {
4242  0x00000000, 0x10000000, 0x00000000,
4243};
4244
4245static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {
4246  0x00000000, 0x20000000, 0x00000000,
4247};
4248
4249static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {
4250  0x00000000, 0x40000000, 0x00000000,
4251};
4252
4253static const uint32_t HI64SubClassMask[] = {
4254  0x00000000, 0x80000000, 0x00000000,
4255  0x00000000, 0x00000000, 0x00000100, // sub_hi
4256};
4257
4258static const uint32_t LO64SubClassMask[] = {
4259  0x00000000, 0x00000000, 0x00000001,
4260  0x00000000, 0x00000000, 0x00000100, // sub_lo
4261};
4262
4263static const uint32_t SP64SubClassMask[] = {
4264  0x00000000, 0x00000000, 0x00000002,
4265};
4266
4267static const uint32_t MSA128BSubClassMask[] = {
4268  0x00000000, 0x00000000, 0x000000fc,
4269};
4270
4271static const uint32_t MSA128DSubClassMask[] = {
4272  0x00000000, 0x00000000, 0x000000fc,
4273};
4274
4275static const uint32_t MSA128HSubClassMask[] = {
4276  0x00000000, 0x00000000, 0x000000fc,
4277};
4278
4279static const uint32_t MSA128WSubClassMask[] = {
4280  0x00000000, 0x00000000, 0x000000fc,
4281};
4282
4283static const uint32_t MSA128B_with_sub_64_in_OddSPSubClassMask[] = {
4284  0x00000000, 0x00000000, 0x00000040,
4285};
4286
4287static const uint32_t MSA128WEvensSubClassMask[] = {
4288  0x00000000, 0x00000000, 0x00000080,
4289};
4290
4291static const uint32_t ACC128SubClassMask[] = {
4292  0x00000000, 0x00000000, 0x00000100,
4293};
4294
4295static const uint16_t SuperRegIdxSeqs[] = {
4296  /* 0 */ 1, 0,
4297  /* 2 */ 2, 0,
4298  /* 4 */ 8, 0,
4299  /* 6 */ 1, 9, 0,
4300  /* 9 */ 2, 8, 9, 0,
4301  /* 13 */ 1, 8, 10, 0,
4302  /* 17 */ 11, 0,
4303};
4304
4305static const TargetRegisterClass *const MSA128F16_with_sub_64_in_OddSPSuperclasses[] = {
4306  &Mips::MSA128F16RegClass,
4307  nullptr
4308};
4309
4310static const TargetRegisterClass *const FGR32Superclasses[] = {
4311  &Mips::FGRCCRegClass,
4312  nullptr
4313};
4314
4315static const TargetRegisterClass *const FGRCCSuperclasses[] = {
4316  &Mips::FGR32RegClass,
4317  nullptr
4318};
4319
4320static const TargetRegisterClass *const GPR32Superclasses[] = {
4321  &Mips::DSPRRegClass,
4322  nullptr
4323};
4324
4325static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = {
4326  &Mips::DSPRRegClass,
4327  &Mips::GPR32RegClass,
4328  nullptr
4329};
4330
4331static const TargetRegisterClass *const OddSP_with_sub_hiSuperclasses[] = {
4332  &Mips::OddSPRegClass,
4333  nullptr
4334};
4335
4336static const TargetRegisterClass *const FGR32_and_OddSPSuperclasses[] = {
4337  &Mips::OddSPRegClass,
4338  &Mips::FGR32RegClass,
4339  &Mips::FGRCCRegClass,
4340  nullptr
4341};
4342
4343static const TargetRegisterClass *const FGRH32_and_OddSPSuperclasses[] = {
4344  &Mips::OddSPRegClass,
4345  &Mips::FGRH32RegClass,
4346  nullptr
4347};
4348
4349static const TargetRegisterClass *const OddSP_with_sub_hi_with_sub_hi_in_FGRH32Superclasses[] = {
4350  &Mips::OddSPRegClass,
4351  &Mips::OddSP_with_sub_hiRegClass,
4352  nullptr
4353};
4354
4355static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = {
4356  &Mips::DSPRRegClass,
4357  &Mips::GPR32RegClass,
4358  &Mips::GPR32NONZERORegClass,
4359  nullptr
4360};
4361
4362static const TargetRegisterClass *const CPU16RegsSuperclasses[] = {
4363  &Mips::DSPRRegClass,
4364  &Mips::GPR32RegClass,
4365  &Mips::GPR32NONZERORegClass,
4366  &Mips::CPU16RegsPlusSPRegClass,
4367  nullptr
4368};
4369
4370static const TargetRegisterClass *const GPRMM16Superclasses[] = {
4371  &Mips::DSPRRegClass,
4372  &Mips::GPR32RegClass,
4373  &Mips::GPR32NONZERORegClass,
4374  &Mips::CPU16RegsPlusSPRegClass,
4375  &Mips::CPU16RegsRegClass,
4376  nullptr
4377};
4378
4379static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = {
4380  &Mips::DSPRRegClass,
4381  &Mips::GPR32RegClass,
4382  nullptr
4383};
4384
4385static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = {
4386  &Mips::DSPRRegClass,
4387  &Mips::GPR32RegClass,
4388  nullptr
4389};
4390
4391static const TargetRegisterClass *const OddSP_with_sub_hi_with_sub_hi_in_FGR32Superclasses[] = {
4392  &Mips::OddSPRegClass,
4393  &Mips::OddSP_with_sub_hiRegClass,
4394  nullptr
4395};
4396
4397static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4398  &Mips::DSPRRegClass,
4399  &Mips::GPR32RegClass,
4400  &Mips::GPR32NONZERORegClass,
4401  &Mips::CPU16RegsPlusSPRegClass,
4402  &Mips::CPU16RegsRegClass,
4403  &Mips::GPRMM16RegClass,
4404  &Mips::GPRMM16ZeroRegClass,
4405  nullptr
4406};
4407
4408static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4409  &Mips::DSPRRegClass,
4410  &Mips::GPR32RegClass,
4411  &Mips::GPR32NONZERORegClass,
4412  &Mips::GPRMM16MovePRegClass,
4413  nullptr
4414};
4415
4416static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4417  &Mips::DSPRRegClass,
4418  &Mips::GPR32RegClass,
4419  &Mips::GPR32NONZERORegClass,
4420  &Mips::CPU16RegsPlusSPRegClass,
4421  &Mips::CPU16RegsRegClass,
4422  &Mips::GPRMM16RegClass,
4423  &Mips::GPRMM16MovePRegClass,
4424  &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
4425  nullptr
4426};
4427
4428static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4429  &Mips::DSPRRegClass,
4430  &Mips::GPR32RegClass,
4431  &Mips::GPRMM16MovePRegClass,
4432  &Mips::GPRMM16ZeroRegClass,
4433  nullptr
4434};
4435
4436static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4437  &Mips::DSPRRegClass,
4438  &Mips::GPR32RegClass,
4439  &Mips::GPR32NONZERORegClass,
4440  &Mips::CPU16RegsPlusSPRegClass,
4441  &Mips::CPU16RegsRegClass,
4442  &Mips::GPRMM16RegClass,
4443  &Mips::GPRMM16MovePRegClass,
4444  &Mips::GPRMM16ZeroRegClass,
4445  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4446  &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
4447  &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
4448  &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4449  nullptr
4450};
4451
4452static const TargetRegisterClass *const CPURARegSuperclasses[] = {
4453  &Mips::DSPRRegClass,
4454  &Mips::GPR32RegClass,
4455  &Mips::GPR32NONZERORegClass,
4456  nullptr
4457};
4458
4459static const TargetRegisterClass *const CPUSPRegSuperclasses[] = {
4460  &Mips::DSPRRegClass,
4461  &Mips::GPR32RegClass,
4462  &Mips::GPR32NONZERORegClass,
4463  &Mips::CPU16RegsPlusSPRegClass,
4464  nullptr
4465};
4466
4467static const TargetRegisterClass *const GP32Superclasses[] = {
4468  &Mips::DSPRRegClass,
4469  &Mips::GPR32RegClass,
4470  &Mips::GPR32NONZERORegClass,
4471  nullptr
4472};
4473
4474static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = {
4475  &Mips::DSPRRegClass,
4476  &Mips::GPR32RegClass,
4477  &Mips::GPRMM16MovePRegClass,
4478  &Mips::GPRMM16ZeroRegClass,
4479  &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4480  nullptr
4481};
4482
4483static const TargetRegisterClass *const HI32Superclasses[] = {
4484  &Mips::HI32DSPRegClass,
4485  nullptr
4486};
4487
4488static const TargetRegisterClass *const LO32Superclasses[] = {
4489  &Mips::LO32DSPRegClass,
4490  nullptr
4491};
4492
4493static const TargetRegisterClass *const SP32Superclasses[] = {
4494  &Mips::DSPRRegClass,
4495  &Mips::GPR32RegClass,
4496  &Mips::GPR32NONZERORegClass,
4497  &Mips::CPU16RegsPlusSPRegClass,
4498  &Mips::CPUSPRegRegClass,
4499  nullptr
4500};
4501
4502static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
4503  &Mips::GPR64RegClass,
4504  nullptr
4505};
4506
4507static const TargetRegisterClass *const FGR64_and_OddSPSuperclasses[] = {
4508  &Mips::OddSPRegClass,
4509  &Mips::OddSP_with_sub_hiRegClass,
4510  &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass,
4511  &Mips::FGR64RegClass,
4512  nullptr
4513};
4514
4515static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
4516  &Mips::GPR64RegClass,
4517  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4518  nullptr
4519};
4520
4521static const TargetRegisterClass *const AFGR64_and_OddSPSuperclasses[] = {
4522  &Mips::OddSPRegClass,
4523  &Mips::OddSP_with_sub_hiRegClass,
4524  &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass,
4525  &Mips::AFGR64RegClass,
4526  nullptr
4527};
4528
4529static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
4530  &Mips::GPR64RegClass,
4531  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4532  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4533  nullptr
4534};
4535
4536static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
4537  &Mips::GPR64RegClass,
4538  nullptr
4539};
4540
4541static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
4542  &Mips::GPR64RegClass,
4543  nullptr
4544};
4545
4546static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4547  &Mips::GPR64RegClass,
4548  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4549  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4550  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4551  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4552  nullptr
4553};
4554
4555static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4556  &Mips::GPR64RegClass,
4557  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4558  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4559  nullptr
4560};
4561
4562static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4563  &Mips::GPR64RegClass,
4564  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4565  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4566  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4567  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4568  &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
4569  nullptr
4570};
4571
4572static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4573  &Mips::GPR64RegClass,
4574  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4575  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4576  nullptr
4577};
4578
4579static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4580  &Mips::GPR64RegClass,
4581  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4582  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4583  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4584  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4585  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4586  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4587  &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
4588  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
4589  &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4590  nullptr
4591};
4592
4593static const TargetRegisterClass *const ACC64Superclasses[] = {
4594  &Mips::ACC64DSPRegClass,
4595  nullptr
4596};
4597
4598static const TargetRegisterClass *const GP64Superclasses[] = {
4599  &Mips::GPR64RegClass,
4600  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4601  nullptr
4602};
4603
4604static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
4605  &Mips::GPR64RegClass,
4606  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4607  nullptr
4608};
4609
4610static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
4611  &Mips::GPR64RegClass,
4612  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4613  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4614  &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4615  nullptr
4616};
4617
4618static const TargetRegisterClass *const SP64Superclasses[] = {
4619  &Mips::GPR64RegClass,
4620  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4621  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4622  nullptr
4623};
4624
4625static const TargetRegisterClass *const MSA128BSuperclasses[] = {
4626  &Mips::MSA128F16RegClass,
4627  &Mips::MSA128DRegClass,
4628  &Mips::MSA128HRegClass,
4629  &Mips::MSA128WRegClass,
4630  nullptr
4631};
4632
4633static const TargetRegisterClass *const MSA128DSuperclasses[] = {
4634  &Mips::MSA128F16RegClass,
4635  &Mips::MSA128BRegClass,
4636  &Mips::MSA128HRegClass,
4637  &Mips::MSA128WRegClass,
4638  nullptr
4639};
4640
4641static const TargetRegisterClass *const MSA128HSuperclasses[] = {
4642  &Mips::MSA128F16RegClass,
4643  &Mips::MSA128BRegClass,
4644  &Mips::MSA128DRegClass,
4645  &Mips::MSA128WRegClass,
4646  nullptr
4647};
4648
4649static const TargetRegisterClass *const MSA128WSuperclasses[] = {
4650  &Mips::MSA128F16RegClass,
4651  &Mips::MSA128BRegClass,
4652  &Mips::MSA128DRegClass,
4653  &Mips::MSA128HRegClass,
4654  nullptr
4655};
4656
4657static const TargetRegisterClass *const MSA128B_with_sub_64_in_OddSPSuperclasses[] = {
4658  &Mips::MSA128F16RegClass,
4659  &Mips::MSA128F16_with_sub_64_in_OddSPRegClass,
4660  &Mips::MSA128BRegClass,
4661  &Mips::MSA128DRegClass,
4662  &Mips::MSA128HRegClass,
4663  &Mips::MSA128WRegClass,
4664  nullptr
4665};
4666
4667static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = {
4668  &Mips::MSA128F16RegClass,
4669  &Mips::MSA128BRegClass,
4670  &Mips::MSA128DRegClass,
4671  &Mips::MSA128HRegClass,
4672  &Mips::MSA128WRegClass,
4673  nullptr
4674};
4675
4676
4677namespace Mips {   // Register class instances
4678  extern const TargetRegisterClass MSA128F16RegClass = {
4679    &MipsMCRegisterClasses[MSA128F16RegClassID],
4680    MSA128F16SubClassMask,
4681    SuperRegIdxSeqs + 1,
4682    LaneBitmask(0x00000041),
4683    0,
4684    true, /* HasDisjunctSubRegs */
4685    false, /* CoveredBySubRegs */
4686    NullRegClasses,
4687    nullptr
4688  };
4689
4690  extern const TargetRegisterClass MSA128F16_with_sub_64_in_OddSPRegClass = {
4691    &MipsMCRegisterClasses[MSA128F16_with_sub_64_in_OddSPRegClassID],
4692    MSA128F16_with_sub_64_in_OddSPSubClassMask,
4693    SuperRegIdxSeqs + 1,
4694    LaneBitmask(0x00000041),
4695    0,
4696    true, /* HasDisjunctSubRegs */
4697    false, /* CoveredBySubRegs */
4698    MSA128F16_with_sub_64_in_OddSPSuperclasses,
4699    nullptr
4700  };
4701
4702  extern const TargetRegisterClass OddSPRegClass = {
4703    &MipsMCRegisterClasses[OddSPRegClassID],
4704    OddSPSubClassMask,
4705    SuperRegIdxSeqs + 9,
4706    LaneBitmask(0x00000041),
4707    0,
4708    true, /* HasDisjunctSubRegs */
4709    false, /* CoveredBySubRegs */
4710    NullRegClasses,
4711    nullptr
4712  };
4713
4714  extern const TargetRegisterClass CCRRegClass = {
4715    &MipsMCRegisterClasses[CCRRegClassID],
4716    CCRSubClassMask,
4717    SuperRegIdxSeqs + 1,
4718    LaneBitmask(0x00000001),
4719    0,
4720    false, /* HasDisjunctSubRegs */
4721    false, /* CoveredBySubRegs */
4722    NullRegClasses,
4723    nullptr
4724  };
4725
4726  extern const TargetRegisterClass COP0RegClass = {
4727    &MipsMCRegisterClasses[COP0RegClassID],
4728    COP0SubClassMask,
4729    SuperRegIdxSeqs + 1,
4730    LaneBitmask(0x00000001),
4731    0,
4732    false, /* HasDisjunctSubRegs */
4733    false, /* CoveredBySubRegs */
4734    NullRegClasses,
4735    nullptr
4736  };
4737
4738  extern const TargetRegisterClass COP2RegClass = {
4739    &MipsMCRegisterClasses[COP2RegClassID],
4740    COP2SubClassMask,
4741    SuperRegIdxSeqs + 1,
4742    LaneBitmask(0x00000001),
4743    0,
4744    false, /* HasDisjunctSubRegs */
4745    false, /* CoveredBySubRegs */
4746    NullRegClasses,
4747    nullptr
4748  };
4749
4750  extern const TargetRegisterClass COP3RegClass = {
4751    &MipsMCRegisterClasses[COP3RegClassID],
4752    COP3SubClassMask,
4753    SuperRegIdxSeqs + 1,
4754    LaneBitmask(0x00000001),
4755    0,
4756    false, /* HasDisjunctSubRegs */
4757    false, /* CoveredBySubRegs */
4758    NullRegClasses,
4759    nullptr
4760  };
4761
4762  extern const TargetRegisterClass DSPRRegClass = {
4763    &MipsMCRegisterClasses[DSPRRegClassID],
4764    DSPRSubClassMask,
4765    SuperRegIdxSeqs + 0,
4766    LaneBitmask(0x00000001),
4767    0,
4768    false, /* HasDisjunctSubRegs */
4769    false, /* CoveredBySubRegs */
4770    NullRegClasses,
4771    nullptr
4772  };
4773
4774  extern const TargetRegisterClass FGR32RegClass = {
4775    &MipsMCRegisterClasses[FGR32RegClassID],
4776    FGR32SubClassMask,
4777    SuperRegIdxSeqs + 10,
4778    LaneBitmask(0x00000001),
4779    0,
4780    false, /* HasDisjunctSubRegs */
4781    false, /* CoveredBySubRegs */
4782    FGR32Superclasses,
4783    nullptr
4784  };
4785
4786  extern const TargetRegisterClass FGRCCRegClass = {
4787    &MipsMCRegisterClasses[FGRCCRegClassID],
4788    FGRCCSubClassMask,
4789    SuperRegIdxSeqs + 10,
4790    LaneBitmask(0x00000001),
4791    0,
4792    false, /* HasDisjunctSubRegs */
4793    false, /* CoveredBySubRegs */
4794    FGRCCSuperclasses,
4795    nullptr
4796  };
4797
4798  extern const TargetRegisterClass FGRH32RegClass = {
4799    &MipsMCRegisterClasses[FGRH32RegClassID],
4800    FGRH32SubClassMask,
4801    SuperRegIdxSeqs + 4,
4802    LaneBitmask(0x00000001),
4803    0,
4804    false, /* HasDisjunctSubRegs */
4805    false, /* CoveredBySubRegs */
4806    NullRegClasses,
4807    nullptr
4808  };
4809
4810  extern const TargetRegisterClass GPR32RegClass = {
4811    &MipsMCRegisterClasses[GPR32RegClassID],
4812    GPR32SubClassMask,
4813    SuperRegIdxSeqs + 0,
4814    LaneBitmask(0x00000001),
4815    0,
4816    false, /* HasDisjunctSubRegs */
4817    false, /* CoveredBySubRegs */
4818    GPR32Superclasses,
4819    nullptr
4820  };
4821
4822  extern const TargetRegisterClass HWRegsRegClass = {
4823    &MipsMCRegisterClasses[HWRegsRegClassID],
4824    HWRegsSubClassMask,
4825    SuperRegIdxSeqs + 1,
4826    LaneBitmask(0x00000001),
4827    0,
4828    false, /* HasDisjunctSubRegs */
4829    false, /* CoveredBySubRegs */
4830    NullRegClasses,
4831    nullptr
4832  };
4833
4834  extern const TargetRegisterClass GPR32NONZERORegClass = {
4835    &MipsMCRegisterClasses[GPR32NONZERORegClassID],
4836    GPR32NONZEROSubClassMask,
4837    SuperRegIdxSeqs + 0,
4838    LaneBitmask(0x00000001),
4839    0,
4840    false, /* HasDisjunctSubRegs */
4841    false, /* CoveredBySubRegs */
4842    GPR32NONZEROSuperclasses,
4843    nullptr
4844  };
4845
4846  extern const TargetRegisterClass OddSP_with_sub_hiRegClass = {
4847    &MipsMCRegisterClasses[OddSP_with_sub_hiRegClassID],
4848    OddSP_with_sub_hiSubClassMask,
4849    SuperRegIdxSeqs + 2,
4850    LaneBitmask(0x00000041),
4851    0,
4852    true, /* HasDisjunctSubRegs */
4853    true, /* CoveredBySubRegs */
4854    OddSP_with_sub_hiSuperclasses,
4855    nullptr
4856  };
4857
4858  extern const TargetRegisterClass FGR32_and_OddSPRegClass = {
4859    &MipsMCRegisterClasses[FGR32_and_OddSPRegClassID],
4860    FGR32_and_OddSPSubClassMask,
4861    SuperRegIdxSeqs + 10,
4862    LaneBitmask(0x00000001),
4863    0,
4864    false, /* HasDisjunctSubRegs */
4865    false, /* CoveredBySubRegs */
4866    FGR32_and_OddSPSuperclasses,
4867    nullptr
4868  };
4869
4870  extern const TargetRegisterClass FGRH32_and_OddSPRegClass = {
4871    &MipsMCRegisterClasses[FGRH32_and_OddSPRegClassID],
4872    FGRH32_and_OddSPSubClassMask,
4873    SuperRegIdxSeqs + 4,
4874    LaneBitmask(0x00000001),
4875    0,
4876    false, /* HasDisjunctSubRegs */
4877    false, /* CoveredBySubRegs */
4878    FGRH32_and_OddSPSuperclasses,
4879    nullptr
4880  };
4881
4882  extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass = {
4883    &MipsMCRegisterClasses[OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID],
4884    OddSP_with_sub_hi_with_sub_hi_in_FGRH32SubClassMask,
4885    SuperRegIdxSeqs + 2,
4886    LaneBitmask(0x00000041),
4887    0,
4888    true, /* HasDisjunctSubRegs */
4889    true, /* CoveredBySubRegs */
4890    OddSP_with_sub_hi_with_sub_hi_in_FGRH32Superclasses,
4891    nullptr
4892  };
4893
4894  extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
4895    &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],
4896    CPU16RegsPlusSPSubClassMask,
4897    SuperRegIdxSeqs + 0,
4898    LaneBitmask(0x00000001),
4899    0,
4900    false, /* HasDisjunctSubRegs */
4901    false, /* CoveredBySubRegs */
4902    CPU16RegsPlusSPSuperclasses,
4903    nullptr
4904  };
4905
4906  extern const TargetRegisterClass CPU16RegsRegClass = {
4907    &MipsMCRegisterClasses[CPU16RegsRegClassID],
4908    CPU16RegsSubClassMask,
4909    SuperRegIdxSeqs + 0,
4910    LaneBitmask(0x00000001),
4911    0,
4912    false, /* HasDisjunctSubRegs */
4913    false, /* CoveredBySubRegs */
4914    CPU16RegsSuperclasses,
4915    nullptr
4916  };
4917
4918  extern const TargetRegisterClass FCCRegClass = {
4919    &MipsMCRegisterClasses[FCCRegClassID],
4920    FCCSubClassMask,
4921    SuperRegIdxSeqs + 1,
4922    LaneBitmask(0x00000001),
4923    0,
4924    false, /* HasDisjunctSubRegs */
4925    false, /* CoveredBySubRegs */
4926    NullRegClasses,
4927    nullptr
4928  };
4929
4930  extern const TargetRegisterClass GPRMM16RegClass = {
4931    &MipsMCRegisterClasses[GPRMM16RegClassID],
4932    GPRMM16SubClassMask,
4933    SuperRegIdxSeqs + 0,
4934    LaneBitmask(0x00000001),
4935    0,
4936    false, /* HasDisjunctSubRegs */
4937    false, /* CoveredBySubRegs */
4938    GPRMM16Superclasses,
4939    nullptr
4940  };
4941
4942  extern const TargetRegisterClass GPRMM16MovePRegClass = {
4943    &MipsMCRegisterClasses[GPRMM16MovePRegClassID],
4944    GPRMM16MovePSubClassMask,
4945    SuperRegIdxSeqs + 0,
4946    LaneBitmask(0x00000001),
4947    0,
4948    false, /* HasDisjunctSubRegs */
4949    false, /* CoveredBySubRegs */
4950    GPRMM16MovePSuperclasses,
4951    nullptr
4952  };
4953
4954  extern const TargetRegisterClass GPRMM16ZeroRegClass = {
4955    &MipsMCRegisterClasses[GPRMM16ZeroRegClassID],
4956    GPRMM16ZeroSubClassMask,
4957    SuperRegIdxSeqs + 0,
4958    LaneBitmask(0x00000001),
4959    0,
4960    false, /* HasDisjunctSubRegs */
4961    false, /* CoveredBySubRegs */
4962    GPRMM16ZeroSuperclasses,
4963    nullptr
4964  };
4965
4966  extern const TargetRegisterClass MSACtrlRegClass = {
4967    &MipsMCRegisterClasses[MSACtrlRegClassID],
4968    MSACtrlSubClassMask,
4969    SuperRegIdxSeqs + 1,
4970    LaneBitmask(0x00000001),
4971    0,
4972    false, /* HasDisjunctSubRegs */
4973    false, /* CoveredBySubRegs */
4974    NullRegClasses,
4975    nullptr
4976  };
4977
4978  extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass = {
4979    &MipsMCRegisterClasses[OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID],
4980    OddSP_with_sub_hi_with_sub_hi_in_FGR32SubClassMask,
4981    SuperRegIdxSeqs + 1,
4982    LaneBitmask(0x00000041),
4983    0,
4984    true, /* HasDisjunctSubRegs */
4985    true, /* CoveredBySubRegs */
4986    OddSP_with_sub_hi_with_sub_hi_in_FGR32Superclasses,
4987    nullptr
4988  };
4989
4990  extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
4991    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],
4992    CPU16Regs_and_GPRMM16ZeroSubClassMask,
4993    SuperRegIdxSeqs + 0,
4994    LaneBitmask(0x00000001),
4995    0,
4996    false, /* HasDisjunctSubRegs */
4997    false, /* CoveredBySubRegs */
4998    CPU16Regs_and_GPRMM16ZeroSuperclasses,
4999    nullptr
5000  };
5001
5002  extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
5003    &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],
5004    GPR32NONZERO_and_GPRMM16MovePSubClassMask,
5005    SuperRegIdxSeqs + 0,
5006    LaneBitmask(0x00000001),
5007    0,
5008    false, /* HasDisjunctSubRegs */
5009    false, /* CoveredBySubRegs */
5010    GPR32NONZERO_and_GPRMM16MovePSuperclasses,
5011    nullptr
5012  };
5013
5014  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
5015    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],
5016    CPU16Regs_and_GPRMM16MovePSubClassMask,
5017    SuperRegIdxSeqs + 0,
5018    LaneBitmask(0x00000001),
5019    0,
5020    false, /* HasDisjunctSubRegs */
5021    false, /* CoveredBySubRegs */
5022    CPU16Regs_and_GPRMM16MovePSuperclasses,
5023    nullptr
5024  };
5025
5026  extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5027    &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
5028    GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
5029    SuperRegIdxSeqs + 0,
5030    LaneBitmask(0x00000001),
5031    0,
5032    false, /* HasDisjunctSubRegs */
5033    false, /* CoveredBySubRegs */
5034    GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
5035    nullptr
5036  };
5037
5038  extern const TargetRegisterClass HI32DSPRegClass = {
5039    &MipsMCRegisterClasses[HI32DSPRegClassID],
5040    HI32DSPSubClassMask,
5041    SuperRegIdxSeqs + 13,
5042    LaneBitmask(0x00000001),
5043    0,
5044    false, /* HasDisjunctSubRegs */
5045    false, /* CoveredBySubRegs */
5046    NullRegClasses,
5047    nullptr
5048  };
5049
5050  extern const TargetRegisterClass LO32DSPRegClass = {
5051    &MipsMCRegisterClasses[LO32DSPRegClassID],
5052    LO32DSPSubClassMask,
5053    SuperRegIdxSeqs + 6,
5054    LaneBitmask(0x00000001),
5055    0,
5056    false, /* HasDisjunctSubRegs */
5057    false, /* CoveredBySubRegs */
5058    NullRegClasses,
5059    nullptr
5060  };
5061
5062  extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5063    &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
5064    GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5065    SuperRegIdxSeqs + 0,
5066    LaneBitmask(0x00000001),
5067    0,
5068    false, /* HasDisjunctSubRegs */
5069    false, /* CoveredBySubRegs */
5070    GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5071    nullptr
5072  };
5073
5074  extern const TargetRegisterClass CPURARegRegClass = {
5075    &MipsMCRegisterClasses[CPURARegRegClassID],
5076    CPURARegSubClassMask,
5077    SuperRegIdxSeqs + 0,
5078    LaneBitmask(0x00000001),
5079    0,
5080    false, /* HasDisjunctSubRegs */
5081    false, /* CoveredBySubRegs */
5082    CPURARegSuperclasses,
5083    nullptr
5084  };
5085
5086  extern const TargetRegisterClass CPUSPRegRegClass = {
5087    &MipsMCRegisterClasses[CPUSPRegRegClassID],
5088    CPUSPRegSubClassMask,
5089    SuperRegIdxSeqs + 0,
5090    LaneBitmask(0x00000001),
5091    0,
5092    false, /* HasDisjunctSubRegs */
5093    false, /* CoveredBySubRegs */
5094    CPUSPRegSuperclasses,
5095    nullptr
5096  };
5097
5098  extern const TargetRegisterClass DSPCCRegClass = {
5099    &MipsMCRegisterClasses[DSPCCRegClassID],
5100    DSPCCSubClassMask,
5101    SuperRegIdxSeqs + 1,
5102    LaneBitmask(0x00000001),
5103    0,
5104    false, /* HasDisjunctSubRegs */
5105    false, /* CoveredBySubRegs */
5106    NullRegClasses,
5107    nullptr
5108  };
5109
5110  extern const TargetRegisterClass GP32RegClass = {
5111    &MipsMCRegisterClasses[GP32RegClassID],
5112    GP32SubClassMask,
5113    SuperRegIdxSeqs + 0,
5114    LaneBitmask(0x00000001),
5115    0,
5116    false, /* HasDisjunctSubRegs */
5117    false, /* CoveredBySubRegs */
5118    GP32Superclasses,
5119    nullptr
5120  };
5121
5122  extern const TargetRegisterClass GPR32ZERORegClass = {
5123    &MipsMCRegisterClasses[GPR32ZERORegClassID],
5124    GPR32ZEROSubClassMask,
5125    SuperRegIdxSeqs + 0,
5126    LaneBitmask(0x00000001),
5127    0,
5128    false, /* HasDisjunctSubRegs */
5129    false, /* CoveredBySubRegs */
5130    GPR32ZEROSuperclasses,
5131    nullptr
5132  };
5133
5134  extern const TargetRegisterClass HI32RegClass = {
5135    &MipsMCRegisterClasses[HI32RegClassID],
5136    HI32SubClassMask,
5137    SuperRegIdxSeqs + 13,
5138    LaneBitmask(0x00000001),
5139    0,
5140    false, /* HasDisjunctSubRegs */
5141    false, /* CoveredBySubRegs */
5142    HI32Superclasses,
5143    nullptr
5144  };
5145
5146  extern const TargetRegisterClass LO32RegClass = {
5147    &MipsMCRegisterClasses[LO32RegClassID],
5148    LO32SubClassMask,
5149    SuperRegIdxSeqs + 6,
5150    LaneBitmask(0x00000001),
5151    0,
5152    false, /* HasDisjunctSubRegs */
5153    false, /* CoveredBySubRegs */
5154    LO32Superclasses,
5155    nullptr
5156  };
5157
5158  extern const TargetRegisterClass SP32RegClass = {
5159    &MipsMCRegisterClasses[SP32RegClassID],
5160    SP32SubClassMask,
5161    SuperRegIdxSeqs + 0,
5162    LaneBitmask(0x00000001),
5163    0,
5164    false, /* HasDisjunctSubRegs */
5165    false, /* CoveredBySubRegs */
5166    SP32Superclasses,
5167    nullptr
5168  };
5169
5170  extern const TargetRegisterClass FGR64RegClass = {
5171    &MipsMCRegisterClasses[FGR64RegClassID],
5172    FGR64SubClassMask,
5173    SuperRegIdxSeqs + 2,
5174    LaneBitmask(0x00000041),
5175    0,
5176    true, /* HasDisjunctSubRegs */
5177    true, /* CoveredBySubRegs */
5178    NullRegClasses,
5179    nullptr
5180  };
5181
5182  extern const TargetRegisterClass GPR64RegClass = {
5183    &MipsMCRegisterClasses[GPR64RegClassID],
5184    GPR64SubClassMask,
5185    SuperRegIdxSeqs + 1,
5186    LaneBitmask(0x00000001),
5187    0,
5188    false, /* HasDisjunctSubRegs */
5189    false, /* CoveredBySubRegs */
5190    NullRegClasses,
5191    nullptr
5192  };
5193
5194  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
5195    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],
5196    GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,
5197    SuperRegIdxSeqs + 1,
5198    LaneBitmask(0x00000001),
5199    0,
5200    false, /* HasDisjunctSubRegs */
5201    false, /* CoveredBySubRegs */
5202    GPR64_with_sub_32_in_GPR32NONZEROSuperclasses,
5203    nullptr
5204  };
5205
5206  extern const TargetRegisterClass AFGR64RegClass = {
5207    &MipsMCRegisterClasses[AFGR64RegClassID],
5208    AFGR64SubClassMask,
5209    SuperRegIdxSeqs + 1,
5210    LaneBitmask(0x00000041),
5211    0,
5212    true, /* HasDisjunctSubRegs */
5213    true, /* CoveredBySubRegs */
5214    NullRegClasses,
5215    nullptr
5216  };
5217
5218  extern const TargetRegisterClass FGR64_and_OddSPRegClass = {
5219    &MipsMCRegisterClasses[FGR64_and_OddSPRegClassID],
5220    FGR64_and_OddSPSubClassMask,
5221    SuperRegIdxSeqs + 2,
5222    LaneBitmask(0x00000041),
5223    0,
5224    true, /* HasDisjunctSubRegs */
5225    true, /* CoveredBySubRegs */
5226    FGR64_and_OddSPSuperclasses,
5227    nullptr
5228  };
5229
5230  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
5231    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],
5232    GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,
5233    SuperRegIdxSeqs + 1,
5234    LaneBitmask(0x00000001),
5235    0,
5236    false, /* HasDisjunctSubRegs */
5237    false, /* CoveredBySubRegs */
5238    GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses,
5239    nullptr
5240  };
5241
5242  extern const TargetRegisterClass AFGR64_and_OddSPRegClass = {
5243    &MipsMCRegisterClasses[AFGR64_and_OddSPRegClassID],
5244    AFGR64_and_OddSPSubClassMask,
5245    SuperRegIdxSeqs + 1,
5246    LaneBitmask(0x00000041),
5247    0,
5248    true, /* HasDisjunctSubRegs */
5249    true, /* CoveredBySubRegs */
5250    AFGR64_and_OddSPSuperclasses,
5251    nullptr
5252  };
5253
5254  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {
5255    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],
5256    GPR64_with_sub_32_in_CPU16RegsSubClassMask,
5257    SuperRegIdxSeqs + 1,
5258    LaneBitmask(0x00000001),
5259    0,
5260    false, /* HasDisjunctSubRegs */
5261    false, /* CoveredBySubRegs */
5262    GPR64_with_sub_32_in_CPU16RegsSuperclasses,
5263    nullptr
5264  };
5265
5266  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {
5267    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],
5268    GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,
5269    SuperRegIdxSeqs + 1,
5270    LaneBitmask(0x00000001),
5271    0,
5272    false, /* HasDisjunctSubRegs */
5273    false, /* CoveredBySubRegs */
5274    GPR64_with_sub_32_in_GPRMM16MovePSuperclasses,
5275    nullptr
5276  };
5277
5278  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {
5279    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],
5280    GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,
5281    SuperRegIdxSeqs + 1,
5282    LaneBitmask(0x00000001),
5283    0,
5284    false, /* HasDisjunctSubRegs */
5285    false, /* CoveredBySubRegs */
5286    GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses,
5287    nullptr
5288  };
5289
5290  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {
5291    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],
5292    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5293    SuperRegIdxSeqs + 1,
5294    LaneBitmask(0x00000001),
5295    0,
5296    false, /* HasDisjunctSubRegs */
5297    false, /* CoveredBySubRegs */
5298    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5299    nullptr
5300  };
5301
5302  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {
5303    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],
5304    GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,
5305    SuperRegIdxSeqs + 1,
5306    LaneBitmask(0x00000001),
5307    0,
5308    false, /* HasDisjunctSubRegs */
5309    false, /* CoveredBySubRegs */
5310    GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses,
5311    nullptr
5312  };
5313
5314  extern const TargetRegisterClass ACC64DSPRegClass = {
5315    &MipsMCRegisterClasses[ACC64DSPRegClassID],
5316    ACC64DSPSubClassMask,
5317    SuperRegIdxSeqs + 17,
5318    LaneBitmask(0x00000041),
5319    0,
5320    true, /* HasDisjunctSubRegs */
5321    true, /* CoveredBySubRegs */
5322    NullRegClasses,
5323    nullptr
5324  };
5325
5326  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {
5327    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],
5328    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,
5329    SuperRegIdxSeqs + 1,
5330    LaneBitmask(0x00000001),
5331    0,
5332    false, /* HasDisjunctSubRegs */
5333    false, /* CoveredBySubRegs */
5334    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses,
5335    nullptr
5336  };
5337
5338  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5339    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
5340    GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
5341    SuperRegIdxSeqs + 1,
5342    LaneBitmask(0x00000001),
5343    0,
5344    false, /* HasDisjunctSubRegs */
5345    false, /* CoveredBySubRegs */
5346    GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
5347    nullptr
5348  };
5349
5350  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5351    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
5352    GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5353    SuperRegIdxSeqs + 1,
5354    LaneBitmask(0x00000001),
5355    0,
5356    false, /* HasDisjunctSubRegs */
5357    false, /* CoveredBySubRegs */
5358    GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5359    nullptr
5360  };
5361
5362  extern const TargetRegisterClass OCTEON_MPLRegClass = {
5363    &MipsMCRegisterClasses[OCTEON_MPLRegClassID],
5364    OCTEON_MPLSubClassMask,
5365    SuperRegIdxSeqs + 1,
5366    LaneBitmask(0x00000001),
5367    0,
5368    false, /* HasDisjunctSubRegs */
5369    false, /* CoveredBySubRegs */
5370    NullRegClasses,
5371    nullptr
5372  };
5373
5374  extern const TargetRegisterClass OCTEON_PRegClass = {
5375    &MipsMCRegisterClasses[OCTEON_PRegClassID],
5376    OCTEON_PSubClassMask,
5377    SuperRegIdxSeqs + 1,
5378    LaneBitmask(0x00000001),
5379    0,
5380    false, /* HasDisjunctSubRegs */
5381    false, /* CoveredBySubRegs */
5382    NullRegClasses,
5383    nullptr
5384  };
5385
5386  extern const TargetRegisterClass ACC64RegClass = {
5387    &MipsMCRegisterClasses[ACC64RegClassID],
5388    ACC64SubClassMask,
5389    SuperRegIdxSeqs + 17,
5390    LaneBitmask(0x00000041),
5391    0,
5392    true, /* HasDisjunctSubRegs */
5393    true, /* CoveredBySubRegs */
5394    ACC64Superclasses,
5395    nullptr
5396  };
5397
5398  extern const TargetRegisterClass GP64RegClass = {
5399    &MipsMCRegisterClasses[GP64RegClassID],
5400    GP64SubClassMask,
5401    SuperRegIdxSeqs + 1,
5402    LaneBitmask(0x00000001),
5403    0,
5404    false, /* HasDisjunctSubRegs */
5405    false, /* CoveredBySubRegs */
5406    GP64Superclasses,
5407    nullptr
5408  };
5409
5410  extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {
5411    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],
5412    GPR64_with_sub_32_in_CPURARegSubClassMask,
5413    SuperRegIdxSeqs + 1,
5414    LaneBitmask(0x00000001),
5415    0,
5416    false, /* HasDisjunctSubRegs */
5417    false, /* CoveredBySubRegs */
5418    GPR64_with_sub_32_in_CPURARegSuperclasses,
5419    nullptr
5420  };
5421
5422  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {
5423    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],
5424    GPR64_with_sub_32_in_GPR32ZEROSubClassMask,
5425    SuperRegIdxSeqs + 1,
5426    LaneBitmask(0x00000001),
5427    0,
5428    false, /* HasDisjunctSubRegs */
5429    false, /* CoveredBySubRegs */
5430    GPR64_with_sub_32_in_GPR32ZEROSuperclasses,
5431    nullptr
5432  };
5433
5434  extern const TargetRegisterClass HI64RegClass = {
5435    &MipsMCRegisterClasses[HI64RegClassID],
5436    HI64SubClassMask,
5437    SuperRegIdxSeqs + 4,
5438    LaneBitmask(0x00000001),
5439    0,
5440    false, /* HasDisjunctSubRegs */
5441    false, /* CoveredBySubRegs */
5442    NullRegClasses,
5443    nullptr
5444  };
5445
5446  extern const TargetRegisterClass LO64RegClass = {
5447    &MipsMCRegisterClasses[LO64RegClassID],
5448    LO64SubClassMask,
5449    SuperRegIdxSeqs + 7,
5450    LaneBitmask(0x00000001),
5451    0,
5452    false, /* HasDisjunctSubRegs */
5453    false, /* CoveredBySubRegs */
5454    NullRegClasses,
5455    nullptr
5456  };
5457
5458  extern const TargetRegisterClass SP64RegClass = {
5459    &MipsMCRegisterClasses[SP64RegClassID],
5460    SP64SubClassMask,
5461    SuperRegIdxSeqs + 1,
5462    LaneBitmask(0x00000001),
5463    0,
5464    false, /* HasDisjunctSubRegs */
5465    false, /* CoveredBySubRegs */
5466    SP64Superclasses,
5467    nullptr
5468  };
5469
5470  extern const TargetRegisterClass MSA128BRegClass = {
5471    &MipsMCRegisterClasses[MSA128BRegClassID],
5472    MSA128BSubClassMask,
5473    SuperRegIdxSeqs + 1,
5474    LaneBitmask(0x00000041),
5475    0,
5476    true, /* HasDisjunctSubRegs */
5477    false, /* CoveredBySubRegs */
5478    MSA128BSuperclasses,
5479    nullptr
5480  };
5481
5482  extern const TargetRegisterClass MSA128DRegClass = {
5483    &MipsMCRegisterClasses[MSA128DRegClassID],
5484    MSA128DSubClassMask,
5485    SuperRegIdxSeqs + 1,
5486    LaneBitmask(0x00000041),
5487    0,
5488    true, /* HasDisjunctSubRegs */
5489    false, /* CoveredBySubRegs */
5490    MSA128DSuperclasses,
5491    nullptr
5492  };
5493
5494  extern const TargetRegisterClass MSA128HRegClass = {
5495    &MipsMCRegisterClasses[MSA128HRegClassID],
5496    MSA128HSubClassMask,
5497    SuperRegIdxSeqs + 1,
5498    LaneBitmask(0x00000041),
5499    0,
5500    true, /* HasDisjunctSubRegs */
5501    false, /* CoveredBySubRegs */
5502    MSA128HSuperclasses,
5503    nullptr
5504  };
5505
5506  extern const TargetRegisterClass MSA128WRegClass = {
5507    &MipsMCRegisterClasses[MSA128WRegClassID],
5508    MSA128WSubClassMask,
5509    SuperRegIdxSeqs + 1,
5510    LaneBitmask(0x00000041),
5511    0,
5512    true, /* HasDisjunctSubRegs */
5513    false, /* CoveredBySubRegs */
5514    MSA128WSuperclasses,
5515    nullptr
5516  };
5517
5518  extern const TargetRegisterClass MSA128B_with_sub_64_in_OddSPRegClass = {
5519    &MipsMCRegisterClasses[MSA128B_with_sub_64_in_OddSPRegClassID],
5520    MSA128B_with_sub_64_in_OddSPSubClassMask,
5521    SuperRegIdxSeqs + 1,
5522    LaneBitmask(0x00000041),
5523    0,
5524    true, /* HasDisjunctSubRegs */
5525    false, /* CoveredBySubRegs */
5526    MSA128B_with_sub_64_in_OddSPSuperclasses,
5527    nullptr
5528  };
5529
5530  extern const TargetRegisterClass MSA128WEvensRegClass = {
5531    &MipsMCRegisterClasses[MSA128WEvensRegClassID],
5532    MSA128WEvensSubClassMask,
5533    SuperRegIdxSeqs + 1,
5534    LaneBitmask(0x00000041),
5535    0,
5536    true, /* HasDisjunctSubRegs */
5537    false, /* CoveredBySubRegs */
5538    MSA128WEvensSuperclasses,
5539    nullptr
5540  };
5541
5542  extern const TargetRegisterClass ACC128RegClass = {
5543    &MipsMCRegisterClasses[ACC128RegClassID],
5544    ACC128SubClassMask,
5545    SuperRegIdxSeqs + 1,
5546    LaneBitmask(0x00000041),
5547    0,
5548    true, /* HasDisjunctSubRegs */
5549    true, /* CoveredBySubRegs */
5550    NullRegClasses,
5551    nullptr
5552  };
5553
5554} // end namespace Mips
5555
5556namespace {
5557  const TargetRegisterClass* const RegisterClasses[] = {
5558    &Mips::MSA128F16RegClass,
5559    &Mips::MSA128F16_with_sub_64_in_OddSPRegClass,
5560    &Mips::OddSPRegClass,
5561    &Mips::CCRRegClass,
5562    &Mips::COP0RegClass,
5563    &Mips::COP2RegClass,
5564    &Mips::COP3RegClass,
5565    &Mips::DSPRRegClass,
5566    &Mips::FGR32RegClass,
5567    &Mips::FGRCCRegClass,
5568    &Mips::FGRH32RegClass,
5569    &Mips::GPR32RegClass,
5570    &Mips::HWRegsRegClass,
5571    &Mips::GPR32NONZERORegClass,
5572    &Mips::OddSP_with_sub_hiRegClass,
5573    &Mips::FGR32_and_OddSPRegClass,
5574    &Mips::FGRH32_and_OddSPRegClass,
5575    &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass,
5576    &Mips::CPU16RegsPlusSPRegClass,
5577    &Mips::CPU16RegsRegClass,
5578    &Mips::FCCRegClass,
5579    &Mips::GPRMM16RegClass,
5580    &Mips::GPRMM16MovePRegClass,
5581    &Mips::GPRMM16ZeroRegClass,
5582    &Mips::MSACtrlRegClass,
5583    &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass,
5584    &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
5585    &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
5586    &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
5587    &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
5588    &Mips::HI32DSPRegClass,
5589    &Mips::LO32DSPRegClass,
5590    &Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
5591    &Mips::CPURARegRegClass,
5592    &Mips::CPUSPRegRegClass,
5593    &Mips::DSPCCRegClass,
5594    &Mips::GP32RegClass,
5595    &Mips::GPR32ZERORegClass,
5596    &Mips::HI32RegClass,
5597    &Mips::LO32RegClass,
5598    &Mips::SP32RegClass,
5599    &Mips::FGR64RegClass,
5600    &Mips::GPR64RegClass,
5601    &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
5602    &Mips::AFGR64RegClass,
5603    &Mips::FGR64_and_OddSPRegClass,
5604    &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
5605    &Mips::AFGR64_and_OddSPRegClass,
5606    &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
5607    &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
5608    &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
5609    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
5610    &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
5611    &Mips::ACC64DSPRegClass,
5612    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
5613    &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
5614    &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
5615    &Mips::OCTEON_MPLRegClass,
5616    &Mips::OCTEON_PRegClass,
5617    &Mips::ACC64RegClass,
5618    &Mips::GP64RegClass,
5619    &Mips::GPR64_with_sub_32_in_CPURARegRegClass,
5620    &Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,
5621    &Mips::HI64RegClass,
5622    &Mips::LO64RegClass,
5623    &Mips::SP64RegClass,
5624    &Mips::MSA128BRegClass,
5625    &Mips::MSA128DRegClass,
5626    &Mips::MSA128HRegClass,
5627    &Mips::MSA128WRegClass,
5628    &Mips::MSA128B_with_sub_64_in_OddSPRegClass,
5629    &Mips::MSA128WEvensRegClass,
5630    &Mips::ACC128RegClass,
5631  };
5632} // end anonymous namespace
5633
5634static const TargetRegisterInfoDesc MipsRegInfoDesc[] = { // Extra Descriptors
5635  { 0, false },
5636  { 0, true },
5637  { 0, true },
5638  { 0, false },
5639  { 0, false },
5640  { 0, false },
5641  { 0, false },
5642  { 0, false },
5643  { 0, true },
5644  { 0, true },
5645  { 0, true },
5646  { 0, true },
5647  { 0, true },
5648  { 0, true },
5649  { 0, true },
5650  { 0, true },
5651  { 0, true },
5652  { 0, true },
5653  { 0, false },
5654  { 0, true },
5655  { 0, true },
5656  { 0, true },
5657  { 0, true },
5658  { 0, true },
5659  { 0, true },
5660  { 0, true },
5661  { 0, true },
5662  { 0, true },
5663  { 0, true },
5664  { 0, true },
5665  { 0, true },
5666  { 0, false },
5667  { 0, false },
5668  { 0, false },
5669  { 0, false },
5670  { 0, false },
5671  { 0, false },
5672  { 0, false },
5673  { 0, false },
5674  { 0, false },
5675  { 0, false },
5676  { 0, false },
5677  { 0, false },
5678  { 0, false },
5679  { 0, false },
5680  { 0, false },
5681  { 0, false },
5682  { 0, false },
5683  { 0, false },
5684  { 0, false },
5685  { 0, false },
5686  { 0, false },
5687  { 0, false },
5688  { 0, false },
5689  { 0, false },
5690  { 0, false },
5691  { 0, false },
5692  { 0, false },
5693  { 0, false },
5694  { 0, false },
5695  { 0, false },
5696  { 0, false },
5697  { 0, false },
5698  { 0, false },
5699  { 0, false },
5700  { 0, false },
5701  { 0, false },
5702  { 0, false },
5703  { 0, false },
5704  { 0, false },
5705  { 0, false },
5706  { 0, false },
5707  { 0, false },
5708  { 0, false },
5709  { 0, false },
5710  { 0, false },
5711  { 0, false },
5712  { 0, false },
5713  { 0, false },
5714  { 0, false },
5715  { 0, false },
5716  { 0, false },
5717  { 0, false },
5718  { 0, false },
5719  { 0, false },
5720  { 0, false },
5721  { 0, false },
5722  { 0, false },
5723  { 0, false },
5724  { 0, false },
5725  { 0, false },
5726  { 0, false },
5727  { 0, false },
5728  { 0, false },
5729  { 0, false },
5730  { 0, false },
5731  { 0, false },
5732  { 0, false },
5733  { 0, false },
5734  { 0, false },
5735  { 0, false },
5736  { 0, false },
5737  { 0, false },
5738  { 0, false },
5739  { 0, false },
5740  { 0, false },
5741  { 0, false },
5742  { 0, false },
5743  { 0, false },
5744  { 0, false },
5745  { 0, false },
5746  { 0, false },
5747  { 0, false },
5748  { 0, false },
5749  { 0, false },
5750  { 0, false },
5751  { 0, false },
5752  { 0, false },
5753  { 0, false },
5754  { 0, false },
5755  { 0, false },
5756  { 0, false },
5757  { 0, false },
5758  { 0, false },
5759  { 0, false },
5760  { 0, false },
5761  { 0, false },
5762  { 0, true },
5763  { 0, true },
5764  { 0, true },
5765  { 0, true },
5766  { 0, true },
5767  { 0, true },
5768  { 0, true },
5769  { 0, true },
5770  { 0, true },
5771  { 0, true },
5772  { 0, true },
5773  { 0, true },
5774  { 0, true },
5775  { 0, true },
5776  { 0, true },
5777  { 0, true },
5778  { 0, false },
5779  { 0, false },
5780  { 0, false },
5781  { 0, false },
5782  { 0, true },
5783  { 0, true },
5784  { 0, true },
5785  { 0, true },
5786  { 0, true },
5787  { 0, true },
5788  { 0, true },
5789  { 0, true },
5790  { 0, true },
5791  { 0, true },
5792  { 0, true },
5793  { 0, true },
5794  { 0, true },
5795  { 0, true },
5796  { 0, true },
5797  { 0, true },
5798  { 0, true },
5799  { 0, true },
5800  { 0, true },
5801  { 0, true },
5802  { 0, true },
5803  { 0, true },
5804  { 0, true },
5805  { 0, true },
5806  { 0, true },
5807  { 0, true },
5808  { 0, true },
5809  { 0, true },
5810  { 0, true },
5811  { 0, true },
5812  { 0, true },
5813  { 0, true },
5814  { 0, false },
5815  { 0, false },
5816  { 0, false },
5817  { 0, false },
5818  { 0, false },
5819  { 0, false },
5820  { 0, false },
5821  { 0, false },
5822  { 0, false },
5823  { 0, false },
5824  { 0, false },
5825  { 0, false },
5826  { 0, false },
5827  { 0, false },
5828  { 0, false },
5829  { 0, false },
5830  { 0, false },
5831  { 0, false },
5832  { 0, false },
5833  { 0, false },
5834  { 0, false },
5835  { 0, false },
5836  { 0, false },
5837  { 0, false },
5838  { 0, false },
5839  { 0, false },
5840  { 0, false },
5841  { 0, false },
5842  { 0, false },
5843  { 0, false },
5844  { 0, false },
5845  { 0, false },
5846  { 0, false },
5847  { 0, false },
5848  { 0, false },
5849  { 0, false },
5850  { 0, false },
5851  { 0, false },
5852  { 0, false },
5853  { 0, false },
5854  { 0, true },
5855  { 0, false },
5856  { 0, false },
5857  { 0, false },
5858  { 0, false },
5859  { 0, false },
5860  { 0, false },
5861  { 0, false },
5862  { 0, false },
5863  { 0, false },
5864  { 0, false },
5865  { 0, false },
5866  { 0, false },
5867  { 0, false },
5868  { 0, false },
5869  { 0, false },
5870  { 0, false },
5871  { 0, false },
5872  { 0, false },
5873  { 0, false },
5874  { 0, false },
5875  { 0, false },
5876  { 0, false },
5877  { 0, false },
5878  { 0, false },
5879  { 0, false },
5880  { 0, false },
5881  { 0, false },
5882  { 0, false },
5883  { 0, false },
5884  { 0, false },
5885  { 0, false },
5886  { 0, false },
5887  { 0, true },
5888  { 0, true },
5889  { 0, true },
5890  { 0, true },
5891  { 0, true },
5892  { 0, false },
5893  { 0, false },
5894  { 0, false },
5895  { 0, false },
5896  { 0, false },
5897  { 0, false },
5898  { 0, false },
5899  { 0, false },
5900  { 0, false },
5901  { 0, false },
5902  { 0, false },
5903  { 0, false },
5904  { 0, false },
5905  { 0, false },
5906  { 0, false },
5907  { 0, false },
5908  { 0, false },
5909  { 0, false },
5910  { 0, false },
5911  { 0, false },
5912  { 0, false },
5913  { 0, false },
5914  { 0, false },
5915  { 0, false },
5916  { 0, false },
5917  { 0, false },
5918  { 0, false },
5919  { 0, false },
5920  { 0, false },
5921  { 0, false },
5922  { 0, false },
5923  { 0, false },
5924  { 0, true },
5925  { 0, true },
5926  { 0, true },
5927  { 0, true },
5928  { 0, true },
5929  { 0, true },
5930  { 0, false },
5931  { 0, false },
5932  { 0, false },
5933  { 0, false },
5934  { 0, false },
5935  { 0, false },
5936  { 0, true },
5937  { 0, true },
5938  { 0, true },
5939  { 0, true },
5940  { 0, true },
5941  { 0, true },
5942  { 0, true },
5943  { 0, true },
5944  { 0, true },
5945  { 0, true },
5946  { 0, true },
5947  { 0, true },
5948  { 0, true },
5949  { 0, true },
5950  { 0, true },
5951  { 0, true },
5952  { 0, true },
5953  { 0, true },
5954  { 0, true },
5955  { 0, true },
5956  { 0, true },
5957  { 0, true },
5958  { 0, true },
5959  { 0, true },
5960  { 0, true },
5961  { 0, true },
5962  { 0, true },
5963  { 0, true },
5964  { 0, true },
5965  { 0, true },
5966  { 0, true },
5967  { 0, true },
5968  { 0, true },
5969  { 0, true },
5970  { 0, true },
5971  { 0, true },
5972  { 0, true },
5973  { 0, true },
5974  { 0, true },
5975  { 0, true },
5976  { 0, true },
5977  { 0, true },
5978  { 0, true },
5979  { 0, true },
5980  { 0, true },
5981  { 0, true },
5982  { 0, true },
5983  { 0, true },
5984  { 0, true },
5985  { 0, true },
5986  { 0, true },
5987  { 0, true },
5988  { 0, true },
5989  { 0, true },
5990  { 0, true },
5991  { 0, true },
5992  { 0, true },
5993  { 0, true },
5994  { 0, true },
5995  { 0, true },
5996  { 0, true },
5997  { 0, true },
5998  { 0, true },
5999  { 0, true },
6000  { 0, true },
6001  { 0, true },
6002  { 0, true },
6003  { 0, true },
6004  { 0, true },
6005  { 0, true },
6006  { 0, true },
6007  { 0, true },
6008  { 0, true },
6009  { 0, true },
6010  { 0, true },
6011  { 0, true },
6012  { 0, true },
6013  { 0, true },
6014  { 0, true },
6015  { 0, true },
6016  { 0, true },
6017  { 0, true },
6018  { 0, true },
6019  { 0, true },
6020  { 0, true },
6021  { 0, true },
6022  { 0, true },
6023  { 0, true },
6024  { 0, true },
6025  { 0, true },
6026  { 0, true },
6027  { 0, true },
6028  { 0, false },
6029  { 0, true },
6030  { 0, true },
6031  { 0, true },
6032  { 0, true },
6033  { 0, true },
6034  { 0, true },
6035  { 0, true },
6036  { 0, true },
6037  { 0, true },
6038  { 0, true },
6039  { 0, true },
6040  { 0, true },
6041  { 0, true },
6042  { 0, true },
6043  { 0, true },
6044  { 0, true },
6045  { 0, true },
6046  { 0, true },
6047  { 0, true },
6048  { 0, true },
6049  { 0, true },
6050  { 0, true },
6051  { 0, true },
6052  { 0, true },
6053};
6054unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
6055  static const uint8_t RowMap[11] = {
6056    0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
6057  };
6058  static const uint8_t Rows[2][11] = {
6059    { 10, 0, 0, 0, 0, 0, 0, 8, 9, 0, 0, },
6060    { 1, 0, 0, 0, 0, 0, 0, 10, 1, 0, 0, },
6061  };
6062
6063  --IdxA; assert(IdxA < 11);
6064  --IdxB; assert(IdxB < 11);
6065  return Rows[RowMap[IdxA]][IdxB];
6066}
6067
6068  struct MaskRolOp {
6069    LaneBitmask Mask;
6070    uint8_t  RotateLeft;
6071  };
6072  static const MaskRolOp LaneMaskComposeSequences[] = {
6073    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
6074    { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
6075    { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
6076    { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
6077    { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
6078    { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
6079    { LaneBitmask(0xFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 }  // Sequence 12
6080  };
6081  static const MaskRolOp *const CompositeSequences[] = {
6082    &LaneMaskComposeSequences[0], // to sub_32
6083    &LaneMaskComposeSequences[0], // to sub_64
6084    &LaneMaskComposeSequences[2], // to sub_dsp16_19
6085    &LaneMaskComposeSequences[4], // to sub_dsp20
6086    &LaneMaskComposeSequences[6], // to sub_dsp21
6087    &LaneMaskComposeSequences[8], // to sub_dsp22
6088    &LaneMaskComposeSequences[10], // to sub_dsp23
6089    &LaneMaskComposeSequences[12], // to sub_hi
6090    &LaneMaskComposeSequences[0], // to sub_lo
6091    &LaneMaskComposeSequences[12], // to sub_hi_then_sub_32
6092    &LaneMaskComposeSequences[0] // to sub_32_sub_hi_then_sub_32
6093  };
6094
6095LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
6096  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
6097  LaneBitmask Result;
6098  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
6099    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
6100    if (unsigned S = Ops->RotateLeft)
6101      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
6102    else
6103      Result |= LaneBitmask(M);
6104  }
6105  return Result;
6106}
6107
6108LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
6109  LaneMask &= getSubRegIndexLaneMask(IdxA);
6110  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
6111  LaneBitmask Result;
6112  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
6113    LaneBitmask::Type M = LaneMask.getAsInteger();
6114    if (unsigned S = Ops->RotateLeft)
6115      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
6116    else
6117      Result |= LaneBitmask(M);
6118  }
6119  return Result;
6120}
6121
6122const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
6123  static const uint8_t Table[73][11] = {
6124    {	// MSA128F16
6125      0,	// sub_32
6126      1,	// sub_64 -> MSA128F16
6127      0,	// sub_dsp16_19
6128      0,	// sub_dsp20
6129      0,	// sub_dsp21
6130      0,	// sub_dsp22
6131      0,	// sub_dsp23
6132      1,	// sub_hi -> MSA128F16
6133      1,	// sub_lo -> MSA128F16
6134      0,	// sub_hi_then_sub_32
6135      0,	// sub_32_sub_hi_then_sub_32
6136    },
6137    {	// MSA128F16_with_sub_64_in_OddSP
6138      0,	// sub_32
6139      2,	// sub_64 -> MSA128F16_with_sub_64_in_OddSP
6140      0,	// sub_dsp16_19
6141      0,	// sub_dsp20
6142      0,	// sub_dsp21
6143      0,	// sub_dsp22
6144      0,	// sub_dsp23
6145      2,	// sub_hi -> MSA128F16_with_sub_64_in_OddSP
6146      2,	// sub_lo -> MSA128F16_with_sub_64_in_OddSP
6147      0,	// sub_hi_then_sub_32
6148      0,	// sub_32_sub_hi_then_sub_32
6149    },
6150    {	// OddSP
6151      0,	// sub_32
6152      0,	// sub_64
6153      0,	// sub_dsp16_19
6154      0,	// sub_dsp20
6155      0,	// sub_dsp21
6156      0,	// sub_dsp22
6157      0,	// sub_dsp23
6158      15,	// sub_hi -> OddSP_with_sub_hi
6159      15,	// sub_lo -> OddSP_with_sub_hi
6160      0,	// sub_hi_then_sub_32
6161      0,	// sub_32_sub_hi_then_sub_32
6162    },
6163    {	// CCR
6164      0,	// sub_32
6165      0,	// sub_64
6166      0,	// sub_dsp16_19
6167      0,	// sub_dsp20
6168      0,	// sub_dsp21
6169      0,	// sub_dsp22
6170      0,	// sub_dsp23
6171      0,	// sub_hi
6172      0,	// sub_lo
6173      0,	// sub_hi_then_sub_32
6174      0,	// sub_32_sub_hi_then_sub_32
6175    },
6176    {	// COP0
6177      0,	// sub_32
6178      0,	// sub_64
6179      0,	// sub_dsp16_19
6180      0,	// sub_dsp20
6181      0,	// sub_dsp21
6182      0,	// sub_dsp22
6183      0,	// sub_dsp23
6184      0,	// sub_hi
6185      0,	// sub_lo
6186      0,	// sub_hi_then_sub_32
6187      0,	// sub_32_sub_hi_then_sub_32
6188    },
6189    {	// COP2
6190      0,	// sub_32
6191      0,	// sub_64
6192      0,	// sub_dsp16_19
6193      0,	// sub_dsp20
6194      0,	// sub_dsp21
6195      0,	// sub_dsp22
6196      0,	// sub_dsp23
6197      0,	// sub_hi
6198      0,	// sub_lo
6199      0,	// sub_hi_then_sub_32
6200      0,	// sub_32_sub_hi_then_sub_32
6201    },
6202    {	// COP3
6203      0,	// sub_32
6204      0,	// sub_64
6205      0,	// sub_dsp16_19
6206      0,	// sub_dsp20
6207      0,	// sub_dsp21
6208      0,	// sub_dsp22
6209      0,	// sub_dsp23
6210      0,	// sub_hi
6211      0,	// sub_lo
6212      0,	// sub_hi_then_sub_32
6213      0,	// sub_32_sub_hi_then_sub_32
6214    },
6215    {	// DSPR
6216      0,	// sub_32
6217      0,	// sub_64
6218      0,	// sub_dsp16_19
6219      0,	// sub_dsp20
6220      0,	// sub_dsp21
6221      0,	// sub_dsp22
6222      0,	// sub_dsp23
6223      0,	// sub_hi
6224      0,	// sub_lo
6225      0,	// sub_hi_then_sub_32
6226      0,	// sub_32_sub_hi_then_sub_32
6227    },
6228    {	// FGR32
6229      0,	// sub_32
6230      0,	// sub_64
6231      0,	// sub_dsp16_19
6232      0,	// sub_dsp20
6233      0,	// sub_dsp21
6234      0,	// sub_dsp22
6235      0,	// sub_dsp23
6236      0,	// sub_hi
6237      0,	// sub_lo
6238      0,	// sub_hi_then_sub_32
6239      0,	// sub_32_sub_hi_then_sub_32
6240    },
6241    {	// FGRCC
6242      0,	// sub_32
6243      0,	// sub_64
6244      0,	// sub_dsp16_19
6245      0,	// sub_dsp20
6246      0,	// sub_dsp21
6247      0,	// sub_dsp22
6248      0,	// sub_dsp23
6249      0,	// sub_hi
6250      0,	// sub_lo
6251      0,	// sub_hi_then_sub_32
6252      0,	// sub_32_sub_hi_then_sub_32
6253    },
6254    {	// FGRH32
6255      0,	// sub_32
6256      0,	// sub_64
6257      0,	// sub_dsp16_19
6258      0,	// sub_dsp20
6259      0,	// sub_dsp21
6260      0,	// sub_dsp22
6261      0,	// sub_dsp23
6262      0,	// sub_hi
6263      0,	// sub_lo
6264      0,	// sub_hi_then_sub_32
6265      0,	// sub_32_sub_hi_then_sub_32
6266    },
6267    {	// GPR32
6268      0,	// sub_32
6269      0,	// sub_64
6270      0,	// sub_dsp16_19
6271      0,	// sub_dsp20
6272      0,	// sub_dsp21
6273      0,	// sub_dsp22
6274      0,	// sub_dsp23
6275      0,	// sub_hi
6276      0,	// sub_lo
6277      0,	// sub_hi_then_sub_32
6278      0,	// sub_32_sub_hi_then_sub_32
6279    },
6280    {	// HWRegs
6281      0,	// sub_32
6282      0,	// sub_64
6283      0,	// sub_dsp16_19
6284      0,	// sub_dsp20
6285      0,	// sub_dsp21
6286      0,	// sub_dsp22
6287      0,	// sub_dsp23
6288      0,	// sub_hi
6289      0,	// sub_lo
6290      0,	// sub_hi_then_sub_32
6291      0,	// sub_32_sub_hi_then_sub_32
6292    },
6293    {	// GPR32NONZERO
6294      0,	// sub_32
6295      0,	// sub_64
6296      0,	// sub_dsp16_19
6297      0,	// sub_dsp20
6298      0,	// sub_dsp21
6299      0,	// sub_dsp22
6300      0,	// sub_dsp23
6301      0,	// sub_hi
6302      0,	// sub_lo
6303      0,	// sub_hi_then_sub_32
6304      0,	// sub_32_sub_hi_then_sub_32
6305    },
6306    {	// OddSP_with_sub_hi
6307      0,	// sub_32
6308      0,	// sub_64
6309      0,	// sub_dsp16_19
6310      0,	// sub_dsp20
6311      0,	// sub_dsp21
6312      0,	// sub_dsp22
6313      0,	// sub_dsp23
6314      15,	// sub_hi -> OddSP_with_sub_hi
6315      15,	// sub_lo -> OddSP_with_sub_hi
6316      0,	// sub_hi_then_sub_32
6317      0,	// sub_32_sub_hi_then_sub_32
6318    },
6319    {	// FGR32_and_OddSP
6320      0,	// sub_32
6321      0,	// sub_64
6322      0,	// sub_dsp16_19
6323      0,	// sub_dsp20
6324      0,	// sub_dsp21
6325      0,	// sub_dsp22
6326      0,	// sub_dsp23
6327      0,	// sub_hi
6328      0,	// sub_lo
6329      0,	// sub_hi_then_sub_32
6330      0,	// sub_32_sub_hi_then_sub_32
6331    },
6332    {	// FGRH32_and_OddSP
6333      0,	// sub_32
6334      0,	// sub_64
6335      0,	// sub_dsp16_19
6336      0,	// sub_dsp20
6337      0,	// sub_dsp21
6338      0,	// sub_dsp22
6339      0,	// sub_dsp23
6340      0,	// sub_hi
6341      0,	// sub_lo
6342      0,	// sub_hi_then_sub_32
6343      0,	// sub_32_sub_hi_then_sub_32
6344    },
6345    {	// OddSP_with_sub_hi_with_sub_hi_in_FGRH32
6346      0,	// sub_32
6347      0,	// sub_64
6348      0,	// sub_dsp16_19
6349      0,	// sub_dsp20
6350      0,	// sub_dsp21
6351      0,	// sub_dsp22
6352      0,	// sub_dsp23
6353      18,	// sub_hi -> OddSP_with_sub_hi_with_sub_hi_in_FGRH32
6354      18,	// sub_lo -> OddSP_with_sub_hi_with_sub_hi_in_FGRH32
6355      0,	// sub_hi_then_sub_32
6356      0,	// sub_32_sub_hi_then_sub_32
6357    },
6358    {	// CPU16RegsPlusSP
6359      0,	// sub_32
6360      0,	// sub_64
6361      0,	// sub_dsp16_19
6362      0,	// sub_dsp20
6363      0,	// sub_dsp21
6364      0,	// sub_dsp22
6365      0,	// sub_dsp23
6366      0,	// sub_hi
6367      0,	// sub_lo
6368      0,	// sub_hi_then_sub_32
6369      0,	// sub_32_sub_hi_then_sub_32
6370    },
6371    {	// CPU16Regs
6372      0,	// sub_32
6373      0,	// sub_64
6374      0,	// sub_dsp16_19
6375      0,	// sub_dsp20
6376      0,	// sub_dsp21
6377      0,	// sub_dsp22
6378      0,	// sub_dsp23
6379      0,	// sub_hi
6380      0,	// sub_lo
6381      0,	// sub_hi_then_sub_32
6382      0,	// sub_32_sub_hi_then_sub_32
6383    },
6384    {	// FCC
6385      0,	// sub_32
6386      0,	// sub_64
6387      0,	// sub_dsp16_19
6388      0,	// sub_dsp20
6389      0,	// sub_dsp21
6390      0,	// sub_dsp22
6391      0,	// sub_dsp23
6392      0,	// sub_hi
6393      0,	// sub_lo
6394      0,	// sub_hi_then_sub_32
6395      0,	// sub_32_sub_hi_then_sub_32
6396    },
6397    {	// GPRMM16
6398      0,	// sub_32
6399      0,	// sub_64
6400      0,	// sub_dsp16_19
6401      0,	// sub_dsp20
6402      0,	// sub_dsp21
6403      0,	// sub_dsp22
6404      0,	// sub_dsp23
6405      0,	// sub_hi
6406      0,	// sub_lo
6407      0,	// sub_hi_then_sub_32
6408      0,	// sub_32_sub_hi_then_sub_32
6409    },
6410    {	// GPRMM16MoveP
6411      0,	// sub_32
6412      0,	// sub_64
6413      0,	// sub_dsp16_19
6414      0,	// sub_dsp20
6415      0,	// sub_dsp21
6416      0,	// sub_dsp22
6417      0,	// sub_dsp23
6418      0,	// sub_hi
6419      0,	// sub_lo
6420      0,	// sub_hi_then_sub_32
6421      0,	// sub_32_sub_hi_then_sub_32
6422    },
6423    {	// GPRMM16Zero
6424      0,	// sub_32
6425      0,	// sub_64
6426      0,	// sub_dsp16_19
6427      0,	// sub_dsp20
6428      0,	// sub_dsp21
6429      0,	// sub_dsp22
6430      0,	// sub_dsp23
6431      0,	// sub_hi
6432      0,	// sub_lo
6433      0,	// sub_hi_then_sub_32
6434      0,	// sub_32_sub_hi_then_sub_32
6435    },
6436    {	// MSACtrl
6437      0,	// sub_32
6438      0,	// sub_64
6439      0,	// sub_dsp16_19
6440      0,	// sub_dsp20
6441      0,	// sub_dsp21
6442      0,	// sub_dsp22
6443      0,	// sub_dsp23
6444      0,	// sub_hi
6445      0,	// sub_lo
6446      0,	// sub_hi_then_sub_32
6447      0,	// sub_32_sub_hi_then_sub_32
6448    },
6449    {	// OddSP_with_sub_hi_with_sub_hi_in_FGR32
6450      0,	// sub_32
6451      0,	// sub_64
6452      0,	// sub_dsp16_19
6453      0,	// sub_dsp20
6454      0,	// sub_dsp21
6455      0,	// sub_dsp22
6456      0,	// sub_dsp23
6457      26,	// sub_hi -> OddSP_with_sub_hi_with_sub_hi_in_FGR32
6458      26,	// sub_lo -> OddSP_with_sub_hi_with_sub_hi_in_FGR32
6459      0,	// sub_hi_then_sub_32
6460      0,	// sub_32_sub_hi_then_sub_32
6461    },
6462    {	// CPU16Regs_and_GPRMM16Zero
6463      0,	// sub_32
6464      0,	// sub_64
6465      0,	// sub_dsp16_19
6466      0,	// sub_dsp20
6467      0,	// sub_dsp21
6468      0,	// sub_dsp22
6469      0,	// sub_dsp23
6470      0,	// sub_hi
6471      0,	// sub_lo
6472      0,	// sub_hi_then_sub_32
6473      0,	// sub_32_sub_hi_then_sub_32
6474    },
6475    {	// GPR32NONZERO_and_GPRMM16MoveP
6476      0,	// sub_32
6477      0,	// sub_64
6478      0,	// sub_dsp16_19
6479      0,	// sub_dsp20
6480      0,	// sub_dsp21
6481      0,	// sub_dsp22
6482      0,	// sub_dsp23
6483      0,	// sub_hi
6484      0,	// sub_lo
6485      0,	// sub_hi_then_sub_32
6486      0,	// sub_32_sub_hi_then_sub_32
6487    },
6488    {	// CPU16Regs_and_GPRMM16MoveP
6489      0,	// sub_32
6490      0,	// sub_64
6491      0,	// sub_dsp16_19
6492      0,	// sub_dsp20
6493      0,	// sub_dsp21
6494      0,	// sub_dsp22
6495      0,	// sub_dsp23
6496      0,	// sub_hi
6497      0,	// sub_lo
6498      0,	// sub_hi_then_sub_32
6499      0,	// sub_32_sub_hi_then_sub_32
6500    },
6501    {	// GPRMM16MoveP_and_GPRMM16Zero
6502      0,	// sub_32
6503      0,	// sub_64
6504      0,	// sub_dsp16_19
6505      0,	// sub_dsp20
6506      0,	// sub_dsp21
6507      0,	// sub_dsp22
6508      0,	// sub_dsp23
6509      0,	// sub_hi
6510      0,	// sub_lo
6511      0,	// sub_hi_then_sub_32
6512      0,	// sub_32_sub_hi_then_sub_32
6513    },
6514    {	// HI32DSP
6515      0,	// sub_32
6516      0,	// sub_64
6517      0,	// sub_dsp16_19
6518      0,	// sub_dsp20
6519      0,	// sub_dsp21
6520      0,	// sub_dsp22
6521      0,	// sub_dsp23
6522      0,	// sub_hi
6523      0,	// sub_lo
6524      0,	// sub_hi_then_sub_32
6525      0,	// sub_32_sub_hi_then_sub_32
6526    },
6527    {	// LO32DSP
6528      0,	// sub_32
6529      0,	// sub_64
6530      0,	// sub_dsp16_19
6531      0,	// sub_dsp20
6532      0,	// sub_dsp21
6533      0,	// sub_dsp22
6534      0,	// sub_dsp23
6535      0,	// sub_hi
6536      0,	// sub_lo
6537      0,	// sub_hi_then_sub_32
6538      0,	// sub_32_sub_hi_then_sub_32
6539    },
6540    {	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6541      0,	// sub_32
6542      0,	// sub_64
6543      0,	// sub_dsp16_19
6544      0,	// sub_dsp20
6545      0,	// sub_dsp21
6546      0,	// sub_dsp22
6547      0,	// sub_dsp23
6548      0,	// sub_hi
6549      0,	// sub_lo
6550      0,	// sub_hi_then_sub_32
6551      0,	// sub_32_sub_hi_then_sub_32
6552    },
6553    {	// CPURAReg
6554      0,	// sub_32
6555      0,	// sub_64
6556      0,	// sub_dsp16_19
6557      0,	// sub_dsp20
6558      0,	// sub_dsp21
6559      0,	// sub_dsp22
6560      0,	// sub_dsp23
6561      0,	// sub_hi
6562      0,	// sub_lo
6563      0,	// sub_hi_then_sub_32
6564      0,	// sub_32_sub_hi_then_sub_32
6565    },
6566    {	// CPUSPReg
6567      0,	// sub_32
6568      0,	// sub_64
6569      0,	// sub_dsp16_19
6570      0,	// sub_dsp20
6571      0,	// sub_dsp21
6572      0,	// sub_dsp22
6573      0,	// sub_dsp23
6574      0,	// sub_hi
6575      0,	// sub_lo
6576      0,	// sub_hi_then_sub_32
6577      0,	// sub_32_sub_hi_then_sub_32
6578    },
6579    {	// DSPCC
6580      0,	// sub_32
6581      0,	// sub_64
6582      0,	// sub_dsp16_19
6583      0,	// sub_dsp20
6584      0,	// sub_dsp21
6585      0,	// sub_dsp22
6586      0,	// sub_dsp23
6587      0,	// sub_hi
6588      0,	// sub_lo
6589      0,	// sub_hi_then_sub_32
6590      0,	// sub_32_sub_hi_then_sub_32
6591    },
6592    {	// GP32
6593      0,	// sub_32
6594      0,	// sub_64
6595      0,	// sub_dsp16_19
6596      0,	// sub_dsp20
6597      0,	// sub_dsp21
6598      0,	// sub_dsp22
6599      0,	// sub_dsp23
6600      0,	// sub_hi
6601      0,	// sub_lo
6602      0,	// sub_hi_then_sub_32
6603      0,	// sub_32_sub_hi_then_sub_32
6604    },
6605    {	// GPR32ZERO
6606      0,	// sub_32
6607      0,	// sub_64
6608      0,	// sub_dsp16_19
6609      0,	// sub_dsp20
6610      0,	// sub_dsp21
6611      0,	// sub_dsp22
6612      0,	// sub_dsp23
6613      0,	// sub_hi
6614      0,	// sub_lo
6615      0,	// sub_hi_then_sub_32
6616      0,	// sub_32_sub_hi_then_sub_32
6617    },
6618    {	// HI32
6619      0,	// sub_32
6620      0,	// sub_64
6621      0,	// sub_dsp16_19
6622      0,	// sub_dsp20
6623      0,	// sub_dsp21
6624      0,	// sub_dsp22
6625      0,	// sub_dsp23
6626      0,	// sub_hi
6627      0,	// sub_lo
6628      0,	// sub_hi_then_sub_32
6629      0,	// sub_32_sub_hi_then_sub_32
6630    },
6631    {	// LO32
6632      0,	// sub_32
6633      0,	// sub_64
6634      0,	// sub_dsp16_19
6635      0,	// sub_dsp20
6636      0,	// sub_dsp21
6637      0,	// sub_dsp22
6638      0,	// sub_dsp23
6639      0,	// sub_hi
6640      0,	// sub_lo
6641      0,	// sub_hi_then_sub_32
6642      0,	// sub_32_sub_hi_then_sub_32
6643    },
6644    {	// SP32
6645      0,	// sub_32
6646      0,	// sub_64
6647      0,	// sub_dsp16_19
6648      0,	// sub_dsp20
6649      0,	// sub_dsp21
6650      0,	// sub_dsp22
6651      0,	// sub_dsp23
6652      0,	// sub_hi
6653      0,	// sub_lo
6654      0,	// sub_hi_then_sub_32
6655      0,	// sub_32_sub_hi_then_sub_32
6656    },
6657    {	// FGR64
6658      0,	// sub_32
6659      0,	// sub_64
6660      0,	// sub_dsp16_19
6661      0,	// sub_dsp20
6662      0,	// sub_dsp21
6663      0,	// sub_dsp22
6664      0,	// sub_dsp23
6665      42,	// sub_hi -> FGR64
6666      42,	// sub_lo -> FGR64
6667      0,	// sub_hi_then_sub_32
6668      0,	// sub_32_sub_hi_then_sub_32
6669    },
6670    {	// GPR64
6671      43,	// sub_32 -> GPR64
6672      0,	// sub_64
6673      0,	// sub_dsp16_19
6674      0,	// sub_dsp20
6675      0,	// sub_dsp21
6676      0,	// sub_dsp22
6677      0,	// sub_dsp23
6678      0,	// sub_hi
6679      0,	// sub_lo
6680      0,	// sub_hi_then_sub_32
6681      0,	// sub_32_sub_hi_then_sub_32
6682    },
6683    {	// GPR64_with_sub_32_in_GPR32NONZERO
6684      44,	// sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO
6685      0,	// sub_64
6686      0,	// sub_dsp16_19
6687      0,	// sub_dsp20
6688      0,	// sub_dsp21
6689      0,	// sub_dsp22
6690      0,	// sub_dsp23
6691      0,	// sub_hi
6692      0,	// sub_lo
6693      0,	// sub_hi_then_sub_32
6694      0,	// sub_32_sub_hi_then_sub_32
6695    },
6696    {	// AFGR64
6697      0,	// sub_32
6698      0,	// sub_64
6699      0,	// sub_dsp16_19
6700      0,	// sub_dsp20
6701      0,	// sub_dsp21
6702      0,	// sub_dsp22
6703      0,	// sub_dsp23
6704      45,	// sub_hi -> AFGR64
6705      45,	// sub_lo -> AFGR64
6706      0,	// sub_hi_then_sub_32
6707      0,	// sub_32_sub_hi_then_sub_32
6708    },
6709    {	// FGR64_and_OddSP
6710      0,	// sub_32
6711      0,	// sub_64
6712      0,	// sub_dsp16_19
6713      0,	// sub_dsp20
6714      0,	// sub_dsp21
6715      0,	// sub_dsp22
6716      0,	// sub_dsp23
6717      46,	// sub_hi -> FGR64_and_OddSP
6718      46,	// sub_lo -> FGR64_and_OddSP
6719      0,	// sub_hi_then_sub_32
6720      0,	// sub_32_sub_hi_then_sub_32
6721    },
6722    {	// GPR64_with_sub_32_in_CPU16RegsPlusSP
6723      47,	// sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP
6724      0,	// sub_64
6725      0,	// sub_dsp16_19
6726      0,	// sub_dsp20
6727      0,	// sub_dsp21
6728      0,	// sub_dsp22
6729      0,	// sub_dsp23
6730      0,	// sub_hi
6731      0,	// sub_lo
6732      0,	// sub_hi_then_sub_32
6733      0,	// sub_32_sub_hi_then_sub_32
6734    },
6735    {	// AFGR64_and_OddSP
6736      0,	// sub_32
6737      0,	// sub_64
6738      0,	// sub_dsp16_19
6739      0,	// sub_dsp20
6740      0,	// sub_dsp21
6741      0,	// sub_dsp22
6742      0,	// sub_dsp23
6743      48,	// sub_hi -> AFGR64_and_OddSP
6744      48,	// sub_lo -> AFGR64_and_OddSP
6745      0,	// sub_hi_then_sub_32
6746      0,	// sub_32_sub_hi_then_sub_32
6747    },
6748    {	// GPR64_with_sub_32_in_CPU16Regs
6749      49,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs
6750      0,	// sub_64
6751      0,	// sub_dsp16_19
6752      0,	// sub_dsp20
6753      0,	// sub_dsp21
6754      0,	// sub_dsp22
6755      0,	// sub_dsp23
6756      0,	// sub_hi
6757      0,	// sub_lo
6758      0,	// sub_hi_then_sub_32
6759      0,	// sub_32_sub_hi_then_sub_32
6760    },
6761    {	// GPR64_with_sub_32_in_GPRMM16MoveP
6762      50,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP
6763      0,	// sub_64
6764      0,	// sub_dsp16_19
6765      0,	// sub_dsp20
6766      0,	// sub_dsp21
6767      0,	// sub_dsp22
6768      0,	// sub_dsp23
6769      0,	// sub_hi
6770      0,	// sub_lo
6771      0,	// sub_hi_then_sub_32
6772      0,	// sub_32_sub_hi_then_sub_32
6773    },
6774    {	// GPR64_with_sub_32_in_GPRMM16Zero
6775      51,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero
6776      0,	// sub_64
6777      0,	// sub_dsp16_19
6778      0,	// sub_dsp20
6779      0,	// sub_dsp21
6780      0,	// sub_dsp22
6781      0,	// sub_dsp23
6782      0,	// sub_hi
6783      0,	// sub_lo
6784      0,	// sub_hi_then_sub_32
6785      0,	// sub_32_sub_hi_then_sub_32
6786    },
6787    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
6788      52,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
6789      0,	// sub_64
6790      0,	// sub_dsp16_19
6791      0,	// sub_dsp20
6792      0,	// sub_dsp21
6793      0,	// sub_dsp22
6794      0,	// sub_dsp23
6795      0,	// sub_hi
6796      0,	// sub_lo
6797      0,	// sub_hi_then_sub_32
6798      0,	// sub_32_sub_hi_then_sub_32
6799    },
6800    {	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
6801      53,	// sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
6802      0,	// sub_64
6803      0,	// sub_dsp16_19
6804      0,	// sub_dsp20
6805      0,	// sub_dsp21
6806      0,	// sub_dsp22
6807      0,	// sub_dsp23
6808      0,	// sub_hi
6809      0,	// sub_lo
6810      0,	// sub_hi_then_sub_32
6811      0,	// sub_32_sub_hi_then_sub_32
6812    },
6813    {	// ACC64DSP
6814      0,	// sub_32
6815      0,	// sub_64
6816      0,	// sub_dsp16_19
6817      0,	// sub_dsp20
6818      0,	// sub_dsp21
6819      0,	// sub_dsp22
6820      0,	// sub_dsp23
6821      54,	// sub_hi -> ACC64DSP
6822      54,	// sub_lo -> ACC64DSP
6823      0,	// sub_hi_then_sub_32
6824      0,	// sub_32_sub_hi_then_sub_32
6825    },
6826    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
6827      55,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
6828      0,	// sub_64
6829      0,	// sub_dsp16_19
6830      0,	// sub_dsp20
6831      0,	// sub_dsp21
6832      0,	// sub_dsp22
6833      0,	// sub_dsp23
6834      0,	// sub_hi
6835      0,	// sub_lo
6836      0,	// sub_hi_then_sub_32
6837      0,	// sub_32_sub_hi_then_sub_32
6838    },
6839    {	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
6840      56,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
6841      0,	// sub_64
6842      0,	// sub_dsp16_19
6843      0,	// sub_dsp20
6844      0,	// sub_dsp21
6845      0,	// sub_dsp22
6846      0,	// sub_dsp23
6847      0,	// sub_hi
6848      0,	// sub_lo
6849      0,	// sub_hi_then_sub_32
6850      0,	// sub_32_sub_hi_then_sub_32
6851    },
6852    {	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6853      57,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6854      0,	// sub_64
6855      0,	// sub_dsp16_19
6856      0,	// sub_dsp20
6857      0,	// sub_dsp21
6858      0,	// sub_dsp22
6859      0,	// sub_dsp23
6860      0,	// sub_hi
6861      0,	// sub_lo
6862      0,	// sub_hi_then_sub_32
6863      0,	// sub_32_sub_hi_then_sub_32
6864    },
6865    {	// OCTEON_MPL
6866      0,	// sub_32
6867      0,	// sub_64
6868      0,	// sub_dsp16_19
6869      0,	// sub_dsp20
6870      0,	// sub_dsp21
6871      0,	// sub_dsp22
6872      0,	// sub_dsp23
6873      0,	// sub_hi
6874      0,	// sub_lo
6875      0,	// sub_hi_then_sub_32
6876      0,	// sub_32_sub_hi_then_sub_32
6877    },
6878    {	// OCTEON_P
6879      0,	// sub_32
6880      0,	// sub_64
6881      0,	// sub_dsp16_19
6882      0,	// sub_dsp20
6883      0,	// sub_dsp21
6884      0,	// sub_dsp22
6885      0,	// sub_dsp23
6886      0,	// sub_hi
6887      0,	// sub_lo
6888      0,	// sub_hi_then_sub_32
6889      0,	// sub_32_sub_hi_then_sub_32
6890    },
6891    {	// ACC64
6892      0,	// sub_32
6893      0,	// sub_64
6894      0,	// sub_dsp16_19
6895      0,	// sub_dsp20
6896      0,	// sub_dsp21
6897      0,	// sub_dsp22
6898      0,	// sub_dsp23
6899      60,	// sub_hi -> ACC64
6900      60,	// sub_lo -> ACC64
6901      0,	// sub_hi_then_sub_32
6902      0,	// sub_32_sub_hi_then_sub_32
6903    },
6904    {	// GP64
6905      61,	// sub_32 -> GP64
6906      0,	// sub_64
6907      0,	// sub_dsp16_19
6908      0,	// sub_dsp20
6909      0,	// sub_dsp21
6910      0,	// sub_dsp22
6911      0,	// sub_dsp23
6912      0,	// sub_hi
6913      0,	// sub_lo
6914      0,	// sub_hi_then_sub_32
6915      0,	// sub_32_sub_hi_then_sub_32
6916    },
6917    {	// GPR64_with_sub_32_in_CPURAReg
6918      62,	// sub_32 -> GPR64_with_sub_32_in_CPURAReg
6919      0,	// sub_64
6920      0,	// sub_dsp16_19
6921      0,	// sub_dsp20
6922      0,	// sub_dsp21
6923      0,	// sub_dsp22
6924      0,	// sub_dsp23
6925      0,	// sub_hi
6926      0,	// sub_lo
6927      0,	// sub_hi_then_sub_32
6928      0,	// sub_32_sub_hi_then_sub_32
6929    },
6930    {	// GPR64_with_sub_32_in_GPR32ZERO
6931      63,	// sub_32 -> GPR64_with_sub_32_in_GPR32ZERO
6932      0,	// sub_64
6933      0,	// sub_dsp16_19
6934      0,	// sub_dsp20
6935      0,	// sub_dsp21
6936      0,	// sub_dsp22
6937      0,	// sub_dsp23
6938      0,	// sub_hi
6939      0,	// sub_lo
6940      0,	// sub_hi_then_sub_32
6941      0,	// sub_32_sub_hi_then_sub_32
6942    },
6943    {	// HI64
6944      64,	// sub_32 -> HI64
6945      0,	// sub_64
6946      0,	// sub_dsp16_19
6947      0,	// sub_dsp20
6948      0,	// sub_dsp21
6949      0,	// sub_dsp22
6950      0,	// sub_dsp23
6951      0,	// sub_hi
6952      0,	// sub_lo
6953      0,	// sub_hi_then_sub_32
6954      0,	// sub_32_sub_hi_then_sub_32
6955    },
6956    {	// LO64
6957      65,	// sub_32 -> LO64
6958      0,	// sub_64
6959      0,	// sub_dsp16_19
6960      0,	// sub_dsp20
6961      0,	// sub_dsp21
6962      0,	// sub_dsp22
6963      0,	// sub_dsp23
6964      0,	// sub_hi
6965      0,	// sub_lo
6966      0,	// sub_hi_then_sub_32
6967      0,	// sub_32_sub_hi_then_sub_32
6968    },
6969    {	// SP64
6970      66,	// sub_32 -> SP64
6971      0,	// sub_64
6972      0,	// sub_dsp16_19
6973      0,	// sub_dsp20
6974      0,	// sub_dsp21
6975      0,	// sub_dsp22
6976      0,	// sub_dsp23
6977      0,	// sub_hi
6978      0,	// sub_lo
6979      0,	// sub_hi_then_sub_32
6980      0,	// sub_32_sub_hi_then_sub_32
6981    },
6982    {	// MSA128B
6983      0,	// sub_32
6984      67,	// sub_64 -> MSA128B
6985      0,	// sub_dsp16_19
6986      0,	// sub_dsp20
6987      0,	// sub_dsp21
6988      0,	// sub_dsp22
6989      0,	// sub_dsp23
6990      67,	// sub_hi -> MSA128B
6991      67,	// sub_lo -> MSA128B
6992      0,	// sub_hi_then_sub_32
6993      0,	// sub_32_sub_hi_then_sub_32
6994    },
6995    {	// MSA128D
6996      0,	// sub_32
6997      68,	// sub_64 -> MSA128D
6998      0,	// sub_dsp16_19
6999      0,	// sub_dsp20
7000      0,	// sub_dsp21
7001      0,	// sub_dsp22
7002      0,	// sub_dsp23
7003      68,	// sub_hi -> MSA128D
7004      68,	// sub_lo -> MSA128D
7005      0,	// sub_hi_then_sub_32
7006      0,	// sub_32_sub_hi_then_sub_32
7007    },
7008    {	// MSA128H
7009      0,	// sub_32
7010      69,	// sub_64 -> MSA128H
7011      0,	// sub_dsp16_19
7012      0,	// sub_dsp20
7013      0,	// sub_dsp21
7014      0,	// sub_dsp22
7015      0,	// sub_dsp23
7016      69,	// sub_hi -> MSA128H
7017      69,	// sub_lo -> MSA128H
7018      0,	// sub_hi_then_sub_32
7019      0,	// sub_32_sub_hi_then_sub_32
7020    },
7021    {	// MSA128W
7022      0,	// sub_32
7023      70,	// sub_64 -> MSA128W
7024      0,	// sub_dsp16_19
7025      0,	// sub_dsp20
7026      0,	// sub_dsp21
7027      0,	// sub_dsp22
7028      0,	// sub_dsp23
7029      70,	// sub_hi -> MSA128W
7030      70,	// sub_lo -> MSA128W
7031      0,	// sub_hi_then_sub_32
7032      0,	// sub_32_sub_hi_then_sub_32
7033    },
7034    {	// MSA128B_with_sub_64_in_OddSP
7035      0,	// sub_32
7036      71,	// sub_64 -> MSA128B_with_sub_64_in_OddSP
7037      0,	// sub_dsp16_19
7038      0,	// sub_dsp20
7039      0,	// sub_dsp21
7040      0,	// sub_dsp22
7041      0,	// sub_dsp23
7042      71,	// sub_hi -> MSA128B_with_sub_64_in_OddSP
7043      71,	// sub_lo -> MSA128B_with_sub_64_in_OddSP
7044      0,	// sub_hi_then_sub_32
7045      0,	// sub_32_sub_hi_then_sub_32
7046    },
7047    {	// MSA128WEvens
7048      0,	// sub_32
7049      72,	// sub_64 -> MSA128WEvens
7050      0,	// sub_dsp16_19
7051      0,	// sub_dsp20
7052      0,	// sub_dsp21
7053      0,	// sub_dsp22
7054      0,	// sub_dsp23
7055      72,	// sub_hi -> MSA128WEvens
7056      72,	// sub_lo -> MSA128WEvens
7057      0,	// sub_hi_then_sub_32
7058      0,	// sub_32_sub_hi_then_sub_32
7059    },
7060    {	// ACC128
7061      73,	// sub_32 -> ACC128
7062      0,	// sub_64
7063      0,	// sub_dsp16_19
7064      0,	// sub_dsp20
7065      0,	// sub_dsp21
7066      0,	// sub_dsp22
7067      0,	// sub_dsp23
7068      73,	// sub_hi -> ACC128
7069      73,	// sub_lo -> ACC128
7070      73,	// sub_hi_then_sub_32 -> ACC128
7071      73,	// sub_32_sub_hi_then_sub_32 -> ACC128
7072    },
7073  };
7074  assert(RC && "Missing regclass");
7075  if (!Idx) return RC;
7076  --Idx;
7077  assert(Idx < 11 && "Bad subreg");
7078  unsigned TV = Table[RC->getID()][Idx];
7079  return TV ? getRegClass(TV - 1) : nullptr;
7080}
7081
7082/// Get the weight in units of pressure for this register class.
7083const RegClassWeight &MipsGenRegisterInfo::
7084getRegClassWeight(const TargetRegisterClass *RC) const {
7085  static const RegClassWeight RCWeightTable[] = {
7086    {2, 64},  	// MSA128F16
7087    {2, 32},  	// MSA128F16_with_sub_64_in_OddSP
7088    {2, 40},  	// OddSP
7089    {0, 0},  	// CCR
7090    {0, 0},  	// COP0
7091    {0, 0},  	// COP2
7092    {0, 0},  	// COP3
7093    {1, 32},  	// DSPR
7094    {1, 32},  	// FGR32
7095    {1, 32},  	// FGRCC
7096    {1, 32},  	// FGRH32
7097    {1, 32},  	// GPR32
7098    {0, 0},  	// HWRegs
7099    {1, 31},  	// GPR32NONZERO
7100    {2, 40},  	// OddSP_with_sub_hi
7101    {1, 16},  	// FGR32_and_OddSP
7102    {1, 16},  	// FGRH32_and_OddSP
7103    {2, 32},  	// OddSP_with_sub_hi_with_sub_hi_in_FGRH32
7104    {1, 9},  	// CPU16RegsPlusSP
7105    {1, 8},  	// CPU16Regs
7106    {0, 0},  	// FCC
7107    {1, 8},  	// GPRMM16
7108    {1, 8},  	// GPRMM16MoveP
7109    {1, 8},  	// GPRMM16Zero
7110    {1, 8},  	// MSACtrl
7111    {2, 16},  	// OddSP_with_sub_hi_with_sub_hi_in_FGR32
7112    {1, 7},  	// CPU16Regs_and_GPRMM16Zero
7113    {1, 7},  	// GPR32NONZERO_and_GPRMM16MoveP
7114    {1, 4},  	// CPU16Regs_and_GPRMM16MoveP
7115    {1, 4},  	// GPRMM16MoveP_and_GPRMM16Zero
7116    {1, 4},  	// HI32DSP
7117    {1, 4},  	// LO32DSP
7118    {1, 3},  	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7119    {1, 1},  	// CPURAReg
7120    {1, 1},  	// CPUSPReg
7121    {1, 1},  	// DSPCC
7122    {1, 1},  	// GP32
7123    {1, 1},  	// GPR32ZERO
7124    {1, 1},  	// HI32
7125    {1, 1},  	// LO32
7126    {1, 1},  	// SP32
7127    {2, 64},  	// FGR64
7128    {1, 32},  	// GPR64
7129    {1, 31},  	// GPR64_with_sub_32_in_GPR32NONZERO
7130    {2, 32},  	// AFGR64
7131    {2, 32},  	// FGR64_and_OddSP
7132    {1, 9},  	// GPR64_with_sub_32_in_CPU16RegsPlusSP
7133    {2, 16},  	// AFGR64_and_OddSP
7134    {1, 8},  	// GPR64_with_sub_32_in_CPU16Regs
7135    {1, 8},  	// GPR64_with_sub_32_in_GPRMM16MoveP
7136    {1, 8},  	// GPR64_with_sub_32_in_GPRMM16Zero
7137    {1, 7},  	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
7138    {1, 7},  	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
7139    {2, 8},  	// ACC64DSP
7140    {1, 4},  	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
7141    {1, 4},  	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
7142    {1, 3},  	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7143    {0, 0},  	// OCTEON_MPL
7144    {0, 0},  	// OCTEON_P
7145    {2, 2},  	// ACC64
7146    {1, 1},  	// GP64
7147    {1, 1},  	// GPR64_with_sub_32_in_CPURAReg
7148    {1, 1},  	// GPR64_with_sub_32_in_GPR32ZERO
7149    {1, 1},  	// HI64
7150    {1, 1},  	// LO64
7151    {1, 1},  	// SP64
7152    {2, 64},  	// MSA128B
7153    {2, 64},  	// MSA128D
7154    {2, 64},  	// MSA128H
7155    {2, 64},  	// MSA128W
7156    {2, 32},  	// MSA128B_with_sub_64_in_OddSP
7157    {2, 32},  	// MSA128WEvens
7158    {2, 2},  	// ACC128
7159  };
7160  return RCWeightTable[RC->getID()];
7161}
7162
7163/// Get the weight in units of pressure for this register unit.
7164unsigned MipsGenRegisterInfo::
7165getRegUnitWeight(unsigned RegUnit) const {
7166  assert(RegUnit < 297 && "invalid register unit");
7167  // All register units have unit weight.
7168  return 1;
7169}
7170
7171
7172// Get the number of dimensions of register pressure.
7173unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {
7174  return 24;
7175}
7176
7177// Get the name of this register unit pressure set.
7178const char *MipsGenRegisterInfo::
7179getRegPressureSetName(unsigned Idx) const {
7180  static const char *const PressureNameTable[] = {
7181    "DSPCC",
7182    "GPR32ZERO",
7183    "GPR64_with_sub_32_in_CPURAReg",
7184    "HI32",
7185    "CPU16Regs_and_GPRMM16MoveP",
7186    "HI32DSP",
7187    "LO32DSP",
7188    "GPRMM16MoveP",
7189    "MSACtrl",
7190    "ACC64DSP",
7191    "CPU16Regs",
7192    "CPU16Regs+GPRMM16MoveP",
7193    "FGR32_and_OddSP",
7194    "AFGR64_and_OddSP",
7195    "FGR32_and_OddSP+AFGR64_and_OddSP",
7196    "MSA128F16_with_sub_64_in_OddSP",
7197    "DSPR",
7198    "FGR32",
7199    "MSA128WEvens",
7200    "MSA128F16_with_sub_64_in_OddSP+AFGR64_and_OddSP",
7201    "AFGR64_and_OddSP+MSA128WEvens",
7202    "MSA128F16_with_sub_64_in_OddSP+FGR32",
7203    "FGR32+MSA128WEvens",
7204    "MSA128F16",
7205  };
7206  return PressureNameTable[Idx];
7207}
7208
7209// Get the register unit pressure limit for this dimension.
7210// This limit must be adjusted dynamically for reserved registers.
7211unsigned MipsGenRegisterInfo::
7212getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
7213  static const uint8_t PressureLimitTable[] = {
7214    1,  	// 0: DSPCC
7215    1,  	// 1: GPR32ZERO
7216    1,  	// 2: GPR64_with_sub_32_in_CPURAReg
7217    2,  	// 3: HI32
7218    5,  	// 4: CPU16Regs_and_GPRMM16MoveP
7219    5,  	// 5: HI32DSP
7220    5,  	// 6: LO32DSP
7221    8,  	// 7: GPRMM16MoveP
7222    8,  	// 8: MSACtrl
7223    8,  	// 9: ACC64DSP
7224    10,  	// 10: CPU16Regs
7225    13,  	// 11: CPU16Regs+GPRMM16MoveP
7226    16,  	// 12: FGR32_and_OddSP
7227    16,  	// 13: AFGR64_and_OddSP
7228    24,  	// 14: FGR32_and_OddSP+AFGR64_and_OddSP
7229    32,  	// 15: MSA128F16_with_sub_64_in_OddSP
7230    32,  	// 16: DSPR
7231    32,  	// 17: FGR32
7232    32,  	// 18: MSA128WEvens
7233    40,  	// 19: MSA128F16_with_sub_64_in_OddSP+AFGR64_and_OddSP
7234    40,  	// 20: AFGR64_and_OddSP+MSA128WEvens
7235    48,  	// 21: MSA128F16_with_sub_64_in_OddSP+FGR32
7236    48,  	// 22: FGR32+MSA128WEvens
7237    64,  	// 23: MSA128F16
7238  };
7239  return PressureLimitTable[Idx];
7240}
7241
7242/// Table of pressure sets per register class or unit.
7243static const int RCSetsTable[] = {
7244  /* 0 */ 0, -1,
7245  /* 2 */ 8, -1,
7246  /* 4 */ 5, 9, -1,
7247  /* 7 */ 3, 5, 6, 9, -1,
7248  /* 12 */ 2, 16, -1,
7249  /* 15 */ 7, 11, 16, -1,
7250  /* 19 */ 1, 4, 7, 10, 11, 16, -1,
7251  /* 26 */ 15, 19, 21, 23, -1,
7252  /* 31 */ 18, 20, 22, 23, -1,
7253  /* 36 */ 17, 21, 22, 23, -1,
7254  /* 41 */ 12, 14, 15, 17, 19, 21, 22, 23, -1,
7255  /* 50 */ 17, 18, 20, 21, 22, 23, -1,
7256  /* 57 */ 13, 14, 17, 19, 20, 21, 22, 23, -1,
7257  /* 66 */ 12, 13, 14, 15, 17, 19, 20, 21, 22, 23, -1,
7258  /* 77 */ 13, 14, 17, 18, 19, 20, 21, 22, 23, -1,
7259};
7260
7261/// Get the dimensions of register pressure impacted by this register class.
7262/// Returns a -1 terminated array of pressure set IDs
7263const int* MipsGenRegisterInfo::
7264getRegClassPressureSets(const TargetRegisterClass *RC) const {
7265  static const uint8_t RCSetStartTable[] = {
7266    29,26,1,1,1,1,1,13,36,36,1,13,1,13,1,41,1,1,22,22,1,22,15,22,2,1,22,15,20,20,4,9,20,1,1,0,1,19,7,7,1,29,13,13,36,26,22,57,22,15,22,22,15,5,20,20,20,1,1,7,1,12,19,7,7,1,29,29,29,29,26,31,7,};
7267  return &RCSetsTable[RCSetStartTable[RC->getID()]];
7268}
7269
7270/// Get the dimensions of register pressure impacted by this register unit.
7271/// Returns a -1 terminated array of pressure set IDs
7272const int* MipsGenRegisterInfo::
7273getRegUnitPressureSets(unsigned RegUnit) const {
7274  assert(RegUnit < 297 && "invalid register unit");
7275  static const uint8_t RUSetStartTable[] = {
7276    13,0,1,1,1,1,1,1,1,1,1,13,13,2,2,2,2,2,2,2,2,1,12,22,19,22,22,22,22,7,7,9,4,9,4,9,4,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,13,13,1,1,1,1,1,1,20,20,15,15,15,13,13,13,13,13,13,13,13,13,13,13,13,13,20,20,};
7277  return &RCSetsTable[RUSetStartTable[RegUnit]];
7278}
7279
7280extern const MCRegisterDesc MipsRegDesc[];
7281extern const MCPhysReg MipsRegDiffLists[];
7282extern const LaneBitmask MipsLaneMaskLists[];
7283extern const char MipsRegStrings[];
7284extern const char MipsRegClassStrings[];
7285extern const MCPhysReg MipsRegUnitRoots[][2];
7286extern const uint16_t MipsSubRegIdxLists[];
7287extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[];
7288extern const uint16_t MipsRegEncodingTable[];
7289// Mips Dwarf<->LLVM register mappings.
7290extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
7291extern const unsigned MipsDwarfFlavour0Dwarf2LSize;
7292
7293extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
7294extern const unsigned MipsEHFlavour0Dwarf2LSize;
7295
7296extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
7297extern const unsigned MipsDwarfFlavour0L2DwarfSize;
7298
7299extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
7300extern const unsigned MipsEHFlavour0L2DwarfSize;
7301
7302MipsGenRegisterInfo::
7303MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
7304      unsigned PC, unsigned HwMode)
7305  : TargetRegisterInfo(MipsRegInfoDesc, RegisterClasses, RegisterClasses+73,
7306             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
7307             LaneBitmask(0xFFFFFF80), RegClassInfos, HwMode) {
7308  InitMCRegisterInfo(MipsRegDesc, 418, RA, PC,
7309                     MipsMCRegisterClasses, 73,
7310                     MipsRegUnitRoots,
7311                     297,
7312                     MipsRegDiffLists,
7313                     MipsLaneMaskLists,
7314                     MipsRegStrings,
7315                     MipsRegClassStrings,
7316                     MipsSubRegIdxLists,
7317                     12,
7318                     MipsSubRegIdxRanges,
7319                     MipsRegEncodingTable);
7320
7321  switch (DwarfFlavour) {
7322  default:
7323    llvm_unreachable("Unknown DWARF flavour");
7324  case 0:
7325    mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
7326    break;
7327  }
7328  switch (EHFlavour) {
7329  default:
7330    llvm_unreachable("Unknown DWARF flavour");
7331  case 0:
7332    mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
7333    break;
7334  }
7335  switch (DwarfFlavour) {
7336  default:
7337    llvm_unreachable("Unknown DWARF flavour");
7338  case 0:
7339    mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
7340    break;
7341  }
7342  switch (EHFlavour) {
7343  default:
7344    llvm_unreachable("Unknown DWARF flavour");
7345  case 0:
7346    mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
7347    break;
7348  }
7349}
7350
7351static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };
7352static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0xffbfc008, 0x00000007, 0x00000000, 0x00000000, 0x00000000, };
7353static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };
7354static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffbfc000, 0x00000007, 0x00000000, 0x00000000, 0x00000000, };
7355static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };
7356static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0xffbfe008, 0x00000007, 0x000001f0, 0xffffe400, 0x00000003, };
7357static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };
7358static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0xffbfe000, 0x00000007, 0x000000f0, 0xffffc000, 0x00000003, };
7359static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };
7360static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03c00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x003fc000, 0x00000006, 0x00000000, 0x00000000, 0x00000000, };
7361static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
7362static const uint32_t CSR_N32_RegMask[] = { 0x00080300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x003fe000, 0x00000000, 0xa0000000, 0x003fc0aa, 0x00000000, };
7363static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
7364static const uint32_t CSR_N64_RegMask[] = { 0x00080300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x003fe000, 0x00000000, 0x00000000, 0x003fc1fe, 0x00000000, };
7365static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
7366static const uint32_t CSR_O32_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x003fc000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
7367static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
7368static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x003fc000, 0x00000000, 0xa0000000, 0x000000aa, 0x00000000, };
7369static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
7370static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x003fc000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
7371static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
7372static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x003fc000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
7373
7374
7375ArrayRef<const uint32_t *> MipsGenRegisterInfo::getRegMasks() const {
7376  static const uint32_t *const Masks[] = {
7377    CSR_Interrupt_32_RegMask,
7378    CSR_Interrupt_32R6_RegMask,
7379    CSR_Interrupt_64_RegMask,
7380    CSR_Interrupt_64R6_RegMask,
7381    CSR_Mips16RetHelper_RegMask,
7382    CSR_N32_RegMask,
7383    CSR_N64_RegMask,
7384    CSR_O32_RegMask,
7385    CSR_O32_FP64_RegMask,
7386    CSR_O32_FPXX_RegMask,
7387    CSR_SingleFloatOnly_RegMask,
7388  };
7389  return makeArrayRef(Masks);
7390}
7391
7392ArrayRef<const char *> MipsGenRegisterInfo::getRegMaskNames() const {
7393  static const char *const Names[] = {
7394    "CSR_Interrupt_32",
7395    "CSR_Interrupt_32R6",
7396    "CSR_Interrupt_64",
7397    "CSR_Interrupt_64R6",
7398    "CSR_Mips16RetHelper",
7399    "CSR_N32",
7400    "CSR_N64",
7401    "CSR_O32",
7402    "CSR_O32_FP64",
7403    "CSR_O32_FPXX",
7404    "CSR_SingleFloatOnly",
7405  };
7406  return makeArrayRef(Names);
7407}
7408
7409const MipsFrameLowering *
7410MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
7411  return static_cast<const MipsFrameLowering *>(
7412      MF.getSubtarget().getFrameLowering());
7413}
7414
7415} // end namespace llvm
7416
7417#endif // GET_REGINFO_TARGET_DESC
7418
7419