1def SDTVecLeaf: 2 SDTypeProfile<1, 0, [SDTCisVec<0>]>; 3def SDTVecBinOp: 4 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>]>; 5 6def SDTHexagonVEXTRACTW: SDTypeProfile<1, 2, 7 [SDTCisVT<0, i32>, SDTCisVec<1>, SDTCisVT<2, i32>]>; 8def HexagonVEXTRACTW : SDNode<"HexagonISD::VEXTRACTW", SDTHexagonVEXTRACTW>; 9 10def SDTHexagonVINSERTW0: SDTypeProfile<1, 2, 11 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>; 12def HexagonVINSERTW0: SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>; 13 14def SDTHexagonVSPLATW: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; 15def HexagonVSPLATW: SDNode<"HexagonISD::VSPLATW", SDTHexagonVSPLATW>; 16 17def HwLen2: SDNodeXForm<imm, [{ 18 const auto &ST = static_cast<const HexagonSubtarget&>(CurDAG->getSubtarget()); 19 return CurDAG->getTargetConstant(ST.getVectorLength()/2, SDLoc(N), MVT::i32); 20}]>; 21 22def Q2V: OutPatFrag<(ops node:$Qs), (V6_vandqrt $Qs, (A2_tfrsi -1))>; 23 24def Combinev: OutPatFrag<(ops node:$Vs, node:$Vt), 25 (REG_SEQUENCE HvxWR, $Vs, vsub_hi, $Vt, vsub_lo)>; 26 27def Combineq: OutPatFrag<(ops node:$Qs, node:$Qt), 28 (V6_vandvrt 29 (V6_vor 30 (V6_vror (V6_vpackeb (V6_vd0), (Q2V $Qs)), 31 (A2_tfrsi (HwLen2 (i32 0)))), // Half the vector length 32 (V6_vpackeb (V6_vd0), (Q2V $Qt))), 33 (A2_tfrsi -1))>; 34 35def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>; 36def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>; 37 38def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>; 39def HexagonQCAT: SDNode<"HexagonISD::QCAT", SDTVecBinOp>; 40def HexagonQTRUE: SDNode<"HexagonISD::QTRUE", SDTVecLeaf>; 41def HexagonQFALSE: SDNode<"HexagonISD::QFALSE", SDTVecLeaf>; 42 43def vzero: PatFrag<(ops), (HexagonVZERO)>; 44def qtrue: PatFrag<(ops), (HexagonQTRUE)>; 45def qfalse: PatFrag<(ops), (HexagonQFALSE)>; 46def qcat: PatFrag<(ops node:$Qs, node:$Qt), 47 (HexagonQCAT node:$Qs, node:$Qt)>; 48 49def qnot: PatFrag<(ops node:$Qs), (xor node:$Qs, qtrue)>; 50 51def VSxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackb $Vs)>; 52def VSxth: OutPatFrag<(ops node:$Vs), (V6_vunpackh $Vs)>; 53def VZxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackub $Vs)>; 54def VZxth: OutPatFrag<(ops node:$Vs), (V6_vunpackuh $Vs)>; 55 56def SplatB: SDNodeXForm<imm, [{ 57 uint32_t V = N->getZExtValue(); 58 assert(isUInt<8>(V)); 59 uint32_t S = V << 24 | V << 16 | V << 8 | V; 60 return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32); 61}]>; 62 63def SplatH: SDNodeXForm<imm, [{ 64 uint32_t V = N->getZExtValue(); 65 assert(isUInt<16>(V)); 66 return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32); 67}]>; 68 69def IsVecOff : PatLeaf<(i32 imm), [{ 70 int32_t V = N->getSExtValue(); 71 int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass); 72 assert(isPowerOf2_32(VecSize)); 73 if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0) 74 return false; 75 int32_t L = Log2_32(VecSize); 76 return isInt<4>(V >> L); 77}]>; 78 79 80def alignedload: PatFrag<(ops node:$a), (load $a), [{ 81 return isAlignedMemNode(dyn_cast<MemSDNode>(N)); 82}]>; 83 84def unalignedload: PatFrag<(ops node:$a), (load $a), [{ 85 return !isAlignedMemNode(dyn_cast<MemSDNode>(N)); 86}]>; 87 88def alignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{ 89 return isAlignedMemNode(dyn_cast<MemSDNode>(N)); 90}]>; 91 92def unalignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{ 93 return !isAlignedMemNode(dyn_cast<MemSDNode>(N)); 94}]>; 95 96 97// HVX loads 98 99multiclass HvxLd_pat<InstHexagon MI, PatFrag Load, ValueType ResType, 100 PatFrag ImmPred> { 101 def: Pat<(ResType (Load I32:$Rt)), 102 (MI I32:$Rt, 0)>; 103 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))), 104 (MI I32:$Rt, imm:$s)>; 105 // The HVX selection code for shuffles can generate vector constants. 106 // Calling "Select" on the resulting loads from CP fails without these 107 // patterns. 108 def: Pat<(ResType (Load (HexagonCP tconstpool:$A))), 109 (MI (A2_tfrsi imm:$A), 0)>; 110 def: Pat<(ResType (Load (HexagonAtPcrel tconstpool:$A))), 111 (MI (C4_addipc imm:$A), 0)>; 112} 113 114multiclass HvxLda_pat<InstHexagon MI, PatFrag Load, ValueType ResType, 115 PatFrag ImmPred> { 116 let AddedComplexity = 50 in { 117 def: Pat<(ResType (Load (valignaddr I32:$Rt))), 118 (MI I32:$Rt, 0)>; 119 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))), 120 (MI I32:$Rt, imm:$Off)>; 121 } 122 defm: HvxLd_pat<MI, Load, ResType, ImmPred>; 123} 124 125let Predicates = [UseHVX] in { 126 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI8, IsVecOff>; 127 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI16, IsVecOff>; 128 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI32, IsVecOff>; 129 130 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI8, IsVecOff>; 131 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI16, IsVecOff>; 132 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI32, IsVecOff>; 133 134 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI8, IsVecOff>; 135 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI16, IsVecOff>; 136 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI32, IsVecOff>; 137} 138 139// HVX stores 140 141multiclass HvxSt_pat<InstHexagon MI, PatFrag Store, PatFrag ImmPred, 142 PatFrag Value> { 143 def: Pat<(Store Value:$Vs, I32:$Rt), 144 (MI I32:$Rt, 0, Value:$Vs)>; 145 def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$s)), 146 (MI I32:$Rt, imm:$s, Value:$Vs)>; 147} 148 149let Predicates = [UseHVX] in { 150 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI8>; 151 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI16>; 152 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI32>; 153 154 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI8>; 155 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI16>; 156 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI32>; 157 158 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI8>; 159 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI16>; 160 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI32>; 161} 162 163// Bitcasts between same-size vector types are no-ops, except for the 164// actual type change. 165class Bitcast<ValueType ResTy, ValueType InpTy, RegisterClass RC> 166 : Pat<(ResTy (bitconvert (InpTy RC:$Val))), (ResTy RC:$Val)>; 167 168let Predicates = [UseHVX] in { 169 def: Bitcast<VecI8, VecI16, HvxVR>; 170 def: Bitcast<VecI8, VecI32, HvxVR>; 171 def: Bitcast<VecI16, VecI8, HvxVR>; 172 def: Bitcast<VecI16, VecI32, HvxVR>; 173 def: Bitcast<VecI32, VecI8, HvxVR>; 174 def: Bitcast<VecI32, VecI16, HvxVR>; 175 176 def: Bitcast<VecPI8, VecPI16, HvxWR>; 177 def: Bitcast<VecPI8, VecPI32, HvxWR>; 178 def: Bitcast<VecPI16, VecPI8, HvxWR>; 179 def: Bitcast<VecPI16, VecPI32, HvxWR>; 180 def: Bitcast<VecPI32, VecPI8, HvxWR>; 181 def: Bitcast<VecPI32, VecPI16, HvxWR>; 182} 183 184let Predicates = [UseHVX] in { 185 def: Pat<(VecI8 vzero), (V6_vd0)>; 186 def: Pat<(VecI16 vzero), (V6_vd0)>; 187 def: Pat<(VecI32 vzero), (V6_vd0)>; 188 def: Pat<(VecPI8 vzero), (PS_vdd0)>; 189 def: Pat<(VecPI16 vzero), (PS_vdd0)>; 190 def: Pat<(VecPI32 vzero), (PS_vdd0)>; 191 192 def: Pat<(concat_vectors (VecI8 vzero), (VecI8 vzero)), (PS_vdd0)>; 193 def: Pat<(concat_vectors (VecI16 vzero), (VecI16 vzero)), (PS_vdd0)>; 194 def: Pat<(concat_vectors (VecI32 vzero), (VecI32 vzero)), (PS_vdd0)>; 195 196 def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)), 197 (Combinev HvxVR:$Vt, HvxVR:$Vs)>; 198 def: Pat<(VecPI16 (concat_vectors HVI16:$Vs, HVI16:$Vt)), 199 (Combinev HvxVR:$Vt, HvxVR:$Vs)>; 200 def: Pat<(VecPI32 (concat_vectors HVI32:$Vs, HVI32:$Vt)), 201 (Combinev HvxVR:$Vt, HvxVR:$Vs)>; 202 203 def: Pat<(VecQ8 (qcat HQ16:$Qs, HQ16:$Qt)), (Combineq $Qt, $Qs)>; 204 def: Pat<(VecQ16 (qcat HQ32:$Qs, HQ32:$Qt)), (Combineq $Qt, $Qs)>; 205 206 def: Pat<(HexagonVEXTRACTW HVI8:$Vu, I32:$Rs), 207 (V6_extractw HvxVR:$Vu, I32:$Rs)>; 208 def: Pat<(HexagonVEXTRACTW HVI16:$Vu, I32:$Rs), 209 (V6_extractw HvxVR:$Vu, I32:$Rs)>; 210 def: Pat<(HexagonVEXTRACTW HVI32:$Vu, I32:$Rs), 211 (V6_extractw HvxVR:$Vu, I32:$Rs)>; 212 213 def: Pat<(HexagonVINSERTW0 HVI8:$Vu, I32:$Rt), 214 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>; 215 def: Pat<(HexagonVINSERTW0 HVI16:$Vu, I32:$Rt), 216 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>; 217 def: Pat<(HexagonVINSERTW0 HVI32:$Vu, I32:$Rt), 218 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>; 219} 220 221def Vsplatib: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 (SplatB $V)))>; 222def Vsplatih: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 (SplatH $V)))>; 223def Vsplatiw: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 $V))>; 224 225def Vsplatrb: OutPatFrag<(ops node:$Rs), (V6_lvsplatw (S2_vsplatrb $Rs))>; 226def Vsplatrh: OutPatFrag<(ops node:$Rs), 227 (V6_lvsplatw (A2_combine_ll $Rs, $Rs))>; 228def Vsplatrw: OutPatFrag<(ops node:$Rs), (V6_lvsplatw $Rs)>; 229 230def Rep: OutPatFrag<(ops node:$N), (Combinev $N, $N)>; 231 232let Predicates = [UseHVX] in { 233 let AddedComplexity = 10 in { 234 def: Pat<(VecI8 (HexagonVSPLAT u8_0ImmPred:$V)), (Vsplatib $V)>; 235 def: Pat<(VecI16 (HexagonVSPLAT u16_0ImmPred:$V)), (Vsplatih $V)>; 236 def: Pat<(VecI32 (HexagonVSPLAT anyimm:$V)), (Vsplatiw $V)>; 237 def: Pat<(VecPI8 (HexagonVSPLAT u8_0ImmPred:$V)), (Rep (Vsplatib $V))>; 238 def: Pat<(VecPI16 (HexagonVSPLAT u16_0ImmPred:$V)), (Rep (Vsplatih $V))>; 239 def: Pat<(VecPI32 (HexagonVSPLAT anyimm:$V)), (Rep (Vsplatiw $V))>; 240 } 241 def: Pat<(VecI8 (HexagonVSPLAT I32:$Rs)), (Vsplatrb $Rs)>; 242 def: Pat<(VecI16 (HexagonVSPLAT I32:$Rs)), (Vsplatrh $Rs)>; 243 def: Pat<(VecI32 (HexagonVSPLAT I32:$Rs)), (Vsplatrw $Rs)>; 244 def: Pat<(VecPI8 (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrb $Rs))>; 245 def: Pat<(VecPI16 (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrh $Rs))>; 246 def: Pat<(VecPI32 (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrw $Rs))>; 247 248 def: Pat<(VecI8 (HexagonVSPLATW I32:$Rs)), (Vsplatrw $Rs)>; 249 def: Pat<(VecI16 (HexagonVSPLATW I32:$Rs)), (Vsplatrw $Rs)>; 250 def: Pat<(VecI32 (HexagonVSPLATW I32:$Rs)), (Vsplatrw $Rs)>; 251 def: Pat<(VecPI8 (HexagonVSPLATW I32:$Rs)), (Rep (Vsplatrw $Rs))>; 252 def: Pat<(VecPI16 (HexagonVSPLATW I32:$Rs)), (Rep (Vsplatrw $Rs))>; 253 def: Pat<(VecPI32 (HexagonVSPLATW I32:$Rs)), (Rep (Vsplatrw $Rs))>; 254} 255 256class Vneg1<ValueType VecTy> 257 : PatFrag<(ops), (VecTy (HexagonVSPLATW (i32 -1)))>; 258 259class Vnot<ValueType VecTy> 260 : PatFrag<(ops node:$Vs), (xor $Vs, Vneg1<VecTy>)>; 261 262let Predicates = [UseHVX] in { 263 let AddedComplexity = 200 in { 264 def: Pat<(Vnot<VecI8> HVI8:$Vs), (V6_vnot HvxVR:$Vs)>; 265 def: Pat<(Vnot<VecI16> HVI16:$Vs), (V6_vnot HvxVR:$Vs)>; 266 def: Pat<(Vnot<VecI32> HVI32:$Vs), (V6_vnot HvxVR:$Vs)>; 267 } 268 269 def: OpR_RR_pat<V6_vaddb, Add, VecI8, HVI8>; 270 def: OpR_RR_pat<V6_vaddh, Add, VecI16, HVI16>; 271 def: OpR_RR_pat<V6_vaddw, Add, VecI32, HVI32>; 272 def: OpR_RR_pat<V6_vaddb_dv, Add, VecPI8, HWI8>; 273 def: OpR_RR_pat<V6_vaddh_dv, Add, VecPI16, HWI16>; 274 def: OpR_RR_pat<V6_vaddw_dv, Add, VecPI32, HWI32>; 275 def: OpR_RR_pat<V6_vsubb, Sub, VecI8, HVI8>; 276 def: OpR_RR_pat<V6_vsubh, Sub, VecI16, HVI16>; 277 def: OpR_RR_pat<V6_vsubw, Sub, VecI32, HVI32>; 278 def: OpR_RR_pat<V6_vsubb_dv, Sub, VecPI8, HWI8>; 279 def: OpR_RR_pat<V6_vsubh_dv, Sub, VecPI16, HWI16>; 280 def: OpR_RR_pat<V6_vsubw_dv, Sub, VecPI32, HWI32>; 281 def: OpR_RR_pat<V6_vand, And, VecI8, HVI8>; 282 def: OpR_RR_pat<V6_vand, And, VecI16, HVI16>; 283 def: OpR_RR_pat<V6_vand, And, VecI32, HVI32>; 284 def: OpR_RR_pat<V6_vor, Or, VecI8, HVI8>; 285 def: OpR_RR_pat<V6_vor, Or, VecI16, HVI16>; 286 def: OpR_RR_pat<V6_vor, Or, VecI32, HVI32>; 287 def: OpR_RR_pat<V6_vxor, Xor, VecI8, HVI8>; 288 def: OpR_RR_pat<V6_vxor, Xor, VecI16, HVI16>; 289 def: OpR_RR_pat<V6_vxor, Xor, VecI32, HVI32>; 290 291 def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt), 292 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>; 293 def: Pat<(vselect HQ16:$Qu, HVI16:$Vs, HVI16:$Vt), 294 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>; 295 def: Pat<(vselect HQ32:$Qu, HVI32:$Vs, HVI32:$Vt), 296 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>; 297 298 def: Pat<(vselect (qnot HQ8:$Qu), HVI8:$Vs, HVI8:$Vt), 299 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>; 300 def: Pat<(vselect (qnot HQ16:$Qu), HVI16:$Vs, HVI16:$Vt), 301 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>; 302 def: Pat<(vselect (qnot HQ32:$Qu), HVI32:$Vs, HVI32:$Vt), 303 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>; 304} 305 306let Predicates = [UseHVX] in { 307 def: Pat<(VecPI16 (sext HVI8:$Vs)), (VSxtb $Vs)>; 308 def: Pat<(VecPI32 (sext HVI16:$Vs)), (VSxth $Vs)>; 309 def: Pat<(VecPI16 (zext HVI8:$Vs)), (VZxtb $Vs)>; 310 def: Pat<(VecPI32 (zext HVI16:$Vs)), (VZxth $Vs)>; 311 312 def: Pat<(VecI16 (sext_invec HVI8:$Vs)), (LoVec (VSxtb $Vs))>; 313 def: Pat<(VecI32 (sext_invec HVI16:$Vs)), (LoVec (VSxth $Vs))>; 314 def: Pat<(VecI32 (sext_invec HVI8:$Vs)), 315 (LoVec (VSxth (LoVec (VSxtb $Vs))))>; 316 def: Pat<(VecPI16 (sext_invec HWI8:$Vss)), (VSxtb (LoVec $Vss))>; 317 def: Pat<(VecPI32 (sext_invec HWI16:$Vss)), (VSxth (LoVec $Vss))>; 318 def: Pat<(VecPI32 (sext_invec HWI8:$Vss)), 319 (VSxth (LoVec (VSxtb (LoVec $Vss))))>; 320 321 def: Pat<(VecI16 (zext_invec HVI8:$Vs)), (LoVec (VZxtb $Vs))>; 322 def: Pat<(VecI32 (zext_invec HVI16:$Vs)), (LoVec (VZxth $Vs))>; 323 def: Pat<(VecI32 (zext_invec HVI8:$Vs)), 324 (LoVec (VZxth (LoVec (VZxtb $Vs))))>; 325 def: Pat<(VecPI16 (zext_invec HWI8:$Vss)), (VZxtb (LoVec $Vss))>; 326 def: Pat<(VecPI32 (zext_invec HWI16:$Vss)), (VZxth (LoVec $Vss))>; 327 def: Pat<(VecPI32 (zext_invec HWI8:$Vss)), 328 (VZxth (LoVec (VZxtb (LoVec $Vss))))>; 329 330 def: Pat<(VecI8 (trunc HWI16:$Vss)), 331 (V6_vpackeb (HiVec $Vss), (LoVec $Vss))>; 332 def: Pat<(VecI16 (trunc HWI32:$Vss)), 333 (V6_vpackeh (HiVec $Vss), (LoVec $Vss))>; 334 335 def: Pat<(VecQ8 (trunc HVI8:$Vs)), 336 (V6_vandvrt HvxVR:$Vs, (A2_tfrsi 0x01010101))>; 337 def: Pat<(VecQ16 (trunc HVI16:$Vs)), 338 (V6_vandvrt HvxVR:$Vs, (A2_tfrsi 0x01010101))>; 339 def: Pat<(VecQ32 (trunc HVI32:$Vs)), 340 (V6_vandvrt HvxVR:$Vs, (A2_tfrsi 0x01010101))>; 341} 342 343let Predicates = [UseHVX] in { 344 // The "source" types are not legal, and there are no parameterized 345 // definitions for them, but they are length-specific. 346 let Predicates = [UseHVX,UseHVX64B] in { 347 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v32i8)), 348 (V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>; 349 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i8)), 350 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>; 351 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i16)), 352 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>; 353 } 354 let Predicates = [UseHVX,UseHVX128B] in { 355 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v64i8)), 356 (V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>; 357 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i8)), 358 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>; 359 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i16)), 360 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>; 361 } 362 363 def: Pat<(HexagonVASL HVI8:$Vs, I32:$Rt), 364 (V6_vpackeb (V6_vaslh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt), 365 (V6_vaslh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>; 366 def: Pat<(HexagonVASR HVI8:$Vs, I32:$Rt), 367 (V6_vpackeb (V6_vasrh (HiVec (VSxtb HvxVR:$Vs)), I32:$Rt), 368 (V6_vasrh (LoVec (VSxtb HvxVR:$Vs)), I32:$Rt))>; 369 def: Pat<(HexagonVLSR HVI8:$Vs, I32:$Rt), 370 (V6_vpackeb (V6_vlsrh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt), 371 (V6_vlsrh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>; 372 373 def: Pat<(HexagonVASL HVI16:$Vs, I32:$Rt), (V6_vaslh HvxVR:$Vs, I32:$Rt)>; 374 def: Pat<(HexagonVASL HVI32:$Vs, I32:$Rt), (V6_vaslw HvxVR:$Vs, I32:$Rt)>; 375 def: Pat<(HexagonVASR HVI16:$Vs, I32:$Rt), (V6_vasrh HvxVR:$Vs, I32:$Rt)>; 376 def: Pat<(HexagonVASR HVI32:$Vs, I32:$Rt), (V6_vasrw HvxVR:$Vs, I32:$Rt)>; 377 def: Pat<(HexagonVLSR HVI16:$Vs, I32:$Rt), (V6_vlsrh HvxVR:$Vs, I32:$Rt)>; 378 def: Pat<(HexagonVLSR HVI32:$Vs, I32:$Rt), (V6_vlsrw HvxVR:$Vs, I32:$Rt)>; 379 380 def: Pat<(add HVI32:$Vx, (HexagonVASL HVI32:$Vu, I32:$Rt)), 381 (V6_vaslw_acc HvxVR:$Vx, HvxVR:$Vu, I32:$Rt)>; 382 def: Pat<(add HVI32:$Vx, (HexagonVASR HVI32:$Vu, I32:$Rt)), 383 (V6_vasrw_acc HvxVR:$Vx, HvxVR:$Vu, I32:$Rt)>; 384 385 def: Pat<(shl HVI16:$Vs, HVI16:$Vt), (V6_vaslhv HvxVR:$Vs, HvxVR:$Vt)>; 386 def: Pat<(shl HVI32:$Vs, HVI32:$Vt), (V6_vaslwv HvxVR:$Vs, HvxVR:$Vt)>; 387 def: Pat<(sra HVI16:$Vs, HVI16:$Vt), (V6_vasrhv HvxVR:$Vs, HvxVR:$Vt)>; 388 def: Pat<(sra HVI32:$Vs, HVI32:$Vt), (V6_vasrwv HvxVR:$Vs, HvxVR:$Vt)>; 389 def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>; 390 def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>; 391 392 def: Pat<(VecI16 (bswap HVI16:$Vs)), 393 (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x01010101)))>; 394 def: Pat<(VecI32 (bswap HVI32:$Vs)), 395 (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x03030303)))>; 396 397 def: Pat<(VecI8 (ctpop HVI8:$Vs)), 398 (V6_vpackeb (V6_vpopcounth (HiVec (V6_vunpackub HvxVR:$Vs))), 399 (V6_vpopcounth (LoVec (V6_vunpackub HvxVR:$Vs))))>; 400 def: Pat<(VecI16 (ctpop HVI16:$Vs)), (V6_vpopcounth HvxVR:$Vs)>; 401 def: Pat<(VecI32 (ctpop HVI32:$Vs)), 402 (V6_vaddw (LoVec (V6_vzh (V6_vpopcounth HvxVR:$Vs))), 403 (HiVec (V6_vzh (V6_vpopcounth HvxVR:$Vs))))>; 404 405 def: Pat<(VecI8 (ctlz HVI8:$Vs)), 406 (V6_vsubb (V6_vpackeb (V6_vcl0h (HiVec (V6_vunpackub HvxVR:$Vs))), 407 (V6_vcl0h (LoVec (V6_vunpackub HvxVR:$Vs)))), 408 (V6_lvsplatw (A2_tfrsi 0x08080808)))>; 409 def: Pat<(VecI16 (ctlz HVI16:$Vs)), (V6_vcl0h HvxVR:$Vs)>; 410 def: Pat<(VecI32 (ctlz HVI32:$Vs)), (V6_vcl0w HvxVR:$Vs)>; 411} 412 413class HvxSel_pat<InstHexagon MI, PatFrag RegPred> 414 : Pat<(select I1:$Pu, RegPred:$Vs, RegPred:$Vt), 415 (MI I1:$Pu, RegPred:$Vs, RegPred:$Vt)>; 416 417let Predicates = [UseHVX] in { 418 def: HvxSel_pat<PS_vselect, HVI8>; 419 def: HvxSel_pat<PS_vselect, HVI16>; 420 def: HvxSel_pat<PS_vselect, HVI32>; 421 def: HvxSel_pat<PS_wselect, HWI8>; 422 def: HvxSel_pat<PS_wselect, HWI16>; 423 def: HvxSel_pat<PS_wselect, HWI32>; 424} 425 426let Predicates = [UseHVX] in { 427 def: Pat<(VecQ8 (qtrue)), (PS_qtrue)>; 428 def: Pat<(VecQ16 (qtrue)), (PS_qtrue)>; 429 def: Pat<(VecQ32 (qtrue)), (PS_qtrue)>; 430 def: Pat<(VecQ8 (qfalse)), (PS_qfalse)>; 431 def: Pat<(VecQ16 (qfalse)), (PS_qfalse)>; 432 def: Pat<(VecQ32 (qfalse)), (PS_qfalse)>; 433 434 def: Pat<(vnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>; 435 def: Pat<(vnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>; 436 def: Pat<(vnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>; 437 def: Pat<(qnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>; 438 def: Pat<(qnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>; 439 def: Pat<(qnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>; 440 441 def: OpR_RR_pat<V6_pred_and, And, VecQ8, HQ8>; 442 def: OpR_RR_pat<V6_pred_and, And, VecQ16, HQ16>; 443 def: OpR_RR_pat<V6_pred_and, And, VecQ32, HQ32>; 444 def: OpR_RR_pat<V6_pred_or, Or, VecQ8, HQ8>; 445 def: OpR_RR_pat<V6_pred_or, Or, VecQ16, HQ16>; 446 def: OpR_RR_pat<V6_pred_or, Or, VecQ32, HQ32>; 447 def: OpR_RR_pat<V6_pred_xor, Xor, VecQ8, HQ8>; 448 def: OpR_RR_pat<V6_pred_xor, Xor, VecQ16, HQ16>; 449 def: OpR_RR_pat<V6_pred_xor, Xor, VecQ32, HQ32>; 450 451 def: OpR_RR_pat<V6_pred_and_n, Not2<And>, VecQ8, HQ8>; 452 def: OpR_RR_pat<V6_pred_and_n, Not2<And>, VecQ16, HQ16>; 453 def: OpR_RR_pat<V6_pred_and_n, Not2<And>, VecQ32, HQ32>; 454 def: OpR_RR_pat<V6_pred_or_n, Not2<Or>, VecQ8, HQ8>; 455 def: OpR_RR_pat<V6_pred_or_n, Not2<Or>, VecQ16, HQ16>; 456 def: OpR_RR_pat<V6_pred_or_n, Not2<Or>, VecQ32, HQ32>; 457 458 def: OpR_RR_pat<V6_veqb, seteq, VecQ8, HVI8>; 459 def: OpR_RR_pat<V6_veqh, seteq, VecQ16, HVI16>; 460 def: OpR_RR_pat<V6_veqw, seteq, VecQ32, HVI32>; 461 def: OpR_RR_pat<V6_vgtb, setgt, VecQ8, HVI8>; 462 def: OpR_RR_pat<V6_vgth, setgt, VecQ16, HVI16>; 463 def: OpR_RR_pat<V6_vgtw, setgt, VecQ32, HVI32>; 464 def: OpR_RR_pat<V6_vgtub, setugt, VecQ8, HVI8>; 465 def: OpR_RR_pat<V6_vgtuh, setugt, VecQ16, HVI16>; 466 def: OpR_RR_pat<V6_vgtuw, setugt, VecQ32, HVI32>; 467 468 def: AccRRR_pat<V6_veqb_and, And, seteq, HQ8, HVI8, HVI8>; 469 def: AccRRR_pat<V6_veqb_or, Or, seteq, HQ8, HVI8, HVI8>; 470 def: AccRRR_pat<V6_veqb_xor, Xor, seteq, HQ8, HVI8, HVI8>; 471 def: AccRRR_pat<V6_veqh_and, And, seteq, HQ16, HVI16, HVI16>; 472 def: AccRRR_pat<V6_veqh_or, Or, seteq, HQ16, HVI16, HVI16>; 473 def: AccRRR_pat<V6_veqh_xor, Xor, seteq, HQ16, HVI16, HVI16>; 474 def: AccRRR_pat<V6_veqw_and, And, seteq, HQ32, HVI32, HVI32>; 475 def: AccRRR_pat<V6_veqw_or, Or, seteq, HQ32, HVI32, HVI32>; 476 def: AccRRR_pat<V6_veqw_xor, Xor, seteq, HQ32, HVI32, HVI32>; 477 478 def: AccRRR_pat<V6_vgtb_and, And, setgt, HQ8, HVI8, HVI8>; 479 def: AccRRR_pat<V6_vgtb_or, Or, setgt, HQ8, HVI8, HVI8>; 480 def: AccRRR_pat<V6_vgtb_xor, Xor, setgt, HQ8, HVI8, HVI8>; 481 def: AccRRR_pat<V6_vgth_and, And, setgt, HQ16, HVI16, HVI16>; 482 def: AccRRR_pat<V6_vgth_or, Or, setgt, HQ16, HVI16, HVI16>; 483 def: AccRRR_pat<V6_vgth_xor, Xor, setgt, HQ16, HVI16, HVI16>; 484 def: AccRRR_pat<V6_vgtw_and, And, setgt, HQ32, HVI32, HVI32>; 485 def: AccRRR_pat<V6_vgtw_or, Or, setgt, HQ32, HVI32, HVI32>; 486 def: AccRRR_pat<V6_vgtw_xor, Xor, setgt, HQ32, HVI32, HVI32>; 487 488 def: AccRRR_pat<V6_vgtub_and, And, setugt, HQ8, HVI8, HVI8>; 489 def: AccRRR_pat<V6_vgtub_or, Or, setugt, HQ8, HVI8, HVI8>; 490 def: AccRRR_pat<V6_vgtub_xor, Xor, setugt, HQ8, HVI8, HVI8>; 491 def: AccRRR_pat<V6_vgtuh_and, And, setugt, HQ16, HVI16, HVI16>; 492 def: AccRRR_pat<V6_vgtuh_or, Or, setugt, HQ16, HVI16, HVI16>; 493 def: AccRRR_pat<V6_vgtuh_xor, Xor, setugt, HQ16, HVI16, HVI16>; 494 def: AccRRR_pat<V6_vgtuw_and, And, setugt, HQ32, HVI32, HVI32>; 495 def: AccRRR_pat<V6_vgtuw_or, Or, setugt, HQ32, HVI32, HVI32>; 496 def: AccRRR_pat<V6_vgtuw_xor, Xor, setugt, HQ32, HVI32, HVI32>; 497} 498