1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips implementation of the TargetInstrInfo class. 11 // 12 // FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in 13 // order for MipsLongBranch pass to work correctly when the code has inline 14 // assembly. The returned value doesn't have to be the asm instruction's exact 15 // size in bytes; MipsLongBranch only expects it to be the correct upper bound. 16 //===----------------------------------------------------------------------===// 17 18 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 19 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 20 21 #include "MCTargetDesc/MipsMCTargetDesc.h" 22 #include "Mips.h" 23 #include "MipsRegisterInfo.h" 24 #include "llvm/ADT/ArrayRef.h" 25 #include "llvm/CodeGen/MachineBasicBlock.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineMemOperand.h" 28 #include "llvm/CodeGen/TargetInstrInfo.h" 29 #include <cstdint> 30 31 #define GET_INSTRINFO_HEADER 32 #include "MipsGenInstrInfo.inc" 33 34 namespace llvm { 35 36 class MachineInstr; 37 class MachineOperand; 38 class MipsSubtarget; 39 class TargetRegisterClass; 40 class TargetRegisterInfo; 41 42 class MipsInstrInfo : public MipsGenInstrInfo { 43 virtual void anchor(); 44 45 protected: 46 const MipsSubtarget &Subtarget; 47 unsigned UncondBrOpc; 48 49 public: 50 enum BranchType { 51 BT_None, // Couldn't analyze branch. 52 BT_NoBranch, // No branches found. 53 BT_Uncond, // One unconditional branch. 54 BT_Cond, // One conditional branch. 55 BT_CondUncond, // A conditional branch followed by an unconditional branch. 56 BT_Indirect // One indirct branch. 57 }; 58 59 explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc); 60 61 static const MipsInstrInfo *create(MipsSubtarget &STI); 62 63 /// Branch Analysis 64 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 65 MachineBasicBlock *&FBB, 66 SmallVectorImpl<MachineOperand> &Cond, 67 bool AllowModify) const override; 68 69 unsigned removeBranch(MachineBasicBlock &MBB, 70 int *BytesRemoved = nullptr) const override; 71 72 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 73 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 74 const DebugLoc &DL, 75 int *BytesAdded = nullptr) const override; 76 77 bool 78 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 79 80 BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 81 MachineBasicBlock *&FBB, 82 SmallVectorImpl<MachineOperand> &Cond, 83 bool AllowModify, 84 SmallVectorImpl<MachineInstr *> &BranchInstrs) const; 85 86 /// Determine the opcode of a non-delay slot form for a branch if one exists. 87 unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const; 88 89 /// Determine if the branch target is in range. 90 bool isBranchOffsetInRange(unsigned BranchOpc, 91 int64_t BrOffset) const override; 92 93 /// Predicate to determine if an instruction can go in a forbidden slot. 94 bool SafeInForbiddenSlot(const MachineInstr &MI) const; 95 96 /// Predicate to determine if an instruction has a forbidden slot. 97 bool HasForbiddenSlot(const MachineInstr &MI) const; 98 99 /// Insert nop instruction when hazard condition is found 100 void insertNoop(MachineBasicBlock &MBB, 101 MachineBasicBlock::iterator MI) const override; 102 103 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 104 /// such, whenever a client has an instance of instruction info, it should 105 /// always be able to get register info as well (through this method). 106 virtual const MipsRegisterInfo &getRegisterInfo() const = 0; 107 108 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; 109 110 /// Return the number of bytes of code the specified instruction may be. 111 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 112 storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,unsigned SrcReg,bool isKill,int FrameIndex,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI)113 void storeRegToStackSlot(MachineBasicBlock &MBB, 114 MachineBasicBlock::iterator MBBI, 115 unsigned SrcReg, bool isKill, int FrameIndex, 116 const TargetRegisterClass *RC, 117 const TargetRegisterInfo *TRI) const override { 118 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); 119 } 120 loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,unsigned DestReg,int FrameIndex,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI)121 void loadRegFromStackSlot(MachineBasicBlock &MBB, 122 MachineBasicBlock::iterator MBBI, 123 unsigned DestReg, int FrameIndex, 124 const TargetRegisterClass *RC, 125 const TargetRegisterInfo *TRI) const override { 126 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0); 127 } 128 129 virtual void storeRegToStack(MachineBasicBlock &MBB, 130 MachineBasicBlock::iterator MI, 131 unsigned SrcReg, bool isKill, int FrameIndex, 132 const TargetRegisterClass *RC, 133 const TargetRegisterInfo *TRI, 134 int64_t Offset) const = 0; 135 136 virtual void loadRegFromStack(MachineBasicBlock &MBB, 137 MachineBasicBlock::iterator MI, 138 unsigned DestReg, int FrameIndex, 139 const TargetRegisterClass *RC, 140 const TargetRegisterInfo *TRI, 141 int64_t Offset) const = 0; 142 143 virtual void adjustStackPtr(unsigned SP, int64_t Amount, 144 MachineBasicBlock &MBB, 145 MachineBasicBlock::iterator I) const = 0; 146 147 /// Create an instruction which has the same operands and memory operands 148 /// as MI but has a new opcode. 149 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, 150 MachineBasicBlock::iterator I) const; 151 152 bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, 153 unsigned &SrcOpIdx2) const override; 154 155 /// Perform target specific instruction verification. 156 bool verifyInstruction(const MachineInstr &MI, 157 StringRef &ErrInfo) const override; 158 159 std::pair<unsigned, unsigned> 160 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 161 162 ArrayRef<std::pair<unsigned, const char *>> 163 getSerializableDirectMachineOperandTargetFlags() const override; 164 165 protected: 166 bool isZeroImm(const MachineOperand &op) const; 167 168 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI, 169 MachineMemOperand::Flags Flags) const; 170 171 private: 172 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0; 173 174 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, 175 MachineBasicBlock *&BB, 176 SmallVectorImpl<MachineOperand> &Cond) const; 177 178 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 179 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const; 180 }; 181 182 /// Create MipsInstrInfo objects. 183 const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI); 184 const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI); 185 186 } // end namespace llvm 187 188 #endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 189