1//===-- MipsMTInstrInfo.td - Mips MT Instruction Infos -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the MIPS MT ASE as defined by MD00378 1.12. 11// 12// TODO: Add support for the microMIPS encodings for the MT ASE and add the 13// instruction mappings. 14// 15//===----------------------------------------------------------------------===// 16 17//===----------------------------------------------------------------------===// 18// MIPS MT Instruction Encodings 19//===----------------------------------------------------------------------===// 20 21class DMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT, 22 OPCODE_SC_D>; 23 24class EMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT, 25 OPCODE_SC_E>; 26 27class DVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE, 28 OPCODE_SC_D>; 29 30class EVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE, 31 OPCODE_SC_E>; 32 33class FORK_ENC : SPECIAL3_MT_FORK; 34 35class YIELD_ENC : SPECIAL3_MT_YIELD; 36 37class MFTR_ENC : COP0_MFTTR_MT<FIELD5_MFTR>; 38 39class MTTR_ENC : COP0_MFTTR_MT<FIELD5_MTTR>; 40 41//===----------------------------------------------------------------------===// 42// MIPS MT Instruction Descriptions 43//===----------------------------------------------------------------------===// 44 45class MT_1R_DESC_BASE<string instr_asm, InstrItinClass Itin = NoItinerary> { 46 dag OutOperandList = (outs GPR32Opnd:$rt); 47 dag InOperandList = (ins); 48 string AsmString = !strconcat(instr_asm, "\t$rt"); 49 list<dag> Pattern = []; 50 InstrItinClass Itinerary = Itin; 51} 52 53class MFTR_DESC { 54 dag OutOperandList = (outs GPR32Opnd:$rd); 55 dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h); 56 string AsmString = "mftr\t$rd, $rt, $u, $sel, $h"; 57 list<dag> Pattern = []; 58 InstrItinClass Itinerary = II_MFTR; 59} 60 61class MTTR_DESC { 62 dag OutOperandList = (outs GPR32Opnd:$rd); 63 dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h); 64 string AsmString = "mttr\t$rt, $rd, $u, $sel, $h"; 65 list<dag> Pattern = []; 66 InstrItinClass Itinerary = II_MTTR; 67} 68 69class FORK_DESC { 70 dag OutOperandList = (outs GPR32Opnd:$rs, GPR32Opnd:$rd); 71 dag InOperandList = (ins GPR32Opnd:$rt); 72 string AsmString = "fork\t$rd, $rs, $rt"; 73 list<dag> Pattern = []; 74 InstrItinClass Itinerary = II_FORK; 75} 76 77class YIELD_DESC { 78 dag OutOperandList = (outs GPR32Opnd:$rd); 79 dag InOperandList = (ins GPR32Opnd:$rs); 80 string AsmString = "yield\t$rd, $rs"; 81 list<dag> Pattern = []; 82 InstrItinClass Itinerary = II_YIELD; 83} 84 85class DMT_DESC : MT_1R_DESC_BASE<"dmt", II_DMT>; 86 87class EMT_DESC : MT_1R_DESC_BASE<"emt", II_EMT>; 88 89class DVPE_DESC : MT_1R_DESC_BASE<"dvpe", II_DVPE>; 90 91class EVPE_DESC : MT_1R_DESC_BASE<"evpe", II_EVPE>; 92 93//===----------------------------------------------------------------------===// 94// MIPS MT Instruction Definitions 95//===----------------------------------------------------------------------===// 96let hasSideEffects = 1, isNotDuplicable = 1, 97 AdditionalPredicates = [NotInMicroMips] in { 98 def DMT : DMT_ENC, DMT_DESC, ASE_MT; 99 100 def EMT : EMT_ENC, EMT_DESC, ASE_MT; 101 102 def DVPE : DVPE_ENC, DVPE_DESC, ASE_MT; 103 104 def EVPE : EVPE_ENC, EVPE_DESC, ASE_MT; 105 106 def FORK : FORK_ENC, FORK_DESC, ASE_MT; 107 108 def YIELD : YIELD_ENC, YIELD_DESC, ASE_MT; 109 110 def MFTR : MFTR_ENC, MFTR_DESC, ASE_MT; 111 112 def MTTR : MTTR_ENC, MTTR_DESC, ASE_MT; 113} 114 115//===----------------------------------------------------------------------===// 116// MIPS MT Pseudo Instructions - used to support mtfr & mttr aliases. 117//===----------------------------------------------------------------------===// 118def MFTC0 : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins COP0Opnd:$rt, 119 uimm3:$sel), 120 "mftc0 $rd, $rt, $sel">, ASE_MT; 121 122def MFTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rt, 123 uimm3:$sel), 124 "mftgpr $rd, $rt">, ASE_MT; 125 126def MFTLO : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac), 127 "mftlo $rt, $ac">, ASE_MT; 128 129def MFTHI : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac), 130 "mfthi $rt, $ac">, ASE_MT; 131 132def MFTACX : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac), 133 "mftacx $rt, $ac">, ASE_MT; 134 135def MFTDSP : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins), 136 "mftdsp $rt">, ASE_MT; 137 138def MFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft), 139 "mftc1 $rt, $ft">, ASE_MT; 140 141def MFTHC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft), 142 "mfthc1 $rt, $ft">, ASE_MT; 143 144def CFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGRCCOpnd:$ft), 145 "cftc1 $rt, $ft">, ASE_MT; 146 147 148def MTTC0 : MipsAsmPseudoInst<(outs COP0Opnd:$rd), (ins GPR32Opnd:$rt, 149 uimm3:$sel), 150 "mttc0 $rt, $rd, $sel">, ASE_MT; 151 152def MTTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins GPR32Opnd:$rd), 153 "mttgpr $rd, $rt">, ASE_MT; 154 155def MTTLO : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt), 156 "mttlo $rt, $ac">, ASE_MT; 157 158def MTTHI : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt), 159 "mtthi $rt, $ac">, ASE_MT; 160 161def MTTACX : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt), 162 "mttacx $rt, $ac">, ASE_MT; 163 164def MTTDSP : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rt), 165 "mttdsp $rt">, ASE_MT; 166 167def MTTC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt), 168 "mttc1 $rt, $ft">, ASE_MT; 169 170def MTTHC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt), 171 "mtthc1 $rt, $ft">, ASE_MT; 172 173def CTTC1 : MipsAsmPseudoInst<(outs FGRCCOpnd:$ft), (ins GPR32Opnd:$rt), 174 "cttc1 $rt, $ft">, ASE_MT; 175 176//===----------------------------------------------------------------------===// 177// MIPS MT Instruction Definitions 178//===----------------------------------------------------------------------===// 179 180let AdditionalPredicates = [NotInMicroMips] in { 181 def : MipsInstAlias<"dmt", (DMT ZERO), 1>, ASE_MT; 182 183 def : MipsInstAlias<"emt", (EMT ZERO), 1>, ASE_MT; 184 185 def : MipsInstAlias<"dvpe", (DVPE ZERO), 1>, ASE_MT; 186 187 def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT; 188 189 def : MipsInstAlias<"yield $rs", (YIELD ZERO, GPR32Opnd:$rs), 1>, ASE_MT; 190 191 def : MipsInstAlias<"mftc0 $rd, $rt", (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0), 192 1>, ASE_MT; 193 194 def : MipsInstAlias<"mftlo $rt", (MFTLO GPR32Opnd:$rt, AC0), 1>, ASE_MT; 195 196 def : MipsInstAlias<"mfthi $rt", (MFTHI GPR32Opnd:$rt, AC0), 1>, ASE_MT; 197 198 def : MipsInstAlias<"mftacx $rt", (MFTACX GPR32Opnd:$rt, AC0), 1>, ASE_MT; 199 200 def : MipsInstAlias<"mttc0 $rd, $rt", (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0), 201 1>, ASE_MT; 202 203 def : MipsInstAlias<"mttlo $rt", (MTTLO AC0, GPR32Opnd:$rt), 1>, ASE_MT; 204 205 def : MipsInstAlias<"mtthi $rt", (MTTHI AC0, GPR32Opnd:$rt), 1>, ASE_MT; 206 207 def : MipsInstAlias<"mttacx $rt", (MTTACX AC0, GPR32Opnd:$rt), 1>, ASE_MT; 208} 209