1//===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This describes the calling conventions for the PowerPC 32- and 64-bit 11// architectures. 12// 13//===----------------------------------------------------------------------===// 14 15/// CCIfSubtarget - Match if the current subtarget has a feature F. 16class CCIfSubtarget<string F, CCAction A> 17 : CCIf<!strconcat("static_cast<const PPCSubtarget&>" 18 "(State.getMachineFunction().getSubtarget()).", 19 F), 20 A>; 21class CCIfNotSubtarget<string F, CCAction A> 22 : CCIf<!strconcat("!static_cast<const PPCSubtarget&>" 23 "(State.getMachineFunction().getSubtarget()).", 24 F), 25 A>; 26class CCIfOrigArgWasNotPPCF128<CCAction A> 27 : CCIf<"!static_cast<PPCCCState *>(&State)->WasOriginalArgPPCF128(ValNo)", 28 A>; 29class CCIfOrigArgWasPPCF128<CCAction A> 30 : CCIf<"static_cast<PPCCCState *>(&State)->WasOriginalArgPPCF128(ValNo)", 31 A>; 32 33//===----------------------------------------------------------------------===// 34// Return Value Calling Convention 35//===----------------------------------------------------------------------===// 36 37// PPC64 AnyReg return-value convention. No explicit register is specified for 38// the return-value. The register allocator is allowed and expected to choose 39// any free register. 40// 41// This calling convention is currently only supported by the stackmap and 42// patchpoint intrinsics. All other uses will result in an assert on Debug 43// builds. On Release builds we fallback to the PPC C calling convention. 44def RetCC_PPC64_AnyReg : CallingConv<[ 45 CCCustom<"CC_PPC_AnyReg_Error"> 46]>; 47 48// Return-value convention for PowerPC coldcc. 49def RetCC_PPC_Cold : CallingConv<[ 50 // Use the same return registers as RetCC_PPC, but limited to only 51 // one return value. The remaining return values will be saved to 52 // the stack. 53 CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>, 54 CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>, 55 56 CCIfType<[i32], CCAssignToReg<[R3]>>, 57 CCIfType<[i64], CCAssignToReg<[X3]>>, 58 CCIfType<[i128], CCAssignToReg<[X3]>>, 59 60 CCIfType<[f32], CCAssignToReg<[F1]>>, 61 CCIfType<[f64], CCAssignToReg<[F1]>>, 62 CCIfType<[f128], CCIfSubtarget<"hasP9Vector()", CCAssignToReg<[V2]>>>, 63 64 CCIfType<[v4f64, v4f32, v4i1], 65 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1]>>>, 66 67 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64], 68 CCIfSubtarget<"hasAltivec()", 69 CCAssignToReg<[V2]>>> 70]>; 71 72// Return-value convention for PowerPC 73def RetCC_PPC : CallingConv<[ 74 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>, 75 76 // On PPC64, integer return values are always promoted to i64 77 CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>, 78 CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>, 79 80 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, 81 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>, 82 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, 83 84 // Floating point types returned as "direct" go into F1 .. F8; note that 85 // only the ELFv2 ABI fully utilizes all these registers. 86 CCIfNotSubtarget<"hasSPE()", 87 CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>, 88 CCIfNotSubtarget<"hasSPE()", 89 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>, 90 CCIfSubtarget<"hasSPE()", 91 CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>, 92 CCIfSubtarget<"hasSPE()", 93 CCIfType<[f64], CCAssignToReg<[S3, S4, S5, S6, S7, S8, S9, S10]>>>, 94 95 // For P9, f128 are passed in vector registers. 96 CCIfType<[f128], 97 CCIfSubtarget<"hasP9Vector()", 98 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>, 99 100 // QPX vectors are returned in QF1 and QF2. 101 CCIfType<[v4f64, v4f32, v4i1], 102 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>, 103 104 // Vector types returned as "direct" go into V2 .. V9; note that only the 105 // ELFv2 ABI fully utilizes all these registers. 106 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64], 107 CCIfSubtarget<"hasAltivec()", 108 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>> 109]>; 110 111// No explicit register is specified for the AnyReg calling convention. The 112// register allocator may assign the arguments to any free register. 113// 114// This calling convention is currently only supported by the stackmap and 115// patchpoint intrinsics. All other uses will result in an assert on Debug 116// builds. On Release builds we fallback to the PPC C calling convention. 117def CC_PPC64_AnyReg : CallingConv<[ 118 CCCustom<"CC_PPC_AnyReg_Error"> 119]>; 120 121// Note that we don't currently have calling conventions for 64-bit 122// PowerPC, but handle all the complexities of the ABI in the lowering 123// logic. FIXME: See if the logic can be simplified with use of CCs. 124// This may require some extensions to current table generation. 125 126// Simple calling convention for 64-bit ELF PowerPC fast isel. 127// Only handle ints and floats. All ints are promoted to i64. 128// Vector types and quadword ints are not handled. 129def CC_PPC64_ELF_FIS : CallingConv<[ 130 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>, 131 132 CCIfType<[i1], CCPromoteToType<i64>>, 133 CCIfType<[i8], CCPromoteToType<i64>>, 134 CCIfType<[i16], CCPromoteToType<i64>>, 135 CCIfType<[i32], CCPromoteToType<i64>>, 136 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>, 137 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>> 138]>; 139 140// Simple return-value convention for 64-bit ELF PowerPC fast isel. 141// All small ints are promoted to i64. Vector types, quadword ints, 142// and multiple register returns are "supported" to avoid compile 143// errors, but none are handled by the fast selector. 144def RetCC_PPC64_ELF_FIS : CallingConv<[ 145 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>, 146 147 CCIfType<[i1], CCPromoteToType<i64>>, 148 CCIfType<[i8], CCPromoteToType<i64>>, 149 CCIfType<[i16], CCPromoteToType<i64>>, 150 CCIfType<[i32], CCPromoteToType<i64>>, 151 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>, 152 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, 153 CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, 154 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, 155 CCIfType<[f128], 156 CCIfSubtarget<"hasP9Vector()", 157 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>, 158 CCIfType<[v4f64, v4f32, v4i1], 159 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>, 160 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64], 161 CCIfSubtarget<"hasAltivec()", 162 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>> 163]>; 164 165//===----------------------------------------------------------------------===// 166// PowerPC System V Release 4 32-bit ABI 167//===----------------------------------------------------------------------===// 168 169def CC_PPC32_SVR4_Common : CallingConv<[ 170 CCIfType<[i1], CCPromoteToType<i32>>, 171 172 // The ABI requires i64 to be passed in two adjacent registers with the first 173 // register having an odd register number. 174 CCIfType<[i32], 175 CCIfSplit<CCIfSubtarget<"useSoftFloat()", 176 CCIfOrigArgWasNotPPCF128< 177 CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>>>, 178 179 CCIfType<[i32], 180 CCIfSplit<CCIfNotSubtarget<"useSoftFloat()", 181 CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>>, 182 CCIfSplit<CCIfSubtarget<"useSoftFloat()", 183 CCIfOrigArgWasPPCF128<CCCustom< 184 "CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128">>>>, 185 186 // The 'nest' parameter, if any, is passed in R11. 187 CCIfNest<CCAssignToReg<[R11]>>, 188 189 // The first 8 integer arguments are passed in integer registers. 190 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, 191 192 // Make sure the i64 words from a long double are either both passed in 193 // registers or both passed on the stack. 194 CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>, 195 196 // FP values are passed in F1 - F8. 197 CCIfType<[f32, f64], 198 CCIfNotSubtarget<"hasSPE()", 199 CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>, 200 CCIfType<[f64], 201 CCIfSubtarget<"hasSPE()", 202 CCAssignToReg<[S3, S4, S5, S6, S7, S8, S9, S10]>>>, 203 CCIfType<[f32], 204 CCIfSubtarget<"hasSPE()", 205 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>, 206 207 // Split arguments have an alignment of 8 bytes on the stack. 208 CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>, 209 210 CCIfType<[i32], CCAssignToStack<4, 4>>, 211 212 // Floats are stored in double precision format, thus they have the same 213 // alignment and size as doubles. 214 // With SPE floats are stored as single precision, so have alignment and 215 // size of int. 216 CCIfType<[f32,f64], CCIfNotSubtarget<"hasSPE()", CCAssignToStack<8, 8>>>, 217 CCIfType<[f32], CCIfSubtarget<"hasSPE()", CCAssignToStack<4, 4>>>, 218 CCIfType<[f64], CCIfSubtarget<"hasSPE()", CCAssignToStack<8, 8>>>, 219 220 // QPX vectors that are stored in double precision need 32-byte alignment. 221 CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>, 222 223 // Vectors and float128 get 16-byte stack slots that are 16-byte aligned. 224 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>, 225 CCIfType<[f128], CCIfSubtarget<"hasP9Vector()", CCAssignToStack<16, 16>>> 226]>; 227 228// This calling convention puts vector arguments always on the stack. It is used 229// to assign vector arguments which belong to the variable portion of the 230// parameter list of a variable argument function. 231def CC_PPC32_SVR4_VarArg : CallingConv<[ 232 CCDelegateTo<CC_PPC32_SVR4_Common> 233]>; 234 235// In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to 236// put vector arguments in vector registers before putting them on the stack. 237def CC_PPC32_SVR4 : CallingConv<[ 238 // QPX vectors mirror the scalar FP convention. 239 CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()", 240 CCAssignToReg<[QF1, QF2, QF3, QF4, QF5, QF6, QF7, QF8]>>>, 241 242 // The first 12 Vector arguments are passed in AltiVec registers. 243 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64], 244 CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2, V3, V4, V5, V6, V7, 245 V8, V9, V10, V11, V12, V13]>>>, 246 247 // Float128 types treated as vector arguments. 248 CCIfType<[f128], 249 CCIfSubtarget<"hasP9Vector()", CCAssignToReg<[V2, V3, V4, V5, V6, V7, 250 V8, V9, V10, V11, V12, V13]>>>, 251 252 CCDelegateTo<CC_PPC32_SVR4_Common> 253]>; 254 255// Helper "calling convention" to handle aggregate by value arguments. 256// Aggregate by value arguments are always placed in the local variable space 257// of the caller. This calling convention is only used to assign those stack 258// offsets in the callers stack frame. 259// 260// Still, the address of the aggregate copy in the callers stack frame is passed 261// in a GPR (or in the parameter list area if all GPRs are allocated) from the 262// caller to the callee. The location for the address argument is assigned by 263// the CC_PPC32_SVR4 calling convention. 264// 265// The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are 266// not passed by value. 267 268def CC_PPC32_SVR4_ByVal : CallingConv<[ 269 CCIfByVal<CCPassByVal<4, 4>>, 270 271 CCCustom<"CC_PPC32_SVR4_Custom_Dummy"> 272]>; 273 274def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27, 275 V28, V29, V30, V31)>; 276 277def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20, 278 R21, R22, R23, R24, R25, R26, R27, R28, 279 R29, R30, R31, F14, F15, F16, F17, F18, 280 F19, F20, F21, F22, F23, F24, F25, F26, 281 F27, F28, F29, F30, F31, CR2, CR3, CR4 282 )>; 283 284def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>; 285 286// SPE does not use FPRs, so break out the common register set as base. 287def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, 288 R21, R22, R23, R24, R25, R26, R27, 289 R28, R29, R30, R31, CR2, CR3, CR4 290 )>; 291def CSR_SVR432 : CalleeSavedRegs<(add CSR_SVR432_COMM, F14, F15, F16, F17, F18, 292 F19, F20, F21, F22, F23, F24, F25, F26, 293 F27, F28, F29, F30, F31 294 )>; 295def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22, 296 S23, S24, S25, S26, S27, S28, S29, S30, S31 297 )>; 298 299def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>; 300 301def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>; 302 303def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20, 304 X21, X22, X23, X24, X25, X26, X27, X28, 305 X29, X30, X31, F14, F15, F16, F17, F18, 306 F19, F20, F21, F22, F23, F24, F25, F26, 307 F27, F28, F29, F30, F31, CR2, CR3, CR4 308 )>; 309 310def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>; 311 312def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, 313 X21, X22, X23, X24, X25, X26, X27, X28, 314 X29, X30, X31, F14, F15, F16, F17, F18, 315 F19, F20, F21, F22, F23, F24, F25, F26, 316 F27, F28, F29, F30, F31, CR2, CR3, CR4 317 )>; 318 319// CSRs that are handled by prologue, epilogue. 320def CSR_SRV464_TLS_PE : CalleeSavedRegs<(add)>; 321 322def CSR_SVR464_ViaCopy : CalleeSavedRegs<(add CSR_SVR464)>; 323 324def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>; 325 326def CSR_SVR464_Altivec_ViaCopy : CalleeSavedRegs<(add CSR_SVR464_Altivec)>; 327 328def CSR_SVR464_R2 : CalleeSavedRegs<(add CSR_SVR464, X2)>; 329 330def CSR_SVR464_R2_ViaCopy : CalleeSavedRegs<(add CSR_SVR464_R2)>; 331 332def CSR_SVR464_R2_Altivec : CalleeSavedRegs<(add CSR_SVR464_Altivec, X2)>; 333 334def CSR_SVR464_R2_Altivec_ViaCopy : CalleeSavedRegs<(add CSR_SVR464_R2_Altivec)>; 335 336def CSR_NoRegs : CalleeSavedRegs<(add)>; 337 338// coldcc calling convection marks most registers as non-volatile. 339// Do not include r1 since the stack pointer is never considered a CSR. 340// Do not include r2, since it is the TOC register and is added depending 341// on wether or not the function uses the TOC and is a non-leaf. 342// Do not include r0,r11,r13 as they are optional in functional linkage 343// and value may be altered by inter-library calls. 344// Do not include r12 as it is used as a scratch register. 345// Do not include return registers r3, f1, v2. 346def CSR_SVR32_ColdCC : CalleeSavedRegs<(add (sequence "R%u", 4, 10), 347 (sequence "R%u", 14, 31), 348 F0, (sequence "F%u", 2, 31), 349 (sequence "CR%u", 0, 7))>; 350 351def CSR_SVR32_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR32_ColdCC, 352 (sequence "V%u", 0, 1), 353 (sequence "V%u", 3, 31))>; 354 355def CSR_SVR64_ColdCC : CalleeSavedRegs<(add (sequence "X%u", 4, 10), 356 (sequence "X%u", 14, 31), 357 F0, (sequence "F%u", 2, 31), 358 (sequence "CR%u", 0, 7))>; 359 360def CSR_SVR64_ColdCC_R2: CalleeSavedRegs<(add CSR_SVR64_ColdCC, X2)>; 361 362def CSR_SVR64_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR64_ColdCC, 363 (sequence "V%u", 0, 1), 364 (sequence "V%u", 3, 31))>; 365 366def CSR_SVR64_ColdCC_R2_Altivec : CalleeSavedRegs<(add CSR_SVR64_ColdCC_Altivec, X2)>; 367 368def CSR_64_AllRegs: CalleeSavedRegs<(add X0, (sequence "X%u", 3, 10), 369 (sequence "X%u", 14, 31), 370 (sequence "F%u", 0, 31), 371 (sequence "CR%u", 0, 7))>; 372 373def CSR_64_AllRegs_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs, 374 (sequence "V%u", 0, 31))>; 375 376def CSR_64_AllRegs_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec, 377 (sequence "VSL%u", 0, 31))>; 378 379