1; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK-CVT --check-prefix=CHECK 2; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK-FP16 --check-prefix=CHECK 3 4define <8 x half> @add_h(<8 x half> %a, <8 x half> %b) { 5entry: 6; CHECK-CVT-LABEL: add_h: 7; CHECK-CVT: fcvt 8; CHECK-CVT: fcvt 9; CHECK-CVT-DAG: fadd 10; CHECK-CVT-DAG: fcvt 11; CHECK-CVT-DAG: fcvt 12; CHECK-CVT-DAG: fadd 13; CHECK-CVT-DAG: fcvt 14; CHECK-CVT-DAG: fcvt 15; CHECK-CVT-DAG: fadd 16; CHECK-CVT-DAG: fcvt 17; CHECK-CVT-DAG: fcvt 18; CHECK-CVT-DAG: fadd 19; CHECK-CVT-DAG: fcvt 20; CHECK-CVT-DAG: fcvt 21; CHECK-CVT-DAG: fadd 22; CHECK-CVT-DAG: fcvt 23; CHECK-CVT-DAG: fcvt 24; CHECK-CVT-DAG: fadd 25; CHECK-CVT-DAG: fcvt 26; CHECK-CVT-DAG: fcvt 27; CHECK-CVT-DAG: fadd 28; CHECK-CVT-DAG: fcvt 29; CHECK-CVT-DAG: fcvt 30; CHECK-CVT-DAG: fadd 31; CHECK-CVT-DAG: fcvt 32; CHECK-CVT-DAG: fcvt 33; CHECK-CVT-DAG: fcvt 34; CHECK-CVT-DAG: fcvt 35; CHECK-CVT-DAG: fcvt 36; CHECK-CVT-DAG: fcvt 37; CHECK-CVT-DAG: fcvt 38; CHECK-CVT: fcvt 39 40; CHECK-FP16-LABEL: add_h: 41; CHECK-FP16: fadd v0.8h, v0.8h, v1.8h 42; CHECK-FP16-NEXT: ret 43 44 %0 = fadd <8 x half> %a, %b 45 ret <8 x half> %0 46} 47 48 49define <8 x half> @sub_h(<8 x half> %a, <8 x half> %b) { 50entry: 51; CHECK-CVT-LABEL: sub_h: 52; CHECK-CVT: fcvt 53; CHECK-CVT: fcvt 54; CHECK-CVT-DAG: fsub 55; CHECK-CVT-DAG: fcvt 56; CHECK-CVT-DAG: fcvt 57; CHECK-CVT-DAG: fsub 58; CHECK-CVT-DAG: fcvt 59; CHECK-CVT-DAG: fcvt 60; CHECK-CVT-DAG: fsub 61; CHECK-CVT-DAG: fcvt 62; CHECK-CVT-DAG: fcvt 63; CHECK-CVT-DAG: fsub 64; CHECK-CVT-DAG: fcvt 65; CHECK-CVT-DAG: fcvt 66; CHECK-CVT-DAG: fsub 67; CHECK-CVT-DAG: fcvt 68; CHECK-CVT-DAG: fcvt 69; CHECK-CVT-DAG: fsub 70; CHECK-CVT-DAG: fcvt 71; CHECK-CVT-DAG: fcvt 72; CHECK-CVT-DAG: fsub 73; CHECK-CVT-DAG: fcvt 74; CHECK-CVT-DAG: fcvt 75; CHECK-CVT-DAG: fsub 76; CHECK-CVT-DAG: fcvt 77; CHECK-CVT-DAG: fcvt 78; CHECK-CVT-DAG: fcvt 79; CHECK-CVT-DAG: fcvt 80; CHECK-CVT-DAG: fcvt 81; CHECK-CVT-DAG: fcvt 82; CHECK-CVT-DAG: fcvt 83; CHECK-CVT: fcvt 84 85; CHECK-FP16-LABEL: sub_h: 86; CHECK-FP16: fsub v0.8h, v0.8h, v1.8h 87; CHECK-FP16-NEXT: ret 88 89 %0 = fsub <8 x half> %a, %b 90 ret <8 x half> %0 91} 92 93 94define <8 x half> @mul_h(<8 x half> %a, <8 x half> %b) { 95entry: 96; CHECK-CVT-LABEL: mul_h: 97; CHECK-CVT: fcvt 98; CHECK-CVT: fcvt 99; CHECK-CVT-DAG: fmul 100; CHECK-CVT-DAG: fcvt 101; CHECK-CVT-DAG: fcvt 102; CHECK-CVT-DAG: fmul 103; CHECK-CVT-DAG: fcvt 104; CHECK-CVT-DAG: fcvt 105; CHECK-CVT-DAG: fmul 106; CHECK-CVT-DAG: fcvt 107; CHECK-CVT-DAG: fcvt 108; CHECK-CVT-DAG: fmul 109; CHECK-CVT-DAG: fcvt 110; CHECK-CVT-DAG: fcvt 111; CHECK-CVT-DAG: fmul 112; CHECK-CVT-DAG: fcvt 113; CHECK-CVT-DAG: fcvt 114; CHECK-CVT-DAG: fmul 115; CHECK-CVT-DAG: fcvt 116; CHECK-CVT-DAG: fcvt 117; CHECK-CVT-DAG: fmul 118; CHECK-CVT-DAG: fcvt 119; CHECK-CVT-DAG: fcvt 120; CHECK-CVT-DAG: fmul 121; CHECK-CVT-DAG: fcvt 122; CHECK-CVT-DAG: fcvt 123; CHECK-CVT-DAG: fcvt 124; CHECK-CVT-DAG: fcvt 125; CHECK-CVT-DAG: fcvt 126; CHECK-CVT-DAG: fcvt 127; CHECK-CVT-DAG: fcvt 128; CHECK-CVT: fcvt 129 130; CHECK-FP16-LABEL: mul_h: 131; CHECK-FP16: fmul v0.8h, v0.8h, v1.8h 132; CHECK-FP16-NEXT: ret 133 134 %0 = fmul <8 x half> %a, %b 135 ret <8 x half> %0 136} 137 138 139define <8 x half> @div_h(<8 x half> %a, <8 x half> %b) { 140entry: 141; CHECK-CVT-LABEL: div_h: 142; CHECK-CVT: fcvt 143; CHECK-CVT: fcvt 144; CHECK-CVT-DAG: fdiv 145; CHECK-CVT-DAG: fcvt 146; CHECK-CVT-DAG: fcvt 147; CHECK-CVT-DAG: fdiv 148; CHECK-CVT-DAG: fcvt 149; CHECK-CVT-DAG: fcvt 150; CHECK-CVT-DAG: fdiv 151; CHECK-CVT-DAG: fcvt 152; CHECK-CVT-DAG: fcvt 153; CHECK-CVT-DAG: fdiv 154; CHECK-CVT-DAG: fcvt 155; CHECK-CVT-DAG: fcvt 156; CHECK-CVT-DAG: fdiv 157; CHECK-CVT-DAG: fcvt 158; CHECK-CVT-DAG: fcvt 159; CHECK-CVT-DAG: fdiv 160; CHECK-CVT-DAG: fcvt 161; CHECK-CVT-DAG: fcvt 162; CHECK-CVT-DAG: fdiv 163; CHECK-CVT-DAG: fcvt 164; CHECK-CVT-DAG: fcvt 165; CHECK-CVT-DAG: fdiv 166; CHECK-CVT-DAG: fcvt 167; CHECK-CVT-DAG: fcvt 168; CHECK-CVT-DAG: fcvt 169; CHECK-CVT-DAG: fcvt 170; CHECK-CVT-DAG: fcvt 171; CHECK-CVT-DAG: fcvt 172; CHECK-CVT-DAG: fcvt 173; CHECK-CVT: fcvt 174 175; CHECK-FP16-LABEL: div_h: 176; CHECK-FP16: fdiv v0.8h, v0.8h, v1.8h 177; CHECK-FP16-NEXT: ret 178 179 %0 = fdiv <8 x half> %a, %b 180 ret <8 x half> %0 181} 182 183 184define <8 x half> @load_h(<8 x half>* %a) { 185entry: 186; CHECK-LABEL: load_h: 187; CHECK: ldr q0, [x0] 188 %0 = load <8 x half>, <8 x half>* %a, align 4 189 ret <8 x half> %0 190} 191 192 193define void @store_h(<8 x half>* %a, <8 x half> %b) { 194entry: 195; CHECK-LABEL: store_h: 196; CHECK: str q0, [x0] 197 store <8 x half> %b, <8 x half>* %a, align 4 198 ret void 199} 200 201define <8 x half> @s_to_h(<8 x float> %a) { 202; CHECK-LABEL: s_to_h: 203; CHECK-DAG: fcvtn v0.4h, v0.4s 204; CHECK-DAG: fcvtn [[REG:v[0-9+]]].4h, v1.4s 205; CHECK: mov v0.d[1], [[REG]].d[0] 206 %1 = fptrunc <8 x float> %a to <8 x half> 207 ret <8 x half> %1 208} 209 210define <8 x half> @d_to_h(<8 x double> %a) { 211; CHECK-LABEL: d_to_h: 212; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1] 213; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1] 214; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1] 215; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1] 216; CHECK-DAG: fcvt h 217; CHECK-DAG: fcvt h 218; CHECK-DAG: fcvt h 219; CHECK-DAG: fcvt h 220; CHECK-DAG: fcvt h 221; CHECK-DAG: fcvt h 222; CHECK-DAG: fcvt h 223; CHECK-DAG: fcvt h 224; CHECK-DAG: mov v{{[0-9]+}}.h 225; CHECK-DAG: mov v{{[0-9]+}}.h 226; CHECK-DAG: mov v{{[0-9]+}}.h 227; CHECK-DAG: mov v{{[0-9]+}}.h 228; CHECK-DAG: mov v{{[0-9]+}}.h 229; CHECK-DAG: mov v{{[0-9]+}}.h 230; CHECK-DAG: mov v{{[0-9]+}}.h 231; CHECK-DAG: mov v{{[0-9]+}}.h 232 %1 = fptrunc <8 x double> %a to <8 x half> 233 ret <8 x half> %1 234} 235 236define <8 x float> @h_to_s(<8 x half> %a) { 237; CHECK-LABEL: h_to_s: 238; CHECK: fcvtl2 v1.4s, v0.8h 239; CHECK: fcvtl v0.4s, v0.4h 240 %1 = fpext <8 x half> %a to <8 x float> 241 ret <8 x float> %1 242} 243 244define <8 x double> @h_to_d(<8 x half> %a) { 245; CHECK-LABEL: h_to_d: 246; CHECK-DAG: mov h{{[0-9]+}}, v0.h 247; CHECK-DAG: mov h{{[0-9]+}}, v0.h 248; CHECK-DAG: mov h{{[0-9]+}}, v0.h 249; CHECK-DAG: mov h{{[0-9]+}}, v0.h 250; CHECK-DAG: mov h{{[0-9]+}}, v0.h 251; CHECK-DAG: mov h{{[0-9]+}}, v0.h 252; CHECK-DAG: mov h{{[0-9]+}}, v0.h 253; CHECK-DAG: fcvt d 254; CHECK-DAG: fcvt d 255; CHECK-DAG: fcvt d 256; CHECK-DAG: fcvt d 257; CHECK-DAG: fcvt d 258; CHECK-DAG: fcvt d 259; CHECK-DAG: fcvt d 260; CHECK-DAG: fcvt d 261 %1 = fpext <8 x half> %a to <8 x double> 262 ret <8 x double> %1 263} 264 265 266define <8 x half> @bitcast_i_to_h(float, <8 x i16> %a) { 267; CHECK-LABEL: bitcast_i_to_h: 268; CHECK: mov v0.16b, v1.16b 269 %2 = bitcast <8 x i16> %a to <8 x half> 270 ret <8 x half> %2 271} 272 273define <8 x i16> @bitcast_h_to_i(float, <8 x half> %a) { 274; CHECK-LABEL: bitcast_h_to_i: 275; CHECK: mov v0.16b, v1.16b 276 %2 = bitcast <8 x half> %a to <8 x i16> 277 ret <8 x i16> %2 278} 279 280 281define <8 x half> @sitofp_i8(<8 x i8> %a) #0 { 282; CHECK-LABEL: sitofp_i8: 283; CHECK-NEXT: sshll v[[REG1:[0-9]+]].8h, v0.8b, #0 284; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0 285; CHECK-NEXT: sshll [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0 286; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]] 287; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]] 288; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]] 289; CHECK-DAG: fcvtn v0.4h, [[HIF]] 290; CHECK: mov v0.d[1], v[[LOREG]].d[0] 291 %1 = sitofp <8 x i8> %a to <8 x half> 292 ret <8 x half> %1 293} 294 295 296define <8 x half> @sitofp_i16(<8 x i16> %a) #0 { 297; CHECK-LABEL: sitofp_i16: 298; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v0.8h, #0 299; CHECK-NEXT: sshll [[HI:v[0-9]+\.4s]], v0.4h, #0 300; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]] 301; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]] 302; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]] 303; CHECK-DAG: fcvtn v0.4h, [[HIF]] 304; CHECK: mov v0.d[1], v[[LOREG]].d[0] 305 %1 = sitofp <8 x i16> %a to <8 x half> 306 ret <8 x half> %1 307} 308 309 310define <8 x half> @sitofp_i32(<8 x i32> %a) #0 { 311; CHECK-LABEL: sitofp_i32: 312; CHECK-DAG: scvtf [[OP1:v[0-9]+\.4s]], v0.4s 313; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s 314; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]] 315; CHECK-DAG: fcvtn v0.4h, [[OP1]] 316; CHECK: mov v0.d[1], v[[REG]].d[0] 317 %1 = sitofp <8 x i32> %a to <8 x half> 318 ret <8 x half> %1 319} 320 321 322define <8 x half> @sitofp_i64(<8 x i64> %a) #0 { 323; CHECK-LABEL: sitofp_i64: 324; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d 325; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d 326; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]] 327; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]] 328; CHECK: fcvtn v0.4h, [[OP3]].4s 329 %1 = sitofp <8 x i64> %a to <8 x half> 330 ret <8 x half> %1 331} 332 333define <8 x half> @uitofp_i8(<8 x i8> %a) #0 { 334; CHECK-LABEL: uitofp_i8: 335; CHECK-NEXT: ushll v[[REG1:[0-9]+]].8h, v0.8b, #0 336; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0 337; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0 338; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]] 339; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]] 340; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]] 341; CHECK-DAG: fcvtn v0.4h, [[HIF]] 342; CHECK: mov v0.d[1], v[[LOREG]].d[0] 343 %1 = uitofp <8 x i8> %a to <8 x half> 344 ret <8 x half> %1 345} 346 347 348define <8 x half> @uitofp_i16(<8 x i16> %a) #0 { 349; CHECK-LABEL: uitofp_i16: 350; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v0.8h, #0 351; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v0.4h, #0 352; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]] 353; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]] 354; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]] 355; CHECK-DAG: fcvtn v0.4h, [[HIF]] 356; CHECK: mov v0.d[1], v[[LOREG]].d[0] 357 %1 = uitofp <8 x i16> %a to <8 x half> 358 ret <8 x half> %1 359} 360 361 362define <8 x half> @uitofp_i32(<8 x i32> %a) #0 { 363; CHECK-LABEL: uitofp_i32: 364; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s 365; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s 366; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]] 367; CHECK-DAG: fcvtn v0.4h, [[OP1]] 368; CHECK: mov v0.d[1], v[[REG]].d[0] 369 %1 = uitofp <8 x i32> %a to <8 x half> 370 ret <8 x half> %1 371} 372 373 374define <8 x half> @uitofp_i64(<8 x i64> %a) #0 { 375; CHECK-LABEL: uitofp_i64: 376; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d 377; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d 378; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]] 379; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]] 380; CHECK: fcvtn v0.4h, [[OP3]].4s 381 %1 = uitofp <8 x i64> %a to <8 x half> 382 ret <8 x half> %1 383} 384 385define void @test_insert_at_zero(half %a, <8 x half>* %b) #0 { 386; CHECK-LABEL: test_insert_at_zero: 387; CHECK-NEXT: str q0, [x0] 388; CHECK-NEXT: ret 389 %1 = insertelement <8 x half> undef, half %a, i64 0 390 store <8 x half> %1, <8 x half>* %b, align 4 391 ret void 392} 393 394define <8 x i8> @fptosi_i8(<8 x half> %a) #0 { 395; CHECK-LABEL: fptosi_i8: 396; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h 397; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h 398; CHECK-DAG: fcvtzs [[LOF32:v[0-9]+\.4s]], [[LO]] 399; CHECK-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] 400; CHECK-DAG: fcvtzs [[HIF32:v[0-9]+\.4s]], [[HI]] 401; CHECK-DAG: xtn2 [[I16]].8h, [[HIF32]] 402; CHECK-NEXT: xtn v0.8b, [[I16]].8h 403; CHECK-NEXT: ret 404 %1 = fptosi<8 x half> %a to <8 x i8> 405 ret <8 x i8> %1 406} 407 408define <8 x i16> @fptosi_i16(<8 x half> %a) #0 { 409; CHECK-LABEL: fptosi_i16: 410; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h 411; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h 412; CHECK-DAG: fcvtzs [[LOF32:v[0-9]+\.4s]], [[LO]] 413; CHECK-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] 414; CHECK-DAG: fcvtzs [[HIF32:v[0-9]+\.4s]], [[HI]] 415; CHECK-NEXT: xtn2 [[I16]].8h, [[HIF32]] 416; CHECK-NEXT: ret 417 %1 = fptosi<8 x half> %a to <8 x i16> 418 ret <8 x i16> %1 419} 420 421define <8 x i8> @fptoui_i8(<8 x half> %a) #0 { 422; CHECK-LABEL: fptoui_i8: 423; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h 424; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h 425; CHECK-DAG: fcvtzu [[LOF32:v[0-9]+\.4s]], [[LO]] 426; CHECK-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] 427; CHECK-DAG: fcvtzu [[HIF32:v[0-9]+\.4s]], [[HI]] 428; CHECK-DAG: xtn2 [[I16]].8h, [[HIF32]] 429; CHECK-NEXT: xtn v0.8b, [[I16]].8h 430; CHECK-NEXT: ret 431 %1 = fptoui<8 x half> %a to <8 x i8> 432 ret <8 x i8> %1 433} 434 435define <8 x i16> @fptoui_i16(<8 x half> %a) #0 { 436; CHECK-LABEL: fptoui_i16: 437; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h 438; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h 439; CHECK-DAG: fcvtzu [[LOF32:v[0-9]+\.4s]], [[LO]] 440; CHECK-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] 441; CHECK-DAG: fcvtzu [[HIF32:v[0-9]+\.4s]], [[HI]] 442; CHECK-NEXT: xtn2 [[I16]].8h, [[HIF32]] 443; CHECK-NEXT: ret 444 %1 = fptoui<8 x half> %a to <8 x i16> 445 ret <8 x i16> %1 446} 447 448define <8 x i1> @test_fcmp_une(<8 x half> %a, <8 x half> %b) #0 { 449; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 450 451; CHECK-FP16-LABEL: test_fcmp_une: 452; CHECK-FP16-NOT: fcvt 453; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 454; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 455; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 456; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 457; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 458; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 459; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 460; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 461 462 %1 = fcmp une <8 x half> %a, %b 463 ret <8 x i1> %1 464} 465 466define <8 x i1> @test_fcmp_ueq(<8 x half> %a, <8 x half> %b) #0 { 467; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 468 469; CHECK-FP16-LABEL: test_fcmp_ueq: 470; CHECK-FP16-NOT: fcvt 471; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 472; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 473; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 474; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 475; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 476; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 477; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 478; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 479 480 %1 = fcmp ueq <8 x half> %a, %b 481 ret <8 x i1> %1 482} 483 484define <8 x i1> @test_fcmp_ugt(<8 x half> %a, <8 x half> %b) #0 { 485; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 486 487; CHECK-FP16-LABEL: test_fcmp_ugt: 488; CHECK-FP16-NOT: fcvt 489; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 490; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 491; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 492; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 493; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 494; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 495; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 496; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 497 498 %1 = fcmp ugt <8 x half> %a, %b 499 ret <8 x i1> %1 500} 501 502define <8 x i1> @test_fcmp_uge(<8 x half> %a, <8 x half> %b) #0 { 503; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 504 505; CHECK-FP16-LABEL: test_fcmp_uge: 506; CHECK-FP16-NOT: fcvt 507; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 508; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 509; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 510; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 511; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 512; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 513; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 514; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 515 516 %1 = fcmp uge <8 x half> %a, %b 517 ret <8 x i1> %1 518} 519 520define <8 x i1> @test_fcmp_ult(<8 x half> %a, <8 x half> %b) #0 { 521; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 522 523; CHECK-FP16-LABEL: test_fcmp_ult: 524; CHECK-FP16-NOT: fcvt 525; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 526; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 527; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 528; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 529; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 530; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 531; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 532; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 533 534 %1 = fcmp ult <8 x half> %a, %b 535 ret <8 x i1> %1 536} 537 538define <8 x i1> @test_fcmp_ule(<8 x half> %a, <8 x half> %b) #0 { 539; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 540 541; CHECK-FP16-LABEL: test_fcmp_ule: 542; CHECK-FP16-NOT: fcvt 543; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 544; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 545; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 546; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 547; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 548; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 549; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 550; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 551 552 %1 = fcmp ule <8 x half> %a, %b 553 ret <8 x i1> %1 554} 555 556define <8 x i1> @test_fcmp_uno(<8 x half> %a, <8 x half> %b) #0 { 557; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 558 559; CHECK-FP16-LABEL: test_fcmp_uno: 560; CHECK-FP16-NOT: fcvt 561; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 562; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 563; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 564; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 565; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 566; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 567; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 568; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 569 570 %1 = fcmp uno <8 x half> %a, %b 571 ret <8 x i1> %1 572} 573 574define <8 x i1> @test_fcmp_one(<8 x half> %a, <8 x half> %b) #0 { 575; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 576 577; CHECK-FP16-LABEL: test_fcmp_one: 578; CHECK-FP16-NOT: fcvt 579; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 580; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 581; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 582; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 583; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 584; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 585; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 586; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 587 588 %1 = fcmp one <8 x half> %a, %b 589 ret <8 x i1> %1 590} 591 592define <8 x i1> @test_fcmp_oeq(<8 x half> %a, <8 x half> %b) #0 { 593; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 594 595; CHECK-FP16-LABEL: test_fcmp_oeq: 596; CHECK-FP16-NOT: fcvt 597; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 598; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 599; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 600; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 601; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 602; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 603; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 604; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 605 606 %1 = fcmp oeq <8 x half> %a, %b 607 ret <8 x i1> %1 608} 609 610define <8 x i1> @test_fcmp_ogt(<8 x half> %a, <8 x half> %b) #0 { 611; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 612 613; CHECK-FP16-LABEL: test_fcmp_ogt: 614; CHECK-FP16-NOT: fcvt 615; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 616; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 617; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 618; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 619; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 620; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 621; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 622; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 623 624 %1 = fcmp ogt <8 x half> %a, %b 625 ret <8 x i1> %1 626} 627 628define <8 x i1> @test_fcmp_oge(<8 x half> %a, <8 x half> %b) #0 { 629; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 630 631; CHECK-FP16-LABEL: test_fcmp_oge: 632; CHECK-FP16-NOT: fcvt 633; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 634; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 635; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 636; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 637; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 638; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 639; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 640; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 641 642 %1 = fcmp oge <8 x half> %a, %b 643 ret <8 x i1> %1 644} 645 646define <8 x i1> @test_fcmp_olt(<8 x half> %a, <8 x half> %b) #0 { 647; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 648 649; CHECK-FP16-LABEL: test_fcmp_olt: 650; CHECK-FP16-NOT: fcvt 651; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 652; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 653; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 654; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 655; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 656; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 657; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 658; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 659 660 %1 = fcmp olt <8 x half> %a, %b 661 ret <8 x i1> %1 662} 663 664define <8 x i1> @test_fcmp_ole(<8 x half> %a, <8 x half> %b) #0 { 665; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 666 667; CHECK-FP16-LABEL: test_fcmp_ole: 668; CHECK-FP16-NOT: fcvt 669; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 670; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 671; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 672; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 673; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 674; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 675; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 676; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 677 678 %1 = fcmp ole <8 x half> %a, %b 679 ret <8 x i1> %1 680} 681 682define <8 x i1> @test_fcmp_ord(<8 x half> %a, <8 x half> %b) #0 { 683; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 684 685; CHECK-FP16-LABEL: test_fcmp_ord: 686; CHECK-FP16-NOT: fcvt 687; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 688; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 689; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 690; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 691; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 692; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 693; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 694; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} 695 696 %1 = fcmp ord <8 x half> %a, %b 697 ret <8 x i1> %1 698} 699 700attributes #0 = { nounwind } 701