1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s 2 3; The branch instruction in LOOP49 has a uniform condition, but PHI instructions 4; introduced by the structurizecfg pass previously caused a false divergence 5; which ended up in an assertion (or incorrect code) because 6; SIAnnotateControlFlow and structurizecfg had different ideas about which 7; branches are uniform. 8; 9; CHECK-LABEL: {{^}}main: 10; CHECK: ; %LOOP49 11; CHECK: v_cmp_ne_u32_e32 vcc, 12; CHECK: s_cbranch_vccnz 13; CHECK: ; %ENDIF53 14define amdgpu_vs float @main(i32 %in) { 15main_body: 16 %cmp = mul i32 %in, 2 17 br label %LOOP 18 19LOOP: ; preds = %ENDLOOP48, %main_body 20 %counter = phi i32 [ 0, %main_body ], [ %counter.next, %ENDLOOP48 ] 21 %v.LOOP = phi i32 [ 0, %main_body ], [ %v.ENDLOOP48, %ENDLOOP48 ] 22 %tmp7 = icmp slt i32 %cmp, %counter 23 br i1 %tmp7, label %IF, label %LOOP49 24 25IF: ; preds = %LOOP 26 %r = bitcast i32 %v.LOOP to float 27 ret float %r 28 29LOOP49: ; preds = %LOOP 30 %tmp8 = icmp ne i32 %counter, 0 31 br i1 %tmp8, label %ENDLOOP48, label %ENDIF53 32 33ENDLOOP48: ; preds = %ENDIF53, %LOOP49 34 %v.ENDLOOP48 = phi i32 [ %v.LOOP, %LOOP49 ], [ %v.ENDIF53, %ENDIF53 ] 35 %counter.next = add i32 %counter, 1 36 br label %LOOP 37 38ENDIF53: ; preds = %LOOP49 39 %v.ENDIF53 = add i32 %v.LOOP, %counter 40 br label %ENDLOOP48 41} 42