1; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 4; GCN-LABEL: {{^}}fptoui_f16_to_i16 5; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 6; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 7; SI: v_cvt_u32_f32_e32 v[[R_I16:[0-9]+]], v[[A_F32]] 8; VI: v_cvt_i32_f32_e32 v[[R_I16:[0-9]+]], v[[A_F32]] 9; GCN: buffer_store_short v[[R_I16]] 10; GCN: s_endpgm 11define amdgpu_kernel void @fptoui_f16_to_i16( 12 i16 addrspace(1)* %r, 13 half addrspace(1)* %a) { 14entry: 15 %a.val = load half, half addrspace(1)* %a 16 %r.val = fptoui half %a.val to i16 17 store i16 %r.val, i16 addrspace(1)* %r 18 ret void 19} 20 21; GCN-LABEL: {{^}}fptoui_f16_to_i32 22; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 23; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 24; GCN: v_cvt_u32_f32_e32 v[[R_I32:[0-9]+]], v[[A_F32]] 25; GCN: buffer_store_dword v[[R_I32]] 26; GCN: s_endpgm 27define amdgpu_kernel void @fptoui_f16_to_i32( 28 i32 addrspace(1)* %r, 29 half addrspace(1)* %a) { 30entry: 31 %a.val = load half, half addrspace(1)* %a 32 %r.val = fptoui half %a.val to i32 33 store i32 %r.val, i32 addrspace(1)* %r 34 ret void 35} 36 37; Need to make sure we promote f16 to f32 when converting f16 to i64. Existing 38; test checks code generated for 'i64 = fp_to_uint f32'. 39 40; GCN-LABEL: {{^}}fptoui_f16_to_i64 41; GCN: buffer_load_ushort 42; GCN: v_cvt_f32_f16_e32 43; GCN: s_endpgm 44define amdgpu_kernel void @fptoui_f16_to_i64( 45 i64 addrspace(1)* %r, 46 half addrspace(1)* %a) { 47entry: 48 %a.val = load half, half addrspace(1)* %a 49 %r.val = fptoui half %a.val to i64 50 store i64 %r.val, i64 addrspace(1)* %r 51 ret void 52} 53 54; GCN-LABEL: {{^}}fptoui_v2f16_to_v2i16 55; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]] 56 57; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] 58; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] 59; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] 60; SI: v_cvt_u32_f32_e32 v[[R_I16_1:[0-9]+]], v[[A_F32_1]] 61; SI: v_cvt_u32_f32_e32 v[[R_I16_0:[0-9]+]], v[[A_F32_0]] 62; SI: v_lshlrev_b32_e32 v[[R_I16_HI:[0-9]+]], 16, v[[R_I16_1]] 63; SI: v_or_b32_e32 v[[R_V2_I16:[0-9]+]], v[[R_I16_0]], v[[R_I16_HI]] 64 65; VI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_V2_F16]] 66; VI-DAG: v_cvt_f32_f16_sdwa v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 67; VI: v_cvt_i32_f32_e32 v[[R_I16_1:[0-9]+]], v[[A_F32_1]] 68; VI: v_cvt_i32_f32_sdwa v[[R_I16_0:[0-9]+]], v[[A_F32_0]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 69; VI: v_or_b32_sdwa v[[R_V2_I16:[0-9]+]], v[[R_I16_1]], v[[R_I16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 70 71; GCN: buffer_store_dword v[[R_V2_I16]] 72; GCN: s_endpgm 73 74define amdgpu_kernel void @fptoui_v2f16_to_v2i16( 75 <2 x i16> addrspace(1)* %r, 76 <2 x half> addrspace(1)* %a) { 77entry: 78 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 79 %r.val = fptoui <2 x half> %a.val to <2 x i16> 80 store <2 x i16> %r.val, <2 x i16> addrspace(1)* %r 81 ret void 82} 83 84; GCN-LABEL: {{^}}fptoui_v2f16_to_v2i32 85; GCN: buffer_load_dword 86; GCN: v_cvt_f32_f16_e32 87; SI: v_cvt_f32_f16_e32 88; VI: v_cvt_f32_f16_sdwa 89; GCN: v_cvt_u32_f32_e32 90; GCN: v_cvt_u32_f32_e32 91; GCN: buffer_store_dwordx2 92; GCN: s_endpgm 93define amdgpu_kernel void @fptoui_v2f16_to_v2i32( 94 <2 x i32> addrspace(1)* %r, 95 <2 x half> addrspace(1)* %a) { 96entry: 97 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 98 %r.val = fptoui <2 x half> %a.val to <2 x i32> 99 store <2 x i32> %r.val, <2 x i32> addrspace(1)* %r 100 ret void 101} 102 103; Need to make sure we promote f16 to f32 when converting f16 to i64. Existing 104; test checks code generated for 'i64 = fp_to_uint f32'. 105 106; GCN-LABEL: {{^}}fptoui_v2f16_to_v2i64 107; GCN: buffer_load_dword 108; GCN: v_cvt_f32_f16_e32 109; SI: v_cvt_f32_f16_e32 110; VI: v_cvt_f32_f16_sdwa 111; GCN: s_endpgm 112define amdgpu_kernel void @fptoui_v2f16_to_v2i64( 113 <2 x i64> addrspace(1)* %r, 114 <2 x half> addrspace(1)* %a) { 115entry: 116 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 117 %r.val = fptoui <2 x half> %a.val to <2 x i64> 118 store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r 119 ret void 120} 121