1; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=SI --check-prefix=FUNC %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=SI --check-prefix=FUNC %s 3; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=EG --check-prefix=FUNC %s 4 5; FUNC-LABEL: {{^}}test_udivrem: 6; EG: RECIP_UINT 7; EG-DAG: MULHI 8; EG-DAG: MULLO_INT 9; EG-DAG: SUB_INT 10; EG: CNDE_INT 11; EG: MULHI 12; EG-DAG: ADD_INT 13; EG-DAG: SUB_INT 14; EG: CNDE_INT 15; EG: MULHI 16; EG: MULLO_INT 17; EG: SUB_INT 18; EG-DAG: SETGE_UINT 19; EG-DAG: SETGE_UINT 20; EG: AND_INT 21; EG-DAG: ADD_INT 22; EG-DAG: SUB_INT 23; EG-DAG: CNDE_INT 24; EG-DAG: CNDE_INT 25; EG-DAG: ADD_INT 26; EG-DAG: SUB_INT 27; EG-DAG: CNDE_INT 28; EG-DAG: CNDE_INT 29 30; SI: v_rcp_iflag_f32_e32 [[RCP:v[0-9]+]] 31; SI-DAG: v_mul_hi_u32 [[RCP_HI:v[0-9]+]], [[RCP]] 32; SI-DAG: v_mul_lo_i32 [[RCP_LO:v[0-9]+]], [[RCP]] 33; SI-DAG: v_sub_{{[iu]}}32_e32 [[NEG_RCP_LO:v[0-9]+]], vcc, 0, [[RCP_LO]] 34; SI: v_cmp_eq_u32_e64 [[CC1:s\[[0-9:]+\]]], 0, [[RCP_HI]] 35; SI: v_cndmask_b32_e64 [[CND1:v[0-9]+]], [[RCP_LO]], [[NEG_RCP_LO]], [[CC1]] 36; SI: v_mul_hi_u32 [[E:v[0-9]+]], [[CND1]], [[RCP]] 37; SI-DAG: v_add_{{[iu]}}32_e32 [[RCP_A_E:v[0-9]+]], vcc, [[E]], [[RCP]] 38; SI-DAG: v_subrev_{{[iu]}}32_e32 [[RCP_S_E:v[0-9]+]], vcc, [[E]], [[RCP]] 39; SI: v_cndmask_b32_e64 [[CND2:v[0-9]+]], [[RCP_S_E]], [[RCP_A_E]], [[CC1]] 40; SI: v_mul_hi_u32 [[Quotient:v[0-9]+]], [[CND2]], 41; SI: v_mul_lo_i32 [[Num_S_Remainder:v[0-9]+]], [[CND2]] 42; SI-DAG: v_add_{{[iu]}}32_e32 [[Quotient_A_One:v[0-9]+]], vcc, 1, [[Quotient]] 43; SI-DAG: v_sub_{{[iu]}}32_e32 [[Remainder:v[0-9]+]], vcc, {{[vs][0-9]+}}, [[Num_S_Remainder]] 44; SI-DAG: v_cndmask_b32_e64 45; SI-DAG: v_subrev_{{[iu]}}32_e32 [[Quotient_S_One:v[0-9]+]], 46; SI-DAG: v_subrev_{{[iu]}}32_e32 [[Remainder_S_Den:v[0-9]+]], 47; SI-DAG: v_cndmask_b32_e64 48; SI-DAG: v_cndmask_b32_e64 49; SI-DAG: v_add_{{[iu]}}32_e32 [[Remainder_A_Den:v[0-9]+]], 50; SI-DAG: v_cndmask_b32_e64 51; SI-DAG: v_cndmask_b32_e64 52; SI-NOT: v_and_b32 53; SI: s_endpgm 54define amdgpu_kernel void @test_udivrem(i32 addrspace(1)* %out0, [8 x i32], i32 addrspace(1)* %out1, [8 x i32], i32 %x, [8 x i32], i32 %y) { 55 %result0 = udiv i32 %x, %y 56 store i32 %result0, i32 addrspace(1)* %out0 57 %result1 = urem i32 %x, %y 58 store i32 %result1, i32 addrspace(1)* %out1 59 ret void 60} 61 62; FUNC-LABEL: {{^}}test_udivrem_v2: 63; EG-DAG: RECIP_UINT 64; EG-DAG: MULHI 65; EG-DAG: MULLO_INT 66; EG-DAG: SUB_INT 67; EG-DAG: CNDE_INT 68; EG-DAG: MULHI 69; EG-DAG: ADD_INT 70; EG-DAG: SUB_INT 71; EG-DAG: CNDE_INT 72; EG-DAG: MULHI 73; EG-DAG: MULLO_INT 74; EG-DAG: SUB_INT 75; EG-DAG: SETGE_UINT 76; EG-DAG: SETGE_UINT 77; EG-DAG: AND_INT 78; EG-DAG: ADD_INT 79; EG-DAG: SUB_INT 80; EG-DAG: CNDE_INT 81; EG-DAG: CNDE_INT 82; EG-DAG: ADD_INT 83; EG-DAG: SUB_INT 84; EG-DAG: CNDE_INT 85; EG-DAG: CNDE_INT 86; EG-DAG: RECIP_UINT 87; EG-DAG: MULHI 88; EG-DAG: MULLO_INT 89; EG-DAG: SUB_INT 90; EG-DAG: CNDE_INT 91; EG-DAG: MULHI 92; EG-DAG: ADD_INT 93; EG-DAG: SUB_INT 94; EG-DAG: CNDE_INT 95; EG-DAG: MULHI 96; EG-DAG: MULLO_INT 97; EG-DAG: SUB_INT 98; EG-DAG: SETGE_UINT 99; EG-DAG: SETGE_UINT 100; EG-DAG: AND_INT 101; EG-DAG: ADD_INT 102; EG-DAG: SUB_INT 103; EG-DAG: CNDE_INT 104; EG-DAG: CNDE_INT 105; EG-DAG: ADD_INT 106; EG-DAG: SUB_INT 107; EG-DAG: CNDE_INT 108; EG-DAG: CNDE_INT 109 110; For SI, we used to have checks for the input and output registers 111; of the instructions, but these are way too fragile. The division for 112; the two vector elements can be intermixed which makes it impossible to 113; accurately check all the operands. 114; SI-DAG: v_rcp_iflag_f32_e32 115; SI-DAG: v_mul_hi_u32 116; SI-DAG: v_mul_lo_i32 117; SI-DAG: v_sub_{{[iu]}}32_e32 118; SI-DAG: v_cndmask_b32_e64 119; SI-DAG: v_mul_hi_u32 120; SI-DAG: v_add_{{[iu]}}32_e32 121; SI-DAG: v_subrev_{{[iu]}}32_e32 122; SI-DAG: v_cndmask_b32_e64 123; SI-DAG: v_mul_hi_u32 124; SI-DAG: v_mul_lo_i32 125; SI-DAG: v_subrev_{{[iu]}}32_e32 126; SI-DAG: v_cndmask_b32_e64 127; SI-DAG: v_add_{{[iu]}}32_e32 128; SI-DAG: v_subrev_{{[iu]}}32_e32 129; SI-DAG: v_cndmask_b32_e64 130; SI-DAG: v_cndmask_b32_e64 131; SI-DAG: v_add_{{[iu]}}32_e32 132; SI-DAG: v_subrev_{{[iu]}}32_e32 133; SI-DAG: v_cndmask_b32_e64 134; SI-DAG: v_cndmask_b32_e64 135; SI-DAG: v_rcp_iflag_f32_e32 136; SI-DAG: v_mul_hi_u32 137; SI-DAG: v_mul_lo_i32 138; SI-DAG: v_sub_{{[iu]}}32_e32 139; SI-DAG: v_cndmask_b32_e64 140; SI-DAG: v_mul_hi_u32 141; SI-DAG: v_add_{{[iu]}}32_e32 142; SI-DAG: v_subrev_{{[iu]}}32_e32 143; SI-DAG: v_cndmask_b32_e64 144; SI-DAG: v_mul_hi_u32 145; SI-DAG: v_mul_lo_i32 146; SI-DAG: v_subrev_{{[iu]}}32_e32 147; SI-DAG: v_cndmask_b32_e64 148; SI-DAG: v_add_{{[iu]}}32_e32 149; SI-DAG: v_subrev_{{[iu]}}32_e32 150; SI-DAG: v_cndmask_b32_e64 151; SI-DAG: v_cndmask_b32_e64 152; SI-DAG: v_add_{{[iu]}}32_e32 153; SI-DAG: v_subrev_{{[iu]}}32_e32 154; SI-DAG: v_cndmask_b32_e64 155; SI-DAG: v_cndmask_b32_e64 156; SI-NOT: v_and_b32 157; SI: s_endpgm 158define amdgpu_kernel void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) { 159 %result0 = udiv <2 x i32> %x, %y 160 store <2 x i32> %result0, <2 x i32> addrspace(1)* %out 161 %result1 = urem <2 x i32> %x, %y 162 store <2 x i32> %result1, <2 x i32> addrspace(1)* %out 163 ret void 164} 165 166 167; FUNC-LABEL: {{^}}test_udivrem_v4: 168; EG-DAG: RECIP_UINT 169; EG-DAG: MULHI 170; EG-DAG: MULLO_INT 171; EG-DAG: SUB_INT 172; EG-DAG: CNDE_INT 173; EG-DAG: MULHI 174; EG-DAG: ADD_INT 175; EG-DAG: SUB_INT 176; EG-DAG: CNDE_INT 177; EG-DAG: MULHI 178; EG-DAG: MULLO_INT 179; EG-DAG: SUB_INT 180; EG-DAG: SETGE_UINT 181; EG-DAG: SETGE_UINT 182; EG-DAG: AND_INT 183; EG-DAG: ADD_INT 184; EG-DAG: SUB_INT 185; EG-DAG: CNDE_INT 186; EG-DAG: CNDE_INT 187; EG-DAG: ADD_INT 188; EG-DAG: SUB_INT 189; EG-DAG: CNDE_INT 190; EG-DAG: CNDE_INT 191; EG-DAG: RECIP_UINT 192; EG-DAG: MULHI 193; EG-DAG: MULLO_INT 194; EG-DAG: SUB_INT 195; EG-DAG: CNDE_INT 196; EG-DAG: MULHI 197; EG-DAG: ADD_INT 198; EG-DAG: SUB_INT 199; EG-DAG: CNDE_INT 200; EG-DAG: MULHI 201; EG-DAG: MULLO_INT 202; EG-DAG: SUB_INT 203; EG-DAG: SETGE_UINT 204; EG-DAG: SETGE_UINT 205; EG-DAG: AND_INT 206; EG-DAG: ADD_INT 207; EG-DAG: SUB_INT 208; EG-DAG: CNDE_INT 209; EG-DAG: CNDE_INT 210; EG-DAG: ADD_INT 211; EG-DAG: SUB_INT 212; EG-DAG: CNDE_INT 213; EG-DAG: CNDE_INT 214; EG-DAG: RECIP_UINT 215; EG-DAG: MULHI 216; EG-DAG: MULLO_INT 217; EG-DAG: SUB_INT 218; EG-DAG: CNDE_INT 219; EG-DAG: MULHI 220; EG-DAG: ADD_INT 221; EG-DAG: SUB_INT 222; EG-DAG: CNDE_INT 223; EG-DAG: MULHI 224; EG-DAG: MULLO_INT 225; EG-DAG: SUB_INT 226; EG-DAG: SETGE_UINT 227; EG-DAG: SETGE_UINT 228; EG-DAG: AND_INT 229; EG-DAG: ADD_INT 230; EG-DAG: SUB_INT 231; EG-DAG: CNDE_INT 232; EG-DAG: CNDE_INT 233; EG-DAG: ADD_INT 234; EG-DAG: SUB_INT 235; EG-DAG: CNDE_INT 236; EG-DAG: CNDE_INT 237; EG-DAG: RECIP_UINT 238; EG-DAG: MULHI 239; EG-DAG: MULLO_INT 240; EG-DAG: SUB_INT 241; EG-DAG: CNDE_INT 242; EG-DAG: MULHI 243; EG-DAG: ADD_INT 244; EG-DAG: SUB_INT 245; EG-DAG: CNDE_INT 246; EG-DAG: MULHI 247; EG-DAG: MULLO_INT 248; EG-DAG: SUB_INT 249; EG-DAG: SETGE_UINT 250; EG-DAG: SETGE_UINT 251; EG-DAG: AND_INT 252; EG-DAG: ADD_INT 253; EG-DAG: SUB_INT 254; EG-DAG: CNDE_INT 255; EG-DAG: CNDE_INT 256; EG-DAG: ADD_INT 257; EG-DAG: SUB_INT 258; EG-DAG: CNDE_INT 259; EG-DAG: CNDE_INT 260 261; SI-DAG: v_rcp_iflag_f32_e32 262; SI-DAG: v_mul_hi_u32 263; SI-DAG: v_mul_lo_i32 264; SI-DAG: v_sub_{{[iu]}}32_e32 265; SI-DAG: v_cndmask_b32_e64 266; SI-DAG: v_mul_hi_u32 267; SI-DAG: v_add_{{[iu]}}32_e32 268; SI-DAG: v_subrev_{{[iu]}}32_e32 269; SI-DAG: v_cndmask_b32_e64 270; SI-DAG: v_mul_hi_u32 271; SI-DAG: v_mul_lo_i32 272; SI-DAG: v_subrev_{{[iu]}}32_e32 273; SI-DAG: v_cndmask_b32_e64 274; SI-DAG: v_add_{{[iu]}}32_e32 275; SI-DAG: v_subrev_{{[iu]}}32_e32 276; SI-DAG: v_cndmask_b32_e64 277; SI-DAG: v_cndmask_b32_e64 278; SI-DAG: v_add_{{[iu]}}32_e32 279; SI-DAG: v_subrev_{{[iu]}}32_e32 280; SI-DAG: v_cndmask_b32_e64 281; SI-DAG: v_cndmask_b32_e64 282; SI-DAG: v_rcp_iflag_f32_e32 283; SI-DAG: v_mul_hi_u32 284; SI-DAG: v_mul_lo_i32 285; SI-DAG: v_sub_{{[iu]}}32_e32 286; SI-DAG: v_cndmask_b32_e64 287; SI-DAG: v_mul_hi_u32 288; SI-DAG: v_add_{{[iu]}}32_e32 289; SI-DAG: v_subrev_{{[iu]}}32_e32 290; SI-DAG: v_cndmask_b32_e64 291; SI-DAG: v_mul_hi_u32 292; SI-DAG: v_mul_lo_i32 293; SI-DAG: v_subrev_{{[iu]}}32_e32 294; SI-DAG: v_cndmask_b32_e64 295; SI-DAG: v_add_{{[iu]}}32_e32 296; SI-DAG: v_subrev_{{[iu]}}32_e32 297; SI-DAG: v_cndmask_b32_e64 298; SI-DAG: v_cndmask_b32_e64 299; SI-DAG: v_add_{{[iu]}}32_e32 300; SI-DAG: v_subrev_{{[iu]}}32_e32 301; SI-DAG: v_cndmask_b32_e64 302; SI-DAG: v_cndmask_b32_e64 303; SI-DAG: v_rcp_iflag_f32_e32 304; SI-DAG: v_mul_hi_u32 305; SI-DAG: v_mul_lo_i32 306; SI-DAG: v_sub_{{[iu]}}32_e32 307; SI-DAG: v_cndmask_b32_e64 308; SI-DAG: v_mul_hi_u32 309; SI-DAG: v_add_{{[iu]}}32_e32 310; SI-DAG: v_subrev_{{[iu]}}32_e32 311; SI-DAG: v_cndmask_b32_e64 312; SI-DAG: v_mul_hi_u32 313; SI-DAG: v_mul_lo_i32 314; SI-DAG: v_subrev_{{[iu]}}32_e32 315; SI-DAG: v_cndmask_b32_e64 316; SI-DAG: v_add_{{[iu]}}32_e32 317; SI-DAG: v_subrev_{{[iu]}}32_e32 318; SI-DAG: v_cndmask_b32_e64 319; SI-DAG: v_cndmask_b32_e64 320; SI-DAG: v_add_{{[iu]}}32_e32 321; SI-DAG: v_subrev_{{[iu]}}32_e32 322; SI-DAG: v_cndmask_b32_e64 323; SI-DAG: v_cndmask_b32_e64 324; SI-DAG: v_rcp_iflag_f32_e32 325; SI-DAG: v_mul_hi_u32 326; SI-DAG: v_mul_lo_i32 327; SI-DAG: v_sub_{{[iu]}}32_e32 328; SI-DAG: v_cndmask_b32_e64 329; SI-DAG: v_mul_hi_u32 330; SI-DAG: v_add_{{[iu]}}32_e32 331; SI-DAG: v_subrev_{{[iu]}}32_e32 332; SI-DAG: v_cndmask_b32_e64 333; SI-NOT: v_and_b32 334; SI: s_endpgm 335define amdgpu_kernel void @test_udivrem_v4(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) { 336 %result0 = udiv <4 x i32> %x, %y 337 store <4 x i32> %result0, <4 x i32> addrspace(1)* %out 338 %result1 = urem <4 x i32> %x, %y 339 store <4 x i32> %result1, <4 x i32> addrspace(1)* %out 340 ret void 341} 342