1; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefix=ARM 2 3; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \ 4; RUN: | FileCheck %s --check-prefix=ARMT2 5 6; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 %s -o - \ 7; RUN: | FileCheck %s --check-prefix=THUMB1 8 9; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \ 10; RUN: | FileCheck %s --check-prefix=THUMB2 11 12; RUN: llc -mtriple=thumbv8m.base-eabi %s -o - \ 13; RUN: | FileCheck %s --check-prefix=V8MBASE 14 15define i32 @t1(i32 %c) nounwind readnone { 16entry: 17; ARM-LABEL: t1: 18; ARM: mov [[R1:r[0-9]+]], #101 19; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256 20; ARM: movgt {{r[0-1]}}, #123 21 22; ARMT2-LABEL: t1: 23; ARMT2: movw [[R:r[0-1]]], #357 24; ARMT2: movwgt [[R]], #123 25 26; THUMB1-LABEL: t1: 27; THUMB1: mov r1, r0 28; THUMB1: movs r2, #255 29; THUMB1: adds r2, #102 30; THUMB1: movs r0, #123 31; THUMB1: cmp r1, #1 32; THUMB1: bgt 33 34; THUMB2-LABEL: t1: 35; THUMB2: movw [[R:r[0-1]]], #357 36; THUMB2: movgt [[R]], #123 37 38 %0 = icmp sgt i32 %c, 1 39 %1 = select i1 %0, i32 123, i32 357 40 ret i32 %1 41} 42 43define i32 @t2(i32 %c) nounwind readnone { 44entry: 45; ARM-LABEL: t2: 46; ARM: mov [[R:r[0-9]+]], #101 47; ARM: orr [[R]], [[R]], #256 48; ARM: movle [[R]], #123 49 50; ARMT2-LABEL: t2: 51; ARMT2: mov [[R:r[0-1]]], #123 52; ARMT2: movwgt [[R]], #357 53 54; THUMB1-LABEL: t2: 55; THUMB1: cmp r{{[0-9]+}}, #1 56; THUMB1: bgt 57 58; THUMB2-LABEL: t2: 59; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #123 60; THUMB2: movwgt [[R]], #357 61 62 %0 = icmp sgt i32 %c, 1 63 %1 = select i1 %0, i32 357, i32 123 64 ret i32 %1 65} 66 67define i32 @t3(i32 %a) nounwind readnone { 68entry: 69; ARM-LABEL: t3: 70; ARM: rsbs r1, r0, #0 71; ARM: adc r0, r0, r1 72 73; ARMT2-LABEL: t3: 74; ARMT2: clz r0, r0 75; ARMT2: lsr r0, r0, #5 76 77; THUMB1-LABEL: t3: 78; THUMB1: movs r1, #0 79; THUMB1: subs r1, r1, r0 80; THUMB1: adcs r0, r1 81 82; THUMB2-LABEL: t3: 83; THUMB2: clz r0, r0 84; THUMB2: lsrs r0, r0, #5 85 %0 = icmp eq i32 %a, 160 86 %1 = zext i1 %0 to i32 87 ret i32 %1 88} 89 90define i32 @t4(i32 %a, i32 %b, i32 %x) nounwind { 91entry: 92; ARM-LABEL: t4: 93; ARM: ldr 94; ARM: mov{{lt|ge}} 95 96; ARMT2-LABEL: t4: 97; ARMT2: movwlt [[R0:r[0-9]+]], #65365 98; ARMT2: movtlt [[R0]], #65365 99 100; THUMB1-LABEL: t4: 101; THUMB1: cmp r{{[0-9]+}}, r{{[0-9]+}} 102; THUMB1: b{{lt|ge}} 103 104; THUMB2-LABEL: t4: 105; THUMB2: mvnlt [[R0:r[0-9]+]], #11141290 106 %0 = icmp slt i32 %a, %b 107 %1 = select i1 %0, i32 4283826005, i32 %x 108 ret i32 %1 109} 110 111; rdar://9758317 112define i32 @t5(i32 %a) nounwind { 113entry: 114; ARM-LABEL: t5: 115; ARM-NOT: mov 116; ARM: sub r0, r0, #1 117; ARM-NOT: mov 118; ARM: rsbs r1, r0, #0 119; ARM: adc r0, r0, r1 120 121; THUMB1-LABEL: t5: 122; THUMB1-NOT: bne 123; THUMB1: movs r0, #0 124; THUMB1: subs r0, r0, r1 125; THUMB1: adcs r0, r1 126 127; THUMB2-LABEL: t5: 128; THUMB2-NOT: mov 129; THUMB2: subs r0, #1 130; THUMB2: clz r0, r0 131; THUMB2: lsrs r0, r0, #5 132 133 %cmp = icmp eq i32 %a, 1 134 %conv = zext i1 %cmp to i32 135 ret i32 %conv 136} 137 138define i32 @t6(i32 %a) nounwind { 139entry: 140; ARM-LABEL: t6: 141; ARM-NOT: mov 142; ARM: cmp r0, #0 143; ARM: movne r0, #1 144 145; THUMB1-LABEL: t6: 146; THUMB1: cmp r{{[0-9]+}}, #0 147; THUMB1: bne 148 149; THUMB2-LABEL: t6: 150; THUMB2-NOT: mov 151; THUMB2: cmp r0, #0 152; THUMB2: it ne 153; THUMB2: movne r0, #1 154 %tobool = icmp ne i32 %a, 0 155 %lnot.ext = zext i1 %tobool to i32 156 ret i32 %lnot.ext 157} 158 159define i32 @t7(i32 %a, i32 %b) nounwind readnone { 160entry: 161; ARM-LABEL: t7: 162; ARM: subs r0, r0, r1 163; ARM: movne r0, #1 164; ARM: lsl r0, r0, #2 165 166; ARMT2-LABEL: t7: 167; ARMT2: subs r0, r0, r1 168; ARMT2: movwne r0, #1 169; ARMT2: lsl r0, r0, #2 170 171; THUMB1-LABEL: t7: 172; THUMB1: subs r0, r0, r1 173; THUMB1: subs r1, r0, #1 174; THUMB1: sbcs r0, r1 175; THUMB1: lsls r0, r0, #2 176 177; THUMB2-LABEL: t7: 178; THUMB2: subs r0, r0, r1 179; THUMB2: it ne 180; THUMB2: movne r0, #1 181; THUMB2: lsls r0, r0, #2 182 %0 = icmp ne i32 %a, %b 183 %1 = select i1 %0, i32 4, i32 0 184 ret i32 %1 185} 186 187define void @t8(i32 %a) { 188entry: 189 190; ARM scheduler emits icmp/zext before both calls, so isn't relevant 191 192; ARMT2-LABEL: t8: 193; ARMT2: bl t7 194; ARMT2: mov r1, r0 195; ARMT2: sub r0, r4, #5 196; ARMT2: clz r0, r0 197; ARMT2: lsr r0, r0, #5 198 199; THUMB1-LABEL: t8: 200; THUMB1: bl t7 201; THUMB1: mov r1, r0 202; THUMB1: subs r2, r4, #5 203; THUMB1: movs r0, #0 204; THUMB1: subs r0, r0, r2 205; THUMB1: adcs r0, r2 206 207; THUMB2-LABEL: t8: 208; THUMB2: bl t7 209; THUMB2: mov r1, r0 210; THUMB2: subs r0, r4, #5 211; THUMB2: clz r0, r0 212; THUMB2: lsrs r0, r0, #5 213 214 %cmp = icmp eq i32 %a, 5 215 %conv = zext i1 %cmp to i32 216 %call = tail call i32 @t7(i32 9, i32 %a) 217 tail call i32 @t7(i32 %conv, i32 %call) 218 ret void 219} 220 221define void @t9(i8* %a, i8 %b) { 222entry: 223 224; ARM scheduler emits icmp/zext before both calls, so isn't relevant 225 226; ARMT2-LABEL: t9: 227; ARMT2: bl f 228; ARMT2: uxtb r0, r4 229; ARMT2: cmp r0, r0 230; ARMT2: add r1, r4, #1 231; ARMT2: mov r2, r0 232; ARMT2: add r2, r2, #1 233; ARMT2: add r1, r1, #1 234; ARMT2: uxtb r3, r2 235; ARMT2: cmp r3, r0 236 237; THUMB1-LABEL: t9: 238; THUMB1: bl f 239; THUMB1: sxtb r1, r4 240; THUMB1: uxtb r0, r1 241; THUMB1: cmp r0, r0 242; THUMB1: adds r1, r1, #1 243; THUMB1: mov r2, r0 244; THUMB1: adds r1, r1, #1 245; THUMB1: adds r2, r2, #1 246; THUMB1: uxtb r3, r2 247; THUMB1: cmp r3, r0 248 249; THUMB2-LABEL: t9: 250; THUMB2: bl f 251; THUMB2: uxtb r0, r4 252; THUMB2: cmp r0, r0 253; THUMB2: adds r1, r4, #1 254; THUMB2: mov r2, r0 255; THUMB2: adds r2, #1 256; THUMB2: adds r1, #1 257; THUMB2: uxtb r3, r2 258; THUMB2: cmp r3, r0 259 260 %0 = load i8, i8* %a 261 %conv = sext i8 %0 to i32 262 %conv119 = zext i8 %0 to i32 263 %conv522 = and i32 %conv, 255 264 %cmp723 = icmp eq i32 %conv522, %conv119 265 tail call void @f(i1 zeroext %cmp723) 266 br i1 %cmp723, label %while.body, label %while.end 267 268while.body: ; preds = %entry, %while.body 269 %ref.025 = phi i8 [ %inc9, %while.body ], [ %0, %entry ] 270 %in.024 = phi i32 [ %inc, %while.body ], [ %conv, %entry ] 271 %inc = add i32 %in.024, 1 272 %inc9 = add i8 %ref.025, 1 273 %conv1 = zext i8 %inc9 to i32 274 %cmp = icmp slt i32 %conv1, %conv119 275 %conv5 = and i32 %inc, 255 276 br i1 %cmp, label %while.body, label %while.end 277 278while.end: 279 ret void 280} 281 282declare void @f(i1 zeroext) 283 284 285define i1 @t10() { 286entry: 287 %q = alloca i32 288 %p = alloca i32 289 store i32 -3, i32* %q 290 store i32 -8, i32* %p 291 %0 = load i32, i32* %q 292 %1 = load i32, i32* %p 293 %div = sdiv i32 %0, %1 294 %mul = mul nsw i32 %div, %1 295 %rem = srem i32 %0, %1 296 %add = add nsw i32 %mul, %rem 297 %cmp = icmp eq i32 %add, %0 298 ret i1 %cmp 299 300; ARM-LABEL: t10: 301; ARM: rsbs r1, r0, #0 302; ARM: adc r0, r0, r1 303 304; ARMT2-LABEL: t10: 305; ARMT2: clz r0, r0 306; ARMT2: lsr r0, r0, #5 307 308; THUMB1-LABEL: t10: 309; THUMB1: movs r0, #0 310; THUMB1: subs r0, r0, r1 311; THUMB1: adcs r0, r1 312 313; THUMB2-LABEL: t10: 314; THUMB2: clz r0, r0 315; THUMB2: lsrs r0, r0, #5 316 317; V8MBASE-LABEL: t10: 318; V8MBASE-NOT: movs r0, #0 319; V8MBASE: movs r0, #7 320} 321 322define i1 @t11() { 323entry: 324 %bit = alloca i32 325 %load = load i32, i32* %bit 326 %clear = and i32 %load, -4096 327 %set = or i32 %clear, 33 328 store i32 %set, i32* %bit 329 %load1 = load i32, i32* %bit 330 %clear2 = and i32 %load1, -33550337 331 %set3 = or i32 %clear2, 40960 332 %clear5 = and i32 %set3, 4095 333 %rem = srem i32 %clear5, 10 334 %clear9 = and i32 %set3, -4096 335 %set10 = or i32 %clear9, %rem 336 store i32 %set10, i32* %bit 337 %clear12 = and i32 %set10, 4095 338 %cmp = icmp eq i32 %clear12, 3 339 ret i1 %cmp 340 341; ARM-LABEL: t11: 342; ARM: rsbs r1, r0, #0 343; ARM: adc r0, r0, r1 344 345; ARMT2-LABEL: t11: 346; ARMT2: clz r0, r0 347; ARMT2: lsr r0, r0, #5 348 349; THUMB1-LABEL: t11: 350; THUMB1-NOT: movs r0, #0 351; THUMB1: movs r0, #5 352 353; THUMB2-LABEL: t11: 354; THUMB2: clz r0, r0 355; THUMB2: lsrs r0, r0, #5 356 357; V8MBASE-LABEL: t11: 358; V8MBASE-NOT: movs r0, #0 359; V8MBASE: movw r0, #40960 360} 361