1; RUN: llc -march=hexagon < %s | FileCheck %s 2 3; The generation of a constant vector in the selection step resulted in 4; a VSPLAT, which, deeper in the expression tree had an unrelated BITCAST. 5; That bitcast was erroneously removed by the constant vector selection 6; function, and caused a selection error due to a type mismatch. 7; 8; Make sure this compiles successfully. 9; CHECK: vsplat 10 11target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" 12target triple = "hexagon" 13 14define void @fred() #0 { 15b0: 16 %v1 = load <8 x i16>, <8 x i16>* undef, align 2 17 %v2 = icmp sgt <8 x i16> %v1, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11> 18 %v3 = zext <8 x i1> %v2 to <8 x i32> 19 %v4 = add nuw nsw <8 x i32> zeroinitializer, %v3 20 %v5 = add nuw nsw <8 x i32> %v4, zeroinitializer 21 %v6 = shufflevector <8 x i32> %v5, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 22 %v7 = add nuw nsw <8 x i32> %v5, %v6 23 %v8 = extractelement <8 x i32> %v7, i32 0 24 %v9 = add nuw nsw i32 %v8, 0 25 %v10 = add nuw nsw i32 %v9, 0 26 %v11 = add nuw nsw i32 %v10, 0 27 %v12 = icmp ult i32 %v11, 5 28 br i1 %v12, label %b13, label %b14 29 30b13: ; preds = %b0 31 unreachable 32 33b14: ; preds = %b0 34 ret void 35} 36 37attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } 38