1# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s 2 3# Test the compare fold peephole. 4 5# CHECK-LABEL: name: test0a 6# TODO: Enhance combiner to handle this case. This expands into: 7# sub $r7, $r6, $r3 8# sub.f $r7, $r6, $r0 9# sel.eq $r18, $r3, $rv 10# This is different from the pattern currently matched. If the lowered form had 11# been sub.f $r3, 0, $r0 then it would have matched. 12 13# CHECK-LABEL: name: test1a 14# CHECK: [[IN1:%.*]]:gpr = COPY $r7 15# CHECK: [[IN2:%.*]]:gpr = COPY $r6 16# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr 17 18# CHECK-LABEL: name: test1b 19# CHECK: [[IN1:%.*]]:gpr = COPY $r7 20# CHECK: [[IN2:%.*]]:gpr = COPY $r6 21# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr 22 23# CHECK-LABEL: name: test2a 24# CHECK: [[IN1:%.*]]:gpr = COPY $r7 25# CHECK: [[IN2:%.*]]:gpr = COPY $r6 26# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr 27 28# CHECK-LABEL: name: test2b 29# CHECK: [[IN1:%.*]]:gpr = COPY $r7 30# CHECK: [[IN2:%.*]]:gpr = COPY $r6 31# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr 32 33# CHECK-LABEL: name: test3 34# CHECK: AND_F_R 35# CHECK: AND_F_R 36# CHECK: AND_F_R 37 38--- | 39 target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" 40 target triple = "lanai-unknown-unknown" 41 42 @a = global i32 -1, align 4 43 @b = global i32 0, align 4 44 45 define i32 @test0a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 46 entry: 47 %sub = sub i32 %b, %a 48 %cmp = icmp eq i32 %sub, 0 49 %cond = select i1 %cmp, i32 %c, i32 %sub 50 ret i32 %cond 51 } 52 53 define i32 @test0b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 54 entry: 55 %cmp = icmp eq i32 %b, %a 56 %cond = select i1 %cmp, i32 %c, i32 %b 57 ret i32 %cond 58 } 59 60 define i32 @test1a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 61 entry: 62 %sub = sub i32 %b, %a 63 %cmp = icmp slt i32 %sub, 0 64 %cond = select i1 %cmp, i32 %c, i32 %d 65 ret i32 %cond 66 } 67 68 define i32 @test1b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 69 entry: 70 %sub = sub i32 %b, %a 71 %cmp = icmp slt i32 %sub, 0 72 %cond = select i1 %cmp, i32 %c, i32 %d 73 ret i32 %cond 74 } 75 76 define i32 @test2a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 77 entry: 78 %sub = sub i32 %b, %a 79 %cmp = icmp sgt i32 %sub, -1 80 %cond = select i1 %cmp, i32 %c, i32 %d 81 ret i32 %cond 82 } 83 84 define i32 @test2b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 85 entry: 86 %sub = sub i32 %b, %a 87 %cmp = icmp sgt i32 %sub, -1 88 %cond = select i1 %cmp, i32 %c, i32 %d 89 ret i32 %cond 90 } 91 92 define i32 @test3(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 93 entry: 94 %sub = sub i32 %b, %a 95 %cmp = icmp slt i32 %sub, 1 96 %cond = select i1 %cmp, i32 %c, i32 %d 97 ret i32 %cond 98 } 99 100 define i32 @test4(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 101 entry: 102 %cmp = icmp ne i32 %a, 0 103 %cmp1 = icmp ult i32 %a, %b 104 %or.cond = and i1 %cmp, %cmp1 105 br i1 %or.cond, label %return, label %if.end 106 107 if.end: ; preds = %entry 108 %cmp2 = icmp ne i32 %b, 0 109 %cmp4 = icmp ult i32 %b, %c 110 %or.cond29 = and i1 %cmp2, %cmp4 111 br i1 %or.cond29, label %return, label %if.end6 112 113 if.end6: ; preds = %if.end 114 %cmp7 = icmp ne i32 %c, 0 115 %cmp9 = icmp ult i32 %c, %d 116 %or.cond30 = and i1 %cmp7, %cmp9 117 br i1 %or.cond30, label %return, label %if.end11 118 119 if.end11: ; preds = %if.end6 120 %cmp12 = icmp ne i32 %d, 0 121 %cmp14 = icmp ult i32 %d, %a 122 %or.cond31 = and i1 %cmp12, %cmp14 123 %b. = select i1 %or.cond31, i32 %b, i32 21 124 ret i32 %b. 125 126 return: ; preds = %if.end6, %if.end, %entry 127 %retval.0 = phi i32 [ %c, %entry ], [ %d, %if.end ], [ %a, %if.end6 ] 128 ret i32 %retval.0 129 } 130 131 define void @testBB() { 132 entry: 133 %0 = load i32, i32* @a, align 4, !tbaa !0 134 %1 = load i32, i32* @b, align 4, !tbaa !0 135 %sub.i = sub i32 %1, %0 136 %tobool = icmp sgt i32 %sub.i, -1 137 br i1 %tobool, label %if.end, label %if.then 138 139 if.then: ; preds = %entry 140 %call1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)() 141 br label %while.body 142 143 while.body: ; preds = %while.body, %if.then 144 br label %while.body 145 146 if.end: ; preds = %entry 147 %cmp.i = icmp slt i32 %sub.i, 1 148 br i1 %cmp.i, label %if.then4, label %if.end7 149 150 if.then4: ; preds = %if.end 151 %call5 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)() 152 br label %while.body6 153 154 while.body6: ; preds = %while.body6, %if.then4 155 br label %while.body6 156 157 if.end7: ; preds = %if.end 158 ret void 159 } 160 161 declare i32 @g(...) 162 163 ; Function Attrs: nounwind 164 declare void @llvm.stackprotector(i8*, i8**) #0 165 166 attributes #0 = { nounwind } 167 168 !0 = !{!1, !1, i64 0} 169 !1 = !{!"int", !2, i64 0} 170 !2 = !{!"omnipotent char", !3, i64 0} 171 !3 = !{!"Simple C/C++ TBAA"} 172 173... 174--- 175name: test0a 176alignment: 2 177exposesReturnsTwice: false 178tracksRegLiveness: true 179registers: 180 - { id: 0, class: gpr } 181 - { id: 1, class: gpr } 182 - { id: 2, class: gpr } 183 - { id: 3, class: gpr } 184 - { id: 4, class: gpr } 185 - { id: 5, class: gpr } 186liveins: 187 - { reg: '$r6', virtual-reg: '%0' } 188 - { reg: '$r7', virtual-reg: '%1' } 189 - { reg: '$r18', virtual-reg: '%2' } 190frameInfo: 191 isFrameAddressTaken: false 192 isReturnAddressTaken: false 193 hasStackMap: false 194 hasPatchPoint: false 195 stackSize: 0 196 offsetAdjustment: 0 197 maxAlignment: 0 198 adjustsStack: false 199 hasCalls: false 200 maxCallFrameSize: 0 201 hasOpaqueSPAdjustment: false 202 hasVAStart: false 203 hasMustTailInVarArgFunc: false 204body: | 205 bb.0.entry: 206 liveins: $r6, $r7, $r18 207 208 %2 = COPY $r18 209 %1 = COPY $r7 210 %0 = COPY $r6 211 %4 = SUB_R %1, %0, 0 212 SFSUB_F_RI_LO %4, 0, implicit-def $sr 213 %5 = SELECT %2, %4, 7, implicit $sr 214 $rv = COPY %5 215 RET implicit $rca, implicit $rv 216 217... 218--- 219name: test0b 220alignment: 2 221exposesReturnsTwice: false 222tracksRegLiveness: true 223registers: 224 - { id: 0, class: gpr } 225 - { id: 1, class: gpr } 226 - { id: 2, class: gpr } 227 - { id: 3, class: gpr } 228 - { id: 4, class: gpr } 229liveins: 230 - { reg: '$r6', virtual-reg: '%0' } 231 - { reg: '$r7', virtual-reg: '%1' } 232 - { reg: '$r18', virtual-reg: '%2' } 233frameInfo: 234 isFrameAddressTaken: false 235 isReturnAddressTaken: false 236 hasStackMap: false 237 hasPatchPoint: false 238 stackSize: 0 239 offsetAdjustment: 0 240 maxAlignment: 0 241 adjustsStack: false 242 hasCalls: false 243 maxCallFrameSize: 0 244 hasOpaqueSPAdjustment: false 245 hasVAStart: false 246 hasMustTailInVarArgFunc: false 247body: | 248 bb.0.entry: 249 liveins: $r6, $r7, $r18 250 251 %2 = COPY $r18 252 %1 = COPY $r7 253 %0 = COPY $r6 254 SFSUB_F_RR %1, %0, implicit-def $sr 255 %4 = SELECT %2, %1, 7, implicit $sr 256 $rv = COPY %4 257 RET implicit $rca, implicit $rv 258 259... 260--- 261name: test1a 262alignment: 2 263exposesReturnsTwice: false 264tracksRegLiveness: true 265registers: 266 - { id: 0, class: gpr } 267 - { id: 1, class: gpr } 268 - { id: 2, class: gpr } 269 - { id: 3, class: gpr } 270 - { id: 4, class: gpr } 271 - { id: 5, class: gpr } 272liveins: 273 - { reg: '$r6', virtual-reg: '%0' } 274 - { reg: '$r7', virtual-reg: '%1' } 275 - { reg: '$r18', virtual-reg: '%2' } 276 - { reg: '$r19', virtual-reg: '%3' } 277frameInfo: 278 isFrameAddressTaken: false 279 isReturnAddressTaken: false 280 hasStackMap: false 281 hasPatchPoint: false 282 stackSize: 0 283 offsetAdjustment: 0 284 maxAlignment: 0 285 adjustsStack: false 286 hasCalls: false 287 maxCallFrameSize: 0 288 hasOpaqueSPAdjustment: false 289 hasVAStart: false 290 hasMustTailInVarArgFunc: false 291body: | 292 bb.0.entry: 293 liveins: $r6, $r7, $r18, $r19 294 295 %3 = COPY $r19 296 %2 = COPY $r18 297 %1 = COPY $r7 298 %0 = COPY $r6 299 %4 = SUB_R %1, %0, 0 300 SFSUB_F_RI_LO killed %4, 0, implicit-def $sr 301 %5 = SELECT %2, %3, 11, implicit $sr 302 $rv = COPY %5 303 RET implicit $rca, implicit $rv 304 305... 306--- 307name: test1b 308alignment: 2 309exposesReturnsTwice: false 310tracksRegLiveness: true 311registers: 312 - { id: 0, class: gpr } 313 - { id: 1, class: gpr } 314 - { id: 2, class: gpr } 315 - { id: 3, class: gpr } 316 - { id: 4, class: gpr } 317 - { id: 5, class: gpr } 318liveins: 319 - { reg: '$r6', virtual-reg: '%0' } 320 - { reg: '$r7', virtual-reg: '%1' } 321 - { reg: '$r18', virtual-reg: '%2' } 322 - { reg: '$r19', virtual-reg: '%3' } 323frameInfo: 324 isFrameAddressTaken: false 325 isReturnAddressTaken: false 326 hasStackMap: false 327 hasPatchPoint: false 328 stackSize: 0 329 offsetAdjustment: 0 330 maxAlignment: 0 331 adjustsStack: false 332 hasCalls: false 333 maxCallFrameSize: 0 334 hasOpaqueSPAdjustment: false 335 hasVAStart: false 336 hasMustTailInVarArgFunc: false 337body: | 338 bb.0.entry: 339 liveins: $r6, $r7, $r18, $r19 340 341 %3 = COPY $r19 342 %2 = COPY $r18 343 %1 = COPY $r7 344 %0 = COPY $r6 345 %4 = SUB_R %1, %0, 0 346 SFSUB_F_RI_LO killed %4, 0, implicit-def $sr 347 %5 = SELECT %2, %3, 11, implicit $sr 348 $rv = COPY %5 349 RET implicit $rca, implicit $rv 350 351... 352--- 353name: test2a 354alignment: 2 355exposesReturnsTwice: false 356tracksRegLiveness: true 357registers: 358 - { id: 0, class: gpr } 359 - { id: 1, class: gpr } 360 - { id: 2, class: gpr } 361 - { id: 3, class: gpr } 362 - { id: 4, class: gpr } 363 - { id: 5, class: gpr } 364liveins: 365 - { reg: '$r6', virtual-reg: '%0' } 366 - { reg: '$r7', virtual-reg: '%1' } 367 - { reg: '$r18', virtual-reg: '%2' } 368 - { reg: '$r19', virtual-reg: '%3' } 369frameInfo: 370 isFrameAddressTaken: false 371 isReturnAddressTaken: false 372 hasStackMap: false 373 hasPatchPoint: false 374 stackSize: 0 375 offsetAdjustment: 0 376 maxAlignment: 0 377 adjustsStack: false 378 hasCalls: false 379 maxCallFrameSize: 0 380 hasOpaqueSPAdjustment: false 381 hasVAStart: false 382 hasMustTailInVarArgFunc: false 383body: | 384 bb.0.entry: 385 liveins: $r6, $r7, $r18, $r19 386 387 %3 = COPY $r19 388 %2 = COPY $r18 389 %1 = COPY $r7 390 %0 = COPY $r6 391 %4 = SUB_R %1, %0, 0 392 SFSUB_F_RI_LO killed %4, 0, implicit-def $sr 393 %5 = SELECT %2, %3, 10, implicit $sr 394 $rv = COPY %5 395 RET implicit $rca, implicit $rv 396 397... 398--- 399name: test2b 400alignment: 2 401exposesReturnsTwice: false 402tracksRegLiveness: true 403registers: 404 - { id: 0, class: gpr } 405 - { id: 1, class: gpr } 406 - { id: 2, class: gpr } 407 - { id: 3, class: gpr } 408 - { id: 4, class: gpr } 409 - { id: 5, class: gpr } 410liveins: 411 - { reg: '$r6', virtual-reg: '%0' } 412 - { reg: '$r7', virtual-reg: '%1' } 413 - { reg: '$r18', virtual-reg: '%2' } 414 - { reg: '$r19', virtual-reg: '%3' } 415frameInfo: 416 isFrameAddressTaken: false 417 isReturnAddressTaken: false 418 hasStackMap: false 419 hasPatchPoint: false 420 stackSize: 0 421 offsetAdjustment: 0 422 maxAlignment: 0 423 adjustsStack: false 424 hasCalls: false 425 maxCallFrameSize: 0 426 hasOpaqueSPAdjustment: false 427 hasVAStart: false 428 hasMustTailInVarArgFunc: false 429body: | 430 bb.0.entry: 431 liveins: $r6, $r7, $r18, $r19 432 433 %3 = COPY $r19 434 %2 = COPY $r18 435 %1 = COPY $r7 436 %0 = COPY $r6 437 %4 = SUB_R %1, %0, 0 438 SFSUB_F_RI_LO killed %4, 0, implicit-def $sr 439 %5 = SELECT %2, %3, 10, implicit $sr 440 $rv = COPY %5 441 RET implicit $rca, implicit $rv 442 443... 444--- 445name: test3 446alignment: 2 447exposesReturnsTwice: false 448tracksRegLiveness: true 449registers: 450 - { id: 0, class: gpr } 451 - { id: 1, class: gpr } 452 - { id: 2, class: gpr } 453 - { id: 3, class: gpr } 454 - { id: 4, class: gpr } 455 - { id: 5, class: gpr } 456liveins: 457 - { reg: '$r6', virtual-reg: '%0' } 458 - { reg: '$r7', virtual-reg: '%1' } 459 - { reg: '$r18', virtual-reg: '%2' } 460 - { reg: '$r19', virtual-reg: '%3' } 461frameInfo: 462 isFrameAddressTaken: false 463 isReturnAddressTaken: false 464 hasStackMap: false 465 hasPatchPoint: false 466 stackSize: 0 467 offsetAdjustment: 0 468 maxAlignment: 0 469 adjustsStack: false 470 hasCalls: false 471 maxCallFrameSize: 0 472 hasOpaqueSPAdjustment: false 473 hasVAStart: false 474 hasMustTailInVarArgFunc: false 475body: | 476 bb.0.entry: 477 liveins: $r6, $r7, $r18, $r19 478 479 %3 = COPY $r19 480 %2 = COPY $r18 481 %1 = COPY $r7 482 %0 = COPY $r6 483 %4 = SUB_R %1, %0, 0 484 SFSUB_F_RI_LO killed %4, 1, implicit-def $sr 485 %5 = SELECT %2, %3, 13, implicit $sr 486 $rv = COPY %5 487 RET implicit $rca, implicit $rv 488 489... 490--- 491name: test4 492alignment: 2 493exposesReturnsTwice: false 494tracksRegLiveness: true 495registers: 496 - { id: 0, class: gpr } 497 - { id: 1, class: gpr } 498 - { id: 2, class: gpr } 499 - { id: 3, class: gpr } 500 - { id: 4, class: gpr } 501 - { id: 5, class: gpr } 502 - { id: 6, class: gpr } 503 - { id: 7, class: gpr } 504 - { id: 8, class: gpr } 505 - { id: 9, class: gpr } 506 - { id: 10, class: gpr } 507 - { id: 11, class: gpr } 508 - { id: 12, class: gpr } 509 - { id: 13, class: gpr } 510 - { id: 14, class: gpr } 511 - { id: 15, class: gpr } 512 - { id: 16, class: gpr } 513 - { id: 17, class: gpr } 514 - { id: 18, class: gpr } 515 - { id: 19, class: gpr } 516 - { id: 20, class: gpr } 517 - { id: 21, class: gpr } 518 - { id: 22, class: gpr } 519liveins: 520 - { reg: '$r6', virtual-reg: '%1' } 521 - { reg: '$r7', virtual-reg: '%2' } 522 - { reg: '$r18', virtual-reg: '%3' } 523 - { reg: '$r19', virtual-reg: '%4' } 524frameInfo: 525 isFrameAddressTaken: false 526 isReturnAddressTaken: false 527 hasStackMap: false 528 hasPatchPoint: false 529 stackSize: 0 530 offsetAdjustment: 0 531 maxAlignment: 0 532 adjustsStack: false 533 hasCalls: false 534 maxCallFrameSize: 0 535 hasOpaqueSPAdjustment: false 536 hasVAStart: false 537 hasMustTailInVarArgFunc: false 538body: | 539 bb.0.entry: 540 successors: %bb.4.return, %bb.1.if.end 541 liveins: $r6, $r7, $r18, $r19 542 543 %4 = COPY $r19 544 %3 = COPY $r18 545 %2 = COPY $r7 546 %1 = COPY $r6 547 SFSUB_F_RI_LO %1, 0, implicit-def $sr 548 %5 = SCC 6, implicit $sr 549 SFSUB_F_RR %1, %2, implicit-def $sr 550 %6 = SCC 4, implicit $sr 551 %7 = AND_R killed %5, killed %6, 0 552 %8 = SLI 1 553 %9 = AND_R killed %7, %8, 0 554 SFSUB_F_RI_LO killed %9, 0, implicit-def $sr 555 BRCC %bb.4.return, 6, implicit $sr 556 BT %bb.1.if.end 557 558 bb.1.if.end: 559 successors: %bb.4.return, %bb.2.if.end6 560 561 SFSUB_F_RI_LO %2, 0, implicit-def $sr 562 %10 = SCC 6, implicit $sr 563 SFSUB_F_RR %2, %3, implicit-def $sr 564 %11 = SCC 4, implicit $sr 565 %12 = AND_R killed %10, killed %11, 0 566 %14 = AND_R killed %12, %8, 0 567 SFSUB_F_RI_LO killed %14, 0, implicit-def $sr 568 BRCC %bb.4.return, 6, implicit $sr 569 BT %bb.2.if.end6 570 571 bb.2.if.end6: 572 successors: %bb.4.return, %bb.3.if.end11 573 574 SFSUB_F_RI_LO %3, 0, implicit-def $sr 575 %15 = SCC 6, implicit $sr 576 SFSUB_F_RR %3, %4, implicit-def $sr 577 %16 = SCC 4, implicit $sr 578 %17 = AND_R killed %15, killed %16, 0 579 %18 = SLI 1 580 %19 = AND_R killed %17, killed %18, 0 581 SFSUB_F_RI_LO killed %19, 0, implicit-def $sr 582 BRCC %bb.4.return, 6, implicit $sr 583 BT %bb.3.if.end11 584 585 bb.3.if.end11: 586 %20 = SLI 21 587 SFSUB_F_RR %4, %1, implicit-def $sr 588 %21 = SELECT %2, %20, 4, implicit $sr 589 SFSUB_F_RI_LO %4, 0, implicit-def $sr 590 %22 = SELECT killed %21, %20, 6, implicit $sr 591 $rv = COPY %22 592 RET implicit $rca, implicit $rv 593 594 bb.4.return: 595 %0 = PHI %3, %bb.0.entry, %4, %bb.1.if.end, %1, %bb.2.if.end6 596 $rv = COPY %0 597 RET implicit $rca, implicit $rv 598 599... 600--- 601name: testBB 602alignment: 2 603exposesReturnsTwice: false 604tracksRegLiveness: true 605registers: 606 - { id: 0, class: gpr } 607 - { id: 1, class: gpr } 608 - { id: 2, class: gpr } 609 - { id: 3, class: gpr } 610 - { id: 4, class: gpr } 611 - { id: 5, class: gpr } 612 - { id: 6, class: gpr } 613 - { id: 7, class: gpr } 614 - { id: 8, class: gpr } 615frameInfo: 616 isFrameAddressTaken: false 617 isReturnAddressTaken: false 618 hasStackMap: false 619 hasPatchPoint: false 620 stackSize: 0 621 offsetAdjustment: 0 622 maxAlignment: 0 623 adjustsStack: false 624 hasCalls: true 625 maxCallFrameSize: 0 626 hasOpaqueSPAdjustment: false 627 hasVAStart: false 628 hasMustTailInVarArgFunc: false 629body: | 630 bb.0.entry: 631 successors: %bb.3.if.end, %bb.1.if.then 632 633 %1 = MOVHI target-flags(lanai-hi) @a 634 %2 = OR_I_LO killed %1, target-flags(lanai-lo) @a 635 %3 = LDW_RI killed %2, 0, 0 :: (load 4 from @a, !tbaa !0) 636 %4 = MOVHI target-flags(lanai-hi) @b 637 %5 = OR_I_LO killed %4, target-flags(lanai-lo) @b 638 %6 = LDW_RI killed %5, 0, 0 :: (load 4 from @b, !tbaa !0) 639 %0 = SUB_R killed %6, killed %3, 0 640 SFSUB_F_RI_LO %0, 0, implicit-def $sr 641 BRCC %bb.3.if.end, 10, implicit $sr 642 BT %bb.1.if.then 643 644 bb.1.if.then: 645 successors: %bb.2.while.body 646 647 ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp 648 CALL @g, csr, implicit-def dead $rca, implicit $sp, implicit-def $sp, implicit-def $rv 649 ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp 650 651 bb.2.while.body: 652 successors: %bb.2.while.body 653 654 BT %bb.2.while.body 655 656 bb.3.if.end: 657 successors: %bb.4.if.then4, %bb.6.if.end7 658 liveins: $sr 659 660 BRCC %bb.6.if.end7, 14, implicit $sr 661 BT %bb.4.if.then4 662 663 bb.4.if.then4: 664 successors: %bb.5.while.body6 665 666 ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp 667 CALL @g, csr, implicit-def dead $rca, implicit $sp, implicit-def $sp, implicit-def $rv 668 ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp 669 670 bb.5.while.body6: 671 successors: %bb.5.while.body6 672 673 BT %bb.5.while.body6 674 675 bb.6.if.end7: 676 RET implicit $rca 677 678... 679