1; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,MIPS4,ACCMULDIV %s 2; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s 3; RUN: llc -march=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s 4; RUN: llc -march=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,GPRMULDIV %s 5 6@gll0 = common global i64 0, align 8 7@gll1 = common global i64 0, align 8 8 9define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { 10entry: 11; ALL-LABEL: f0: 12; ALL: daddu $2, ${{[45]}}, ${{[45]}} 13 %add = add nsw i64 %a1, %a0 14 ret i64 %add 15} 16 17define i64 @f1(i64 %a0, i64 %a1) nounwind readnone { 18entry: 19; ALL-LABEL: f1: 20; ALL: dsubu $2, $4, $5 21 %sub = sub nsw i64 %a0, %a1 22 ret i64 %sub 23} 24 25define i64 @f4(i64 %a0, i64 %a1) nounwind readnone { 26entry: 27; ALL-LABEL: f4: 28; ALL: and $2, ${{[45]}}, ${{[45]}} 29 %and = and i64 %a1, %a0 30 ret i64 %and 31} 32 33define i64 @f5(i64 %a0, i64 %a1) nounwind readnone { 34entry: 35; ALL-LABEL: f5: 36; ALL: or $2, ${{[45]}}, ${{[45]}} 37 %or = or i64 %a1, %a0 38 ret i64 %or 39} 40 41define i64 @f6(i64 %a0, i64 %a1) nounwind readnone { 42entry: 43; ALL-LABEL: f6: 44; ALL: xor $2, ${{[45]}}, ${{[45]}} 45 %xor = xor i64 %a1, %a0 46 ret i64 %xor 47} 48 49define i64 @f7(i64 %a0) nounwind readnone { 50entry: 51; ALL-LABEL: f7: 52; ALL: daddiu $2, $4, 20 53 %add = add nsw i64 %a0, 20 54 ret i64 %add 55} 56 57define i64 @f8(i64 %a0) nounwind readnone { 58entry: 59; ALL-LABEL: f8: 60; ALL: daddiu $2, $4, -20 61 %sub = add nsw i64 %a0, -20 62 ret i64 %sub 63} 64 65define i64 @f9(i64 %a0) nounwind readnone { 66entry: 67; ALL-LABEL: f9: 68; ALL: andi $2, $4, 20 69 %and = and i64 %a0, 20 70 ret i64 %and 71} 72 73define i64 @f10(i64 %a0) nounwind readnone { 74entry: 75; ALL-LABEL: f10: 76; ALL: ori $2, $4, 20 77 %or = or i64 %a0, 20 78 ret i64 %or 79} 80 81define i64 @f11(i64 %a0) nounwind readnone { 82entry: 83; ALL-LABEL: f11: 84; ALL: xori $2, $4, 20 85 %xor = xor i64 %a0, 20 86 ret i64 %xor 87} 88 89define i64 @f12(i64 %a, i64 %b) nounwind readnone { 90entry: 91; ALL-LABEL: f12: 92 93; ACCMULDIV: mult ${{[45]}}, ${{[45]}} 94; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}} 95 96 %mul = mul nsw i64 %b, %a 97 ret i64 %mul 98} 99 100define i64 @f13(i64 %a, i64 %b) nounwind readnone { 101entry: 102; ALL-LABEL: f13: 103 104; ACCMULDIV: mult ${{[45]}}, ${{[45]}} 105; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}} 106 107 %mul = mul i64 %b, %a 108 ret i64 %mul 109} 110 111define i64 @f14(i64 %a, i64 %b) nounwind readnone { 112entry: 113; ALL-LABEL: f14: 114; ALL-DAG: ld $[[T0:[0-9]+]], %lo(gll0)(${{[0-9]+}}) 115; ALL-DAG: ld $[[T1:[0-9]+]], %lo(gll1)(${{[0-9]+}}) 116 117; ACCMULDIV: ddiv $zero, $[[T0]], $[[T1]] 118; ACCMULDIV: teq $[[T1]], $zero, 7 119; ACCMULDIV: mflo $2 120 121; GPRMULDIV: ddiv $2, $[[T0]], $[[T1]] 122; GPRMULDIV: teq $[[T1]], $zero, 7 123 124 %0 = load i64, i64* @gll0, align 8 125 %1 = load i64, i64* @gll1, align 8 126 %div = sdiv i64 %0, %1 127 ret i64 %div 128} 129 130define i64 @f15() nounwind readnone { 131entry: 132; ALL-LABEL: f15: 133; ALL-DAG: ld $[[T0:[0-9]+]], %lo(gll0)(${{[0-9]+}}) 134; ALL-DAG: ld $[[T1:[0-9]+]], %lo(gll1)(${{[0-9]+}}) 135 136; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]] 137; ACCMULDIV: teq $[[T1]], $zero, 7 138; ACCMULDIV: mflo $2 139 140; GPRMULDIV: ddivu $2, $[[T0]], $[[T1]] 141; GPRMULDIV: teq $[[T1]], $zero, 7 142 143 %0 = load i64, i64* @gll0, align 8 144 %1 = load i64, i64* @gll1, align 8 145 %div = udiv i64 %0, %1 146 ret i64 %div 147} 148 149define i64 @f16(i64 %a, i64 %b) nounwind readnone { 150entry: 151; ALL-LABEL: f16: 152 153; ACCMULDIV: ddiv $zero, $4, $5 154; ACCMULDIV: teq $5, $zero, 7 155; ACCMULDIV: mfhi $2 156 157; GPRMULDIV: dmod $2, $4, $5 158; GPRMULDIV: teq $5, $zero, 7 159 160 %rem = srem i64 %a, %b 161 ret i64 %rem 162} 163 164define i64 @f17(i64 %a, i64 %b) nounwind readnone { 165entry: 166; ALL-LABEL: f17: 167 168; ACCMULDIV: ddivu $zero, $4, $5 169; ACCMULDIV: teq $5, $zero, 7 170; ACCMULDIV: mfhi $2 171 172; GPRMULDIV: dmodu $2, $4, $5 173; GPRMULDIV: teq $5, $zero, 7 174 175 %rem = urem i64 %a, %b 176 ret i64 %rem 177} 178 179declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone 180 181define i64 @f18(i64 %X) nounwind readnone { 182entry: 183; ALL-LABEL: f18: 184 185; The MIPS4 version is too long to reasonably test. At least check we don't get dclz 186; MIPS4-NOT: dclz 187 188; HAS-DCLO: dclz $2, $4 189 190 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) 191 ret i64 %tmp1 192} 193 194define i64 @f19(i64 %X) nounwind readnone { 195entry: 196; ALL-LABEL: f19: 197 198; The MIPS4 version is too long to reasonably test. At least check we don't get dclo 199; MIPS4-NOT: dclo 200 201; HAS-DCLO: dclo $2, $4 202 203 %neg = xor i64 %X, -1 204 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) 205 ret i64 %tmp1 206} 207 208define i64 @f20(i64 %a, i64 %b) nounwind readnone { 209entry: 210; ALL-LABEL: f20: 211; ALL: nor $2, ${{[45]}}, ${{[45]}} 212 %or = or i64 %b, %a 213 %neg = xor i64 %or, -1 214 ret i64 %neg 215} 216