1; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -allow-deprecated-dag-overlap %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-NO-EMIT 2; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+nooddspreg < %s | FileCheck -allow-deprecated-dag-overlap %s -check-prefixes=ALL,NOODDSPREG 3; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64 < %s | FileCheck -allow-deprecated-dag-overlap %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-NO-EMIT 4; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64,+nooddspreg < %s | FileCheck -allow-deprecated-dag-overlap %s -check-prefixes=ALL,NOODDSPREG 5; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fpxx,-nooddspreg < %s | FileCheck -allow-deprecated-dag-overlap %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-EMIT 6 7; We don't emit a directive unless we need to. This is to support versions of 8; GAS which do not support the directive. 9; ODDSPREG-EMIT: .module oddspreg 10; ODDSPREG-NO-EMIT-NOT: .module oddspreg 11; NOODDSPREG: .module nooddspreg 12 13define float @two_floats(float %a) { 14entry: 15 ; Clobber all except $f12 and $f13 16 ; 17 ; The intention is that if odd single precision registers are permitted, the 18 ; allocator will choose $f12 and $f13 to avoid the spill/reload. 19 ; 20 ; On the other hand, if odd single precision registers are not permitted, it 21 ; will be forced to spill/reload either %a or %0. 22 ; 23 ; This is affected by scheduling as the new machine scheduler schedules the 24 ; two adds together, avoiding the spill+reload. 25 26 %0 = fadd float %a, 1.0 27 call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() 28 %1 = fadd float %a, %0 29 ret float %1 30} 31 32; ALL-LABEL: two_floats: 33; ODDSPREG: add.s $f[[RES:[0-9]]], $f12, ${{f[0-9]+}} 34; ODDSPREG: add.s ${{f[0-9]+}}, $f12, $f[[RES]] 35; ODDSPREG-NOT: swc1 36; ODDSPREG-NOT: lwc1 37 38; NOODDSPREG: add.s $[[T0:f[0-9]*[02468]]], $f12, ${{f[0-9]+}} 39; NOODDSPREG-NOT: swc1 $[[T0]], 40; NOODDSPREG-NOT: lwc1 $[[T1:f[0-9]*[02468]]], 41; NOODDSPREG: add.s ${{f[0-9]+}}, $f12, $[[T0]] 42 43define double @two_doubles(double %a) { 44entry: 45 ; Clobber all except $f12 and $f13 46 ; 47 ; -mno-odd-sp-reg doesn't need to affect double precision values so both cases 48 ; use $f12 and $f13. 49 50 %0 = fadd double %a, 1.0 51 call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() 52 %1 = fadd double %a, %0 53 ret double %1 54} 55 56; ALL-LABEL: two_doubles: 57; ALL-DAG: add.d $[[T0:f[0-9]+]], $f12, ${{f[0-9]+}} 58; ALL-DAG: add.d $f0, $f12, $[[T0]] 59 60 61; INVALID: -mattr=+nooddspreg is not currently permitted for a 32-bit FPU register file (FR=0 mode). 62