1; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON 2; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64 3; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC 4 5define i64 @addi64(i64 %a, i64 %b) nounwind { 6entry: 7; ALL-LABEL: addi64: 8; OCTEON: jr $ra 9; OCTEON: baddu $2, $4, $5 10; MIPS64: daddu $[[T0:[0-9]+]], $4, $5 11; MIPS64: jr $ra 12; MIPS64: andi $2, $[[T0]], 255 13 %add = add i64 %a, %b 14 %and = and i64 %add, 255 15 ret i64 %and 16} 17 18define i64 @mul(i64 %a, i64 %b) nounwind { 19entry: 20; ALL-LABEL: mul: 21; OCTEON: jr $ra 22; OCTEON: dmul $2, $4, $5 23; MIPS64: dmult $4, $5 24; MIPS64: jr $ra 25; MIPS64: mflo $2 26 %res = mul i64 %a, %b 27 ret i64 %res 28} 29 30define i64 @cmpeq(i64 %a, i64 %b) nounwind { 31entry: 32; ALL-LABEL: cmpeq: 33; OCTEON: jr $ra 34; OCTEON: seq $2, $4, $5 35; MIPS64: xor $[[T0:[0-9]+]], $4, $5 36; MIPS64: sltiu $[[T1:[0-9]+]], $[[T0]], 1 37; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32 38; MIPS64: jr $ra 39; MIPS64: dsrl $2, $[[T2]], 32 40 %res = icmp eq i64 %a, %b 41 %res2 = zext i1 %res to i64 42 ret i64 %res2 43} 44 45define i64 @cmpeqi(i64 %a) nounwind { 46entry: 47; ALL-LABEL: cmpeqi: 48; OCTEON: jr $ra 49; OCTEON: seqi $2, $4, 42 50; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42 51; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]] 52; MIPS64: sltiu $[[T2:[0-9]+]], $[[T1]], 1 53; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32 54; MIPS64: jr $ra 55; MIPS64: dsrl $2, $[[T3]], 32 56 %res = icmp eq i64 %a, 42 57 %res2 = zext i1 %res to i64 58 ret i64 %res2 59} 60 61define i64 @cmpne(i64 %a, i64 %b) nounwind { 62entry: 63; ALL-LABEL: cmpne: 64; OCTEON: jr $ra 65; OCTEON: sne $2, $4, $5 66; MIPS64: xor $[[T0:[0-9]+]], $4, $5 67; MIPS64: sltu $[[T1:[0-9]+]], $zero, $[[T0]] 68; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32 69; MIPS64: jr $ra 70; MIPS64: dsrl $2, $[[T2]], 32 71 %res = icmp ne i64 %a, %b 72 %res2 = zext i1 %res to i64 73 ret i64 %res2 74} 75 76define i64 @cmpnei(i64 %a) nounwind { 77entry: 78; ALL-LABEL: cmpnei: 79; OCTEON: jr $ra 80; OCTEON: snei $2, $4, 42 81; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42 82; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]] 83; MIPS64: sltu $[[T2:[0-9]+]], $zero, $[[T1]] 84; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32 85; MIPS64: jr $ra 86; MIPS64: dsrl $2, $[[T3]], 32 87 %res = icmp ne i64 %a, 42 88 %res2 = zext i1 %res to i64 89 ret i64 %res2 90} 91 92define i64 @bbit1(i64 %a) nounwind { 93entry: 94; ALL-LABEL: bbit1: 95; OCTEON: bbit1 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] 96; OCTEON-PIC-NOT: b {{[[:space:]].*}} 97; OCTEON-NOT: j {{[[:space:]].*}} 98; MIPS64: andi $[[T0:[0-9]+]], $4, 8 99; MIPS64: bnez $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]] 100 %bit = and i64 %a, 8 101 %res = icmp eq i64 %bit, 0 102 br i1 %res, label %endif, label %if 103if: 104 ret i64 48 105 106endif: 107 ret i64 12 108} 109 110define i64 @bbit132(i64 %a) nounwind { 111entry: 112; ALL-LABEL: bbit132: 113; OCTEON: bbit132 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] 114; OCTEON-PIC-NOT: b {{[[:space:]].*}} 115; OCTEON-NOT: j {{[[:space:]].*}} 116; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1 117; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35 118; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]] 119; MIPS64: bnez $[[T2]], [[BB0:(\$|\.L)BB[0-9_]+]] 120 %bit = and i64 %a, 34359738368 121 %res = icmp eq i64 %bit, 0 122 br i1 %res, label %endif, label %if 123if: 124 ret i64 48 125 126endif: 127 ret i64 12 128} 129 130define i64 @bbit0(i64 %a) nounwind { 131entry: 132; ALL-LABEL: bbit0: 133; OCTEON: bbit0 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] 134; OCTEON-PIC-NOT: b {{[[:space:]].*}} 135; OCTEON-NOT: j {{[[:space:]].*}} 136; MIPS64: andi $[[T0:[0-9]+]], $4, 8 137; MIPS64: beqz $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]] 138 %bit = and i64 %a, 8 139 %res = icmp ne i64 %bit, 0 140 br i1 %res, label %endif, label %if 141if: 142 ret i64 48 143 144endif: 145 ret i64 12 146} 147 148define i64 @bbit032(i64 %a) nounwind { 149entry: 150; ALL-LABEL: bbit032: 151; OCTEON: bbit032 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] 152; OCTEON-PIC-NOT: b {{[[:space:]].*}} 153; OCTEON-NOT: j {{[[:space:]].*}} 154; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1 155; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35 156; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]] 157; MIPS64: beqz $[[T2]], [[BB0:(\$|\.L)BB[0-9_]+]] 158 %bit = and i64 %a, 34359738368 159 %res = icmp ne i64 %bit, 0 160 br i1 %res, label %endif, label %if 161if: 162 ret i64 48 163 164endif: 165 ret i64 12 166} 167 168; extern void foo(void); 169; long long var = 7; 170; void bbit0i32 () { 171; if ((var & 0x2)) { 172; foo(); 173; } 174; } 175; 176; void bbit1i32() { 177; if (!(var & 0x2)) { 178; foo(); 179; } 180; } 181 182@var = local_unnamed_addr global i64 7, align 8 183 184define void @bbit0i32() local_unnamed_addr { 185entry: 186; ALL-LABEL: bbit0i32: 187; OCTEON: bbit0 $1, 1, [[BB0:(\$|\.L)BB[0-9_]+]] 188; OCTEON-PIC-NOT: b {{[[:space:]].*}} 189; OCTEON-NOT: j {{[[:space:]].*}} 190 %0 = load i64, i64* @var, align 8 191 %and = and i64 %0, 2 192 %tobool = icmp eq i64 %and, 0 193 br i1 %tobool, label %if.end, label %if.then 194 195if.then: ; preds = %entry 196 tail call void @foo() #2 197 br label %if.end 198 199if.end: ; preds = %entry, %if.then 200 ret void 201} 202 203declare void @foo() local_unnamed_addr 204 205define void @bbit1i32() local_unnamed_addr { 206entry: 207; ALL-LABEL: bbit1i32: 208; OCTEON: bbit1 $1, 1, [[BB0:(\$|\.L)BB[0-9_]+]] 209; OCTEON-PIC-NOT: b {{[[:space:]].*}} 210; OCTEON-NOT: j {{[[:space:]].*}} 211 %0 = load i64, i64* @var, align 8 212 %and = and i64 %0, 2 213 %tobool = icmp eq i64 %and, 0 214 br i1 %tobool, label %if.then, label %if.end 215 216if.then: ; preds = %entry 217 tail call void @foo() #2 218 br label %if.end 219 220if.end: ; preds = %entry, %if.then 221 ret void 222} 223