1; FIXME: FastISel currently returns false if it hits code that uses VSX 2; registers and with -fast-isel-abort=1 turned on the test case will then fail. 3; When fastisel better supports VSX fix up this test case. 4; 5; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 6 7define zeroext i1 @rettrue() nounwind { 8entry: 9; ELF64-LABEL: rettrue 10; ELF64: li 3, 1 11; ELF64: blr 12 ret i1 true 13} 14 15define zeroext i1 @retfalse() nounwind { 16entry: 17; ELF64-LABEL: retfalse 18; ELF64: li 3, 0 19; ELF64: blr 20 ret i1 false 21} 22 23define signext i1 @retstrue() nounwind { 24entry: 25; ELF64-LABEL: retstrue 26; ELF64: li 3, -1 27; ELF64: blr 28 ret i1 true 29} 30 31define signext i1 @retsfalse() nounwind { 32entry: 33; ELF64-LABEL: retsfalse 34; ELF64: li 3, 0 35; ELF64: blr 36 ret i1 false 37} 38 39define signext i8 @ret2(i8 signext %a) nounwind { 40entry: 41; ELF64-LABEL: ret2 42; ELF64: extsb 43; ELF64: blr 44 ret i8 %a 45} 46 47define zeroext i8 @ret3(i8 signext %a) nounwind { 48entry: 49; ELF64-LABEL: ret3 50; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 51; ELF64: blr 52 ret i8 %a 53} 54 55define signext i16 @ret4(i16 signext %a) nounwind { 56entry: 57; ELF64-LABEL: ret4 58; ELF64: extsh 59; ELF64: blr 60 ret i16 %a 61} 62 63define zeroext i16 @ret5(i16 signext %a) nounwind { 64entry: 65; ELF64-LABEL: ret5 66; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 67; ELF64: blr 68 ret i16 %a 69} 70 71define i16 @ret6(i16 %a) nounwind { 72entry: 73; ELF64-LABEL: ret6 74; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 75; ELF64: blr 76 ret i16 %a 77} 78 79define signext i32 @ret7(i32 signext %a) nounwind { 80entry: 81; ELF64-LABEL: ret7 82; ELF64: extsw 83; ELF64: blr 84 ret i32 %a 85} 86 87define zeroext i32 @ret8(i32 signext %a) nounwind { 88entry: 89; ELF64-LABEL: ret8 90; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32 91; ELF64: blr 92 ret i32 %a 93} 94 95define i32 @ret9(i32 %a) nounwind { 96entry: 97; ELF64-LABEL: ret9 98; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32 99; ELF64: blr 100 ret i32 %a 101} 102 103define i64 @ret10(i64 %a) nounwind { 104entry: 105; ELF64-LABEL: ret10 106; ELF64-NOT: exts 107; ELF64-NOT: clrldi 108; ELF64-NOT: rldicl 109; ELF64: blr 110 ret i64 %a 111} 112 113define float @ret11(float %a) nounwind { 114entry: 115; ELF64-LABEL: ret11 116; ELF64: blr 117 ret float %a 118} 119 120define double @ret12(double %a) nounwind { 121entry: 122; ELF64-LABEL: ret12 123; ELF64: blr 124 ret double %a 125} 126 127define i8 @ret13() nounwind { 128entry: 129; ELF64-LABEL: ret13 130; ELF64: li 131; ELF64: blr 132 ret i8 15; 133} 134 135define i16 @ret14() nounwind { 136entry: 137; ELF64-LABEL: ret14 138; ELF64: li 139; ELF64: blr 140 ret i16 -225; 141} 142 143define i32 @ret15() nounwind { 144entry: 145; ELF64-LABEL: ret15 146; ELF64: lis 147; ELF64: ori 148; ELF64: blr 149 ret i32 278135; 150} 151 152define i64 @ret16() nounwind { 153entry: 154; ELF64-LABEL: ret16 155; ELF64: li 156; ELF64: sldi 157; ELF64: oris 158; ELF64: ori 159; ELF64: blr 160 ret i64 27813515225; 161} 162 163define float @ret17() nounwind { 164entry: 165; ELF64-LABEL: ret17 166; ELF64: addis 167; ELF64: lfs 168; ELF64: blr 169 ret float 2.5; 170} 171 172define double @ret18() nounwind { 173entry: 174; ELF64-LABEL: ret18 175; ELF64: addis 176; ELF64: lfd 177; ELF64: blr 178 ret double 2.5e-33; 179} 180 181define zeroext i32 @ret19() nounwind { 182entry: 183; ELF64-LABEL: ret19 184; ELF64: li 185; ELF64: oris 186; ELF64: ori 187; ELF64: blr 188 ret i32 -1 189} 190 191define zeroext i16 @ret20() nounwind { 192entry: 193; ELF64-LABEL: ret20 194; ELF64: lis{{.*}}0 195; ELF64: ori{{.*}}32768 196; ELF64: blr 197 ret i16 32768 198} 199