1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s | FileCheck %s 3target triple = "powerpc64le-linux-gnu" 4 5define i8 @test000(i8 %a, i8 %b) { 6; CHECK-LABEL: test000: 7; CHECK: # %bb.0: 8; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31 9; CHECK-NEXT: slw 3, 3, 4 10; CHECK-NEXT: blr 11 %rem = and i8 %b, 7 12 %shl = shl i8 %a, %rem 13 ret i8 %shl 14} 15 16define i16 @test001(i16 %a, i16 %b) { 17; CHECK-LABEL: test001: 18; CHECK: # %bb.0: 19; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 20; CHECK-NEXT: slw 3, 3, 4 21; CHECK-NEXT: blr 22 %rem = and i16 %b, 15 23 %shl = shl i16 %a, %rem 24 ret i16 %shl 25} 26 27define i32 @test002(i32 %a, i32 %b) { 28; CHECK-LABEL: test002: 29; CHECK: # %bb.0: 30; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31 31; CHECK-NEXT: slw 3, 3, 4 32; CHECK-NEXT: blr 33 %rem = and i32 %b, 31 34 %shl = shl i32 %a, %rem 35 ret i32 %shl 36} 37 38define i64 @test003(i64 %a, i64 %b) { 39; CHECK-LABEL: test003: 40; CHECK: # %bb.0: 41; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31 42; CHECK-NEXT: sld 3, 3, 4 43; CHECK-NEXT: blr 44 %rem = and i64 %b, 63 45 %shl = shl i64 %a, %rem 46 ret i64 %shl 47} 48 49define <16 x i8> @test010(<16 x i8> %a, <16 x i8> %b) { 50; CHECK-LABEL: test010: 51; CHECK: # %bb.0: 52; CHECK-NEXT: vslb 2, 2, 3 53; CHECK-NEXT: blr 54 %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 55 %shl = shl <16 x i8> %a, %rem 56 ret <16 x i8> %shl 57} 58 59define <8 x i16> @test011(<8 x i16> %a, <8 x i16> %b) { 60; CHECK-LABEL: test011: 61; CHECK: # %bb.0: 62; CHECK-NEXT: vslh 2, 2, 3 63; CHECK-NEXT: blr 64 %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 65 %shl = shl <8 x i16> %a, %rem 66 ret <8 x i16> %shl 67} 68 69define <4 x i32> @test012(<4 x i32> %a, <4 x i32> %b) { 70; CHECK-LABEL: test012: 71; CHECK: # %bb.0: 72; CHECK-NEXT: vslw 2, 2, 3 73; CHECK-NEXT: blr 74 %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31> 75 %shl = shl <4 x i32> %a, %rem 76 ret <4 x i32> %shl 77} 78 79define <2 x i64> @test013(<2 x i64> %a, <2 x i64> %b) { 80; CHECK-LABEL: test013: 81; CHECK: # %bb.0: 82; CHECK-NEXT: vsld 2, 2, 3 83; CHECK-NEXT: blr 84 %rem = and <2 x i64> %b, <i64 63, i64 63> 85 %shl = shl <2 x i64> %a, %rem 86 ret <2 x i64> %shl 87} 88 89define i8 @test100(i8 %a, i8 %b) { 90; CHECK-LABEL: test100: 91; CHECK: # %bb.0: 92; CHECK-NEXT: rlwinm 3, 3, 0, 24, 31 93; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31 94; CHECK-NEXT: srw 3, 3, 4 95; CHECK-NEXT: blr 96 %rem = and i8 %b, 7 97 %lshr = lshr i8 %a, %rem 98 ret i8 %lshr 99} 100 101define i16 @test101(i16 %a, i16 %b) { 102; CHECK-LABEL: test101: 103; CHECK: # %bb.0: 104; CHECK-NEXT: rlwinm 3, 3, 0, 16, 31 105; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 106; CHECK-NEXT: srw 3, 3, 4 107; CHECK-NEXT: blr 108 %rem = and i16 %b, 15 109 %lshr = lshr i16 %a, %rem 110 ret i16 %lshr 111} 112 113define i32 @test102(i32 %a, i32 %b) { 114; CHECK-LABEL: test102: 115; CHECK: # %bb.0: 116; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31 117; CHECK-NEXT: srw 3, 3, 4 118; CHECK-NEXT: blr 119 %rem = and i32 %b, 31 120 %lshr = lshr i32 %a, %rem 121 ret i32 %lshr 122} 123 124define i64 @test103(i64 %a, i64 %b) { 125; CHECK-LABEL: test103: 126; CHECK: # %bb.0: 127; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31 128; CHECK-NEXT: srd 3, 3, 4 129; CHECK-NEXT: blr 130 %rem = and i64 %b, 63 131 %lshr = lshr i64 %a, %rem 132 ret i64 %lshr 133} 134 135define <16 x i8> @test110(<16 x i8> %a, <16 x i8> %b) { 136; CHECK-LABEL: test110: 137; CHECK: # %bb.0: 138; CHECK-NEXT: vsrb 2, 2, 3 139; CHECK-NEXT: blr 140 %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 141 %lshr = lshr <16 x i8> %a, %rem 142 ret <16 x i8> %lshr 143} 144 145define <8 x i16> @test111(<8 x i16> %a, <8 x i16> %b) { 146; CHECK-LABEL: test111: 147; CHECK: # %bb.0: 148; CHECK-NEXT: vsrh 2, 2, 3 149; CHECK-NEXT: blr 150 %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 151 %lshr = lshr <8 x i16> %a, %rem 152 ret <8 x i16> %lshr 153} 154 155define <4 x i32> @test112(<4 x i32> %a, <4 x i32> %b) { 156; CHECK-LABEL: test112: 157; CHECK: # %bb.0: 158; CHECK-NEXT: vsrw 2, 2, 3 159; CHECK-NEXT: blr 160 %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31> 161 %lshr = lshr <4 x i32> %a, %rem 162 ret <4 x i32> %lshr 163} 164 165define <2 x i64> @test113(<2 x i64> %a, <2 x i64> %b) { 166; CHECK-LABEL: test113: 167; CHECK: # %bb.0: 168; CHECK-NEXT: vsrd 2, 2, 3 169; CHECK-NEXT: blr 170 %rem = and <2 x i64> %b, <i64 63, i64 63> 171 %lshr = lshr <2 x i64> %a, %rem 172 ret <2 x i64> %lshr 173} 174 175define i8 @test200(i8 %a, i8 %b) { 176; CHECK-LABEL: test200: 177; CHECK: # %bb.0: 178; CHECK-NEXT: extsb 3, 3 179; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31 180; CHECK-NEXT: sraw 3, 3, 4 181; CHECK-NEXT: blr 182 %rem = and i8 %b, 7 183 %ashr = ashr i8 %a, %rem 184 ret i8 %ashr 185} 186 187define i16 @test201(i16 %a, i16 %b) { 188; CHECK-LABEL: test201: 189; CHECK: # %bb.0: 190; CHECK-NEXT: extsh 3, 3 191; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 192; CHECK-NEXT: sraw 3, 3, 4 193; CHECK-NEXT: blr 194 %rem = and i16 %b, 15 195 %ashr = ashr i16 %a, %rem 196 ret i16 %ashr 197} 198 199define i32 @test202(i32 %a, i32 %b) { 200; CHECK-LABEL: test202: 201; CHECK: # %bb.0: 202; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31 203; CHECK-NEXT: sraw 3, 3, 4 204; CHECK-NEXT: blr 205 %rem = and i32 %b, 31 206 %ashr = ashr i32 %a, %rem 207 ret i32 %ashr 208} 209 210define i64 @test203(i64 %a, i64 %b) { 211; CHECK-LABEL: test203: 212; CHECK: # %bb.0: 213; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31 214; CHECK-NEXT: srad 3, 3, 4 215; CHECK-NEXT: blr 216 %rem = and i64 %b, 63 217 %ashr = ashr i64 %a, %rem 218 ret i64 %ashr 219} 220 221define <16 x i8> @test210(<16 x i8> %a, <16 x i8> %b) { 222; CHECK-LABEL: test210: 223; CHECK: # %bb.0: 224; CHECK-NEXT: vsrab 2, 2, 3 225; CHECK-NEXT: blr 226 %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 227 %ashr = ashr <16 x i8> %a, %rem 228 ret <16 x i8> %ashr 229} 230 231define <8 x i16> @test211(<8 x i16> %a, <8 x i16> %b) { 232; CHECK-LABEL: test211: 233; CHECK: # %bb.0: 234; CHECK-NEXT: vsrah 2, 2, 3 235; CHECK-NEXT: blr 236 %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 237 %ashr = ashr <8 x i16> %a, %rem 238 ret <8 x i16> %ashr 239} 240 241define <4 x i32> @test212(<4 x i32> %a, <4 x i32> %b) { 242; CHECK-LABEL: test212: 243; CHECK: # %bb.0: 244; CHECK-NEXT: vsraw 2, 2, 3 245; CHECK-NEXT: blr 246 %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31> 247 %ashr = ashr <4 x i32> %a, %rem 248 ret <4 x i32> %ashr 249} 250 251define <2 x i64> @test213(<2 x i64> %a, <2 x i64> %b) { 252; CHECK-LABEL: test213: 253; CHECK: # %bb.0: 254; CHECK-NEXT: vsrad 2, 2, 3 255; CHECK-NEXT: blr 256 %rem = and <2 x i64> %b, <i64 63, i64 63> 257 %ashr = ashr <2 x i64> %a, %rem 258 ret <2 x i64> %ashr 259} 260