1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s 3 4--- | 5 define i1 @test_and_i1() { 6 %ret = and i1 undef, undef 7 ret i1 %ret 8 } 9 10 define i8 @test_and_i8() { 11 %ret = and i8 undef, undef 12 ret i8 %ret 13 } 14 15 define i16 @test_and_i16() { 16 %ret = and i16 undef, undef 17 ret i16 %ret 18 } 19 20 define i32 @test_and_i32() { 21 %ret = and i32 undef, undef 22 ret i32 %ret 23 } 24 25 define i64 @test_and_i64() { 26 %ret = and i64 undef, undef 27 ret i64 %ret 28 } 29 30... 31--- 32name: test_and_i1 33alignment: 4 34legalized: false 35regBankSelected: false 36registers: 37 - { id: 0, class: _, preferred-register: '' } 38 - { id: 1, class: _, preferred-register: '' } 39 - { id: 2, class: _, preferred-register: '' } 40body: | 41 bb.1 (%ir-block.0): 42 43 ; CHECK-LABEL: name: test_and_i1 44 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx 45 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 46 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 47 ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[TRUNC1]] 48 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s8) 49 ; CHECK: $eax = COPY [[ANYEXT]](s32) 50 ; CHECK: RET 0 51 %0(s32) = COPY $edx 52 %1(s1) = G_TRUNC %0(s32) 53 %2(s1) = G_AND %1, %1 54 %3:_(s32) = G_ANYEXT %2 55 $eax = COPY %3 56 RET 0 57... 58--- 59name: test_and_i8 60alignment: 4 61legalized: false 62regBankSelected: false 63registers: 64 - { id: 0, class: _, preferred-register: '' } 65 - { id: 1, class: _, preferred-register: '' } 66liveins: 67fixedStack: 68stack: 69constants: 70body: | 71 bb.1 (%ir-block.0): 72 ; CHECK-LABEL: name: test_and_i8 73 ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF 74 ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[DEF]], [[DEF]] 75 ; CHECK: $al = COPY [[AND]](s8) 76 ; CHECK: RET 0, implicit $al 77 %0(s8) = IMPLICIT_DEF 78 %1(s8) = G_AND %0, %0 79 $al = COPY %1(s8) 80 RET 0, implicit $al 81 82... 83--- 84name: test_and_i16 85alignment: 4 86legalized: false 87regBankSelected: false 88registers: 89 - { id: 0, class: _, preferred-register: '' } 90 - { id: 1, class: _, preferred-register: '' } 91liveins: 92fixedStack: 93stack: 94constants: 95body: | 96 bb.1 (%ir-block.0): 97 ; CHECK-LABEL: name: test_and_i16 98 ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF 99 ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[DEF]], [[DEF]] 100 ; CHECK: $ax = COPY [[AND]](s16) 101 ; CHECK: RET 0, implicit $ax 102 %0(s16) = IMPLICIT_DEF 103 %1(s16) = G_AND %0, %0 104 $ax = COPY %1(s16) 105 RET 0, implicit $ax 106 107... 108--- 109name: test_and_i32 110alignment: 4 111legalized: false 112regBankSelected: false 113registers: 114 - { id: 0, class: _, preferred-register: '' } 115 - { id: 1, class: _, preferred-register: '' } 116liveins: 117fixedStack: 118stack: 119constants: 120body: | 121 bb.1 (%ir-block.0): 122 ; CHECK-LABEL: name: test_and_i32 123 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF 124 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[DEF]] 125 ; CHECK: $eax = COPY [[AND]](s32) 126 ; CHECK: RET 0, implicit $eax 127 %0(s32) = IMPLICIT_DEF 128 %1(s32) = G_AND %0, %0 129 $eax = COPY %1(s32) 130 RET 0, implicit $eax 131 132... 133--- 134name: test_and_i64 135alignment: 4 136legalized: false 137regBankSelected: false 138registers: 139 - { id: 0, class: _, preferred-register: '' } 140 - { id: 1, class: _, preferred-register: '' } 141liveins: 142fixedStack: 143stack: 144constants: 145body: | 146 bb.1 (%ir-block.0): 147 ; CHECK-LABEL: name: test_and_i64 148 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF 149 ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]] 150 ; CHECK: $rax = COPY [[AND]](s64) 151 ; CHECK: RET 0, implicit $rax 152 %0(s64) = IMPLICIT_DEF 153 %1(s64) = G_AND %0, %0 154 $rax = COPY %1(s64) 155 RET 0, implicit $rax 156 157... 158