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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
3
4--- |
5  define i64 @test_sext_i1(i8 %a) {
6    %val = trunc i8 %a to i1
7    %r = sext i1 %val to i64
8    ret i64 %r
9  }
10
11  define i64 @test_sext_i8(i8 %val) {
12    %r = sext i8 %val to i64
13    ret i64 %r
14  }
15
16  define i64 @test_sext_i16(i16 %val) {
17    %r = sext i16 %val to i64
18    ret i64 %r
19  }
20
21  define i64 @test_sext_i32(i32 %val) {
22    %r = sext i32 %val to i64
23    ret i64 %r
24  }
25
26  define i64 @test_zext_i1(i8 %a) {
27    %val = trunc i8 %a to i1
28    %r = zext i1 %val to i64
29    ret i64 %r
30  }
31
32  define i64 @test_zext_i8(i8 %val) {
33    %r = zext i8 %val to i64
34    ret i64 %r
35  }
36
37  define i64 @test_zext_i16(i16 %val) {
38    %r = zext i16 %val to i64
39    ret i64 %r
40  }
41
42  define i64 @test_zext_i32(i32 %val) {
43    %r = zext i32 %val to i64
44    ret i64 %r
45  }
46
47  define void @test_anyext_i1(i8 %a) {
48    ret void
49  }
50
51  define void @test_anyext_i8(i8 %val) {
52    ret void
53  }
54
55  define void @test_anyext_i16(i16 %val) {
56    ret void
57  }
58
59  define void @test_anyext_i32(i32 %val) {
60    ret void
61  }
62
63
64...
65---
66name:            test_sext_i1
67alignment:       4
68legalized:       false
69regBankSelected: false
70registers:
71  - { id: 0, class: _ }
72  - { id: 1, class: _ }
73  - { id: 2, class: _ }
74body:             |
75  bb.1 (%ir-block.0):
76    liveins: $edi
77
78    ; CHECK-LABEL: name: test_sext_i1
79    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
80    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
81    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
82    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]]
83    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]]
84    ; CHECK: $rax = COPY [[ASHR]](s64)
85    ; CHECK: RET 0, implicit $rax
86    %0(s8) = COPY $dil
87    %1(s1) = G_TRUNC %0(s8)
88    %2(s64) = G_SEXT %1(s1)
89    $rax = COPY %2(s64)
90    RET 0, implicit $rax
91
92...
93---
94name:            test_sext_i8
95alignment:       4
96legalized:       false
97regBankSelected: false
98registers:
99  - { id: 0, class: _ }
100  - { id: 1, class: _ }
101body:             |
102  bb.1 (%ir-block.0):
103    liveins: $edi
104
105    ; CHECK-LABEL: name: test_sext_i8
106    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
107    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s8)
108    ; CHECK: $rax = COPY [[SEXT]](s64)
109    ; CHECK: RET 0, implicit $rax
110    %0(s8) = COPY $dil
111    %1(s64) = G_SEXT %0(s8)
112    $rax = COPY %1(s64)
113    RET 0, implicit $rax
114
115...
116---
117name:            test_sext_i16
118alignment:       4
119legalized:       false
120regBankSelected: false
121registers:
122  - { id: 0, class: _ }
123  - { id: 1, class: _ }
124body:             |
125  bb.1 (%ir-block.0):
126    liveins: $edi
127
128    ; CHECK-LABEL: name: test_sext_i16
129    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
130    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
131    ; CHECK: $rax = COPY [[SEXT]](s64)
132    ; CHECK: RET 0, implicit $rax
133    %0(s16) = COPY $di
134    %1(s64) = G_SEXT %0(s16)
135    $rax = COPY %1(s64)
136    RET 0, implicit $rax
137
138...
139---
140name:            test_sext_i32
141alignment:       4
142legalized:       false
143regBankSelected: false
144registers:
145  - { id: 0, class: _ }
146  - { id: 1, class: _ }
147body:             |
148  bb.1 (%ir-block.0):
149    liveins: $edi
150
151    ; CHECK-LABEL: name: test_sext_i32
152    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
153    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
154    ; CHECK: $rax = COPY [[SEXT]](s64)
155    ; CHECK: RET 0, implicit $rax
156    %0(s32) = COPY $edi
157    %1(s64) = G_SEXT %0(s32)
158    $rax = COPY %1(s64)
159    RET 0, implicit $rax
160
161...
162---
163name:            test_zext_i1
164alignment:       4
165legalized:       false
166regBankSelected: false
167registers:
168  - { id: 0, class: _ }
169  - { id: 1, class: _ }
170  - { id: 2, class: _ }
171body:             |
172  bb.1 (%ir-block.0):
173    liveins: $edi
174
175    ; CHECK-LABEL: name: test_zext_i1
176    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
177    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
178    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
179    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
180    ; CHECK: $rax = COPY [[AND]](s64)
181    ; CHECK: RET 0, implicit $rax
182    %0(s8) = COPY $dil
183    %1(s1) = G_TRUNC %0(s8)
184    %2(s64) = G_ZEXT %1(s1)
185    $rax = COPY %2(s64)
186    RET 0, implicit $rax
187
188...
189---
190name:            test_zext_i8
191alignment:       4
192legalized:       false
193regBankSelected: false
194registers:
195  - { id: 0, class: _ }
196  - { id: 1, class: _ }
197body:             |
198  bb.1 (%ir-block.0):
199    liveins: $edi
200
201    ; CHECK-LABEL: name: test_zext_i8
202    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
203    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s8)
204    ; CHECK: $rax = COPY [[ZEXT]](s64)
205    ; CHECK: RET 0, implicit $rax
206    %0(s8) = COPY $dil
207    %1(s64) = G_ZEXT %0(s8)
208    $rax = COPY %1(s64)
209    RET 0, implicit $rax
210
211...
212---
213name:            test_zext_i16
214alignment:       4
215legalized:       false
216regBankSelected: false
217registers:
218  - { id: 0, class: _ }
219  - { id: 1, class: _ }
220body:             |
221  bb.1 (%ir-block.0):
222    liveins: $edi
223
224    ; CHECK-LABEL: name: test_zext_i16
225    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
226    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
227    ; CHECK: $rax = COPY [[ZEXT]](s64)
228    ; CHECK: RET 0, implicit $rax
229    %0(s16) = COPY $di
230    %1(s64) = G_ZEXT %0(s16)
231    $rax = COPY %1(s64)
232    RET 0, implicit $rax
233
234...
235---
236name:            test_zext_i32
237alignment:       4
238legalized:       false
239regBankSelected: false
240registers:
241  - { id: 0, class: _ }
242  - { id: 1, class: _ }
243body:             |
244  bb.1 (%ir-block.0):
245    liveins: $edi
246
247    ; CHECK-LABEL: name: test_zext_i32
248    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
249    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
250    ; CHECK: $rax = COPY [[ZEXT]](s64)
251    ; CHECK: RET 0, implicit $rax
252    %0(s32) = COPY $edi
253    %1(s64) = G_ZEXT %0(s32)
254    $rax = COPY %1(s64)
255    RET 0, implicit $rax
256
257...
258---
259name:            test_anyext_i1
260alignment:       4
261legalized:       false
262regBankSelected: false
263registers:
264  - { id: 0, class: _ }
265  - { id: 1, class: _ }
266  - { id: 2, class: _ }
267body:             |
268  bb.1 (%ir-block.0):
269    liveins: $edi
270
271    ; CHECK-LABEL: name: test_anyext_i1
272    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
273    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
274    ; CHECK: $rax = COPY [[ANYEXT]](s64)
275    ; CHECK: RET 0, implicit $rax
276    %0(s8) = COPY $dil
277    %1(s1) = G_TRUNC %0(s8)
278    %2(s64) = G_ANYEXT %1(s1)
279    $rax = COPY %2(s64)
280    RET 0, implicit $rax
281
282...
283---
284name:            test_anyext_i8
285alignment:       4
286legalized:       false
287regBankSelected: false
288registers:
289  - { id: 0, class: _ }
290  - { id: 1, class: _ }
291body:             |
292  bb.1 (%ir-block.0):
293    liveins: $edi
294
295    ; CHECK-LABEL: name: test_anyext_i8
296    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
297    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
298    ; CHECK: $rax = COPY [[ANYEXT]](s64)
299    ; CHECK: RET 0, implicit $rax
300    %0(s8) = COPY $dil
301    %1(s64) = G_ANYEXT %0(s8)
302    $rax = COPY %1(s64)
303    RET 0, implicit $rax
304
305...
306---
307name:            test_anyext_i16
308alignment:       4
309legalized:       false
310regBankSelected: false
311registers:
312  - { id: 0, class: _ }
313  - { id: 1, class: _ }
314body:             |
315  bb.1 (%ir-block.0):
316    liveins: $edi
317
318    ; CHECK-LABEL: name: test_anyext_i16
319    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
320    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s16)
321    ; CHECK: $rax = COPY [[ANYEXT]](s64)
322    ; CHECK: RET 0, implicit $rax
323    %0(s16) = COPY $di
324    %1(s64) = G_ANYEXT %0(s16)
325    $rax = COPY %1(s64)
326    RET 0, implicit $rax
327
328...
329---
330name:            test_anyext_i32
331alignment:       4
332legalized:       false
333regBankSelected: false
334registers:
335  - { id: 0, class: _ }
336  - { id: 1, class: _ }
337body:             |
338  bb.1 (%ir-block.0):
339    liveins: $edi
340
341    ; CHECK-LABEL: name: test_anyext_i32
342    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
343    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
344    ; CHECK: $rax = COPY [[ANYEXT]](s64)
345    ; CHECK: RET 0, implicit $rax
346    %0(s32) = COPY $edi
347    %1(s64) = G_ANYEXT %0(s32)
348    $rax = COPY %1(s64)
349    RET 0, implicit $rax
350
351...
352
353