1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL 3--- | 4 define void @test_merge_v128() { 5 ret void 6 } 7 8 define void @test_merge_v256() { 9 ret void 10 } 11 12... 13--- 14name: test_merge_v128 15alignment: 4 16legalized: true 17regBankSelected: true 18registers: 19 - { id: 0, class: vecr } 20 - { id: 1, class: vecr } 21body: | 22 bb.1 (%ir-block.0): 23 24 ; ALL-LABEL: name: test_merge_v128 25 ; ALL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF 26 ; ALL: undef %2.sub_xmm:vr512 = COPY [[DEF]] 27 ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr %2, [[DEF]], 1 28 ; ALL: [[VINSERTF32x4Zrr1:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr]], [[DEF]], 2 29 ; ALL: [[VINSERTF32x4Zrr2:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr1]], [[DEF]], 3 30 ; ALL: $zmm0 = COPY [[VINSERTF32x4Zrr2]] 31 ; ALL: RET 0, implicit $zmm0 32 %0(<4 x s32>) = IMPLICIT_DEF 33 %1(<16 x s32>) = G_MERGE_VALUES %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>) 34 $zmm0 = COPY %1(<16 x s32>) 35 RET 0, implicit $zmm0 36 37... 38--- 39name: test_merge_v256 40alignment: 4 41legalized: true 42regBankSelected: true 43registers: 44 - { id: 0, class: vecr } 45 - { id: 1, class: vecr } 46body: | 47 bb.1 (%ir-block.0): 48 49 ; ALL-LABEL: name: test_merge_v256 50 ; ALL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF 51 ; ALL: undef %2.sub_ymm:vr512 = COPY [[DEF]] 52 ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr %2, [[DEF]], 1 53 ; ALL: $zmm0 = COPY [[VINSERTF64x4Zrr]] 54 ; ALL: RET 0, implicit $zmm0 55 %0(<8 x s32>) = IMPLICIT_DEF 56 %1(<16 x s32>) = G_MERGE_VALUES %0(<8 x s32>), %0(<8 x s32>) 57 $zmm0 = COPY %1(<16 x s32>) 58 RET 0, implicit $zmm0 59 60... 61 62