1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL 3--- | 4 define void @test_unmerge_v128() { 5 ret void 6 } 7 8 define void @test_unmerge_v256() { 9 ret void 10 } 11 12... 13--- 14name: test_unmerge_v128 15alignment: 4 16legalized: true 17regBankSelected: true 18registers: 19 - { id: 0, class: vecr } 20 - { id: 1, class: vecr } 21 - { id: 2, class: vecr } 22 - { id: 3, class: vecr } 23 - { id: 4, class: vecr } 24body: | 25 bb.1 (%ir-block.0): 26 27 ; ALL-LABEL: name: test_unmerge_v128 28 ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF 29 ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY [[DEF]].sub_xmm 30 ; ALL: [[VEXTRACTF32x4Zrr:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrr [[DEF]], 1 31 ; ALL: [[VEXTRACTF32x4Zrr1:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrr [[DEF]], 2 32 ; ALL: [[VEXTRACTF32x4Zrr2:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrr [[DEF]], 3 33 ; ALL: $xmm0 = COPY [[COPY]] 34 ; ALL: RET 0, implicit $xmm0 35 %0(<16 x s32>) = IMPLICIT_DEF 36 %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>), %4(<4 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>) 37 $xmm0 = COPY %1(<4 x s32>) 38 RET 0, implicit $xmm0 39 40... 41--- 42name: test_unmerge_v256 43alignment: 4 44legalized: true 45regBankSelected: true 46registers: 47 - { id: 0, class: vecr } 48 - { id: 1, class: vecr } 49 - { id: 2, class: vecr } 50body: | 51 bb.1 (%ir-block.0): 52 53 ; ALL-LABEL: name: test_unmerge_v256 54 ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF 55 ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY [[DEF]].sub_ymm 56 ; ALL: [[VEXTRACTF64x4Zrr:%[0-9]+]]:vr256x = VEXTRACTF64x4Zrr [[DEF]], 1 57 ; ALL: $ymm0 = COPY [[COPY]] 58 ; ALL: RET 0, implicit $ymm0 59 %0(<16 x s32>) = IMPLICIT_DEF 60 %1(<8 x s32>), %2(<8 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>) 61 $ymm0 = COPY %1(<8 x s32>) 62 RET 0, implicit $ymm0 63 64... 65