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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1,-avx < %s | FileCheck %s --check-prefix=SSE41
3; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx,-avx2 < %s   | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
4; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512dq,+avx512bw < %s   | FileCheck %s --check-prefix=AVX --check-prefix=AVX512
5
6define i32 @veccond128(<4 x i32> %input) {
7; SSE41-LABEL: veccond128:
8; SSE41:       # %bb.0: # %entry
9; SSE41-NEXT:    ptest %xmm0, %xmm0
10; SSE41-NEXT:    je .LBB0_2
11; SSE41-NEXT:  # %bb.1: # %if-true-block
12; SSE41-NEXT:    xorl %eax, %eax
13; SSE41-NEXT:    retq
14; SSE41-NEXT:  .LBB0_2: # %endif-block
15; SSE41-NEXT:    movl $1, %eax
16; SSE41-NEXT:    retq
17;
18; AVX-LABEL: veccond128:
19; AVX:       # %bb.0: # %entry
20; AVX-NEXT:    vptest %xmm0, %xmm0
21; AVX-NEXT:    je .LBB0_2
22; AVX-NEXT:  # %bb.1: # %if-true-block
23; AVX-NEXT:    xorl %eax, %eax
24; AVX-NEXT:    retq
25; AVX-NEXT:  .LBB0_2: # %endif-block
26; AVX-NEXT:    movl $1, %eax
27; AVX-NEXT:    retq
28entry:
29  %0 = bitcast <4 x i32> %input to i128
30  %1 = icmp ne i128 %0, 0
31  br i1 %1, label %if-true-block, label %endif-block
32if-true-block:
33  ret i32 0
34endif-block:
35  ret i32 1
36}
37
38define i32 @veccond256(<8 x i32> %input) {
39; SSE41-LABEL: veccond256:
40; SSE41:       # %bb.0: # %entry
41; SSE41-NEXT:    por %xmm1, %xmm0
42; SSE41-NEXT:    ptest %xmm0, %xmm0
43; SSE41-NEXT:    je .LBB1_2
44; SSE41-NEXT:  # %bb.1: # %if-true-block
45; SSE41-NEXT:    xorl %eax, %eax
46; SSE41-NEXT:    retq
47; SSE41-NEXT:  .LBB1_2: # %endif-block
48; SSE41-NEXT:    movl $1, %eax
49; SSE41-NEXT:    retq
50;
51; AVX-LABEL: veccond256:
52; AVX:       # %bb.0: # %entry
53; AVX-NEXT:    vptest %ymm0, %ymm0
54; AVX-NEXT:    je .LBB1_2
55; AVX-NEXT:  # %bb.1: # %if-true-block
56; AVX-NEXT:    xorl %eax, %eax
57; AVX-NEXT:    vzeroupper
58; AVX-NEXT:    retq
59; AVX-NEXT:  .LBB1_2: # %endif-block
60; AVX-NEXT:    movl $1, %eax
61; AVX-NEXT:    vzeroupper
62; AVX-NEXT:    retq
63entry:
64  %0 = bitcast <8 x i32> %input to i256
65  %1 = icmp ne i256 %0, 0
66  br i1 %1, label %if-true-block, label %endif-block
67if-true-block:
68  ret i32 0
69endif-block:
70  ret i32 1
71}
72
73define i32 @veccond512(<16 x i32> %input) {
74; SSE41-LABEL: veccond512:
75; SSE41:       # %bb.0: # %entry
76; SSE41-NEXT:    por %xmm3, %xmm1
77; SSE41-NEXT:    por %xmm2, %xmm1
78; SSE41-NEXT:    por %xmm0, %xmm1
79; SSE41-NEXT:    ptest %xmm1, %xmm1
80; SSE41-NEXT:    je .LBB2_2
81; SSE41-NEXT:  # %bb.1: # %if-true-block
82; SSE41-NEXT:    xorl %eax, %eax
83; SSE41-NEXT:    retq
84; SSE41-NEXT:  .LBB2_2: # %endif-block
85; SSE41-NEXT:    movl $1, %eax
86; SSE41-NEXT:    retq
87;
88; AVX1-LABEL: veccond512:
89; AVX1:       # %bb.0: # %entry
90; AVX1-NEXT:    vorps %ymm1, %ymm0, %ymm0
91; AVX1-NEXT:    vptest %ymm0, %ymm0
92; AVX1-NEXT:    je .LBB2_2
93; AVX1-NEXT:  # %bb.1: # %if-true-block
94; AVX1-NEXT:    xorl %eax, %eax
95; AVX1-NEXT:    vzeroupper
96; AVX1-NEXT:    retq
97; AVX1-NEXT:  .LBB2_2: # %endif-block
98; AVX1-NEXT:    movl $1, %eax
99; AVX1-NEXT:    vzeroupper
100; AVX1-NEXT:    retq
101;
102; AVX512-LABEL: veccond512:
103; AVX512:       # %bb.0: # %entry
104; AVX512-NEXT:    vextracti32x4 $3, %zmm0, %xmm1
105; AVX512-NEXT:    vmovq %xmm1, %rax
106; AVX512-NEXT:    vextracti128 $1, %ymm0, %xmm2
107; AVX512-NEXT:    vmovq %xmm2, %rcx
108; AVX512-NEXT:    orq %rax, %rcx
109; AVX512-NEXT:    vextracti32x4 $2, %zmm0, %xmm3
110; AVX512-NEXT:    vmovq %xmm3, %rax
111; AVX512-NEXT:    orq %rcx, %rax
112; AVX512-NEXT:    vmovq %xmm0, %rcx
113; AVX512-NEXT:    orq %rax, %rcx
114; AVX512-NEXT:    vpextrq $1, %xmm1, %rax
115; AVX512-NEXT:    vpextrq $1, %xmm2, %rdx
116; AVX512-NEXT:    orq %rax, %rdx
117; AVX512-NEXT:    vpextrq $1, %xmm3, %rax
118; AVX512-NEXT:    orq %rdx, %rax
119; AVX512-NEXT:    vpextrq $1, %xmm0, %rdx
120; AVX512-NEXT:    orq %rax, %rdx
121; AVX512-NEXT:    orq %rcx, %rdx
122; AVX512-NEXT:    je .LBB2_2
123; AVX512-NEXT:  # %bb.1: # %if-true-block
124; AVX512-NEXT:    xorl %eax, %eax
125; AVX512-NEXT:    vzeroupper
126; AVX512-NEXT:    retq
127; AVX512-NEXT:  .LBB2_2: # %endif-block
128; AVX512-NEXT:    movl $1, %eax
129; AVX512-NEXT:    vzeroupper
130; AVX512-NEXT:    retq
131entry:
132  %0 = bitcast <16 x i32> %input to i512
133  %1 = icmp ne i512 %0, 0
134  br i1 %1, label %if-true-block, label %endif-block
135if-true-block:
136  ret i32 0
137endif-block:
138  ret i32 1
139}
140
141define i32 @vectest128(<4 x i32> %input) {
142; SSE41-LABEL: vectest128:
143; SSE41:       # %bb.0:
144; SSE41-NEXT:    xorl %eax, %eax
145; SSE41-NEXT:    ptest %xmm0, %xmm0
146; SSE41-NEXT:    setne %al
147; SSE41-NEXT:    retq
148;
149; AVX-LABEL: vectest128:
150; AVX:       # %bb.0:
151; AVX-NEXT:    xorl %eax, %eax
152; AVX-NEXT:    vptest %xmm0, %xmm0
153; AVX-NEXT:    setne %al
154; AVX-NEXT:    retq
155  %t0 = bitcast <4 x i32> %input to i128
156  %t1 = icmp ne i128 %t0, 0
157  %t2 = zext i1 %t1 to i32
158  ret i32 %t2
159}
160
161define i32 @vectest256(<8 x i32> %input) {
162; SSE41-LABEL: vectest256:
163; SSE41:       # %bb.0:
164; SSE41-NEXT:    por %xmm1, %xmm0
165; SSE41-NEXT:    xorl %eax, %eax
166; SSE41-NEXT:    ptest %xmm0, %xmm0
167; SSE41-NEXT:    setne %al
168; SSE41-NEXT:    retq
169;
170; AVX-LABEL: vectest256:
171; AVX:       # %bb.0:
172; AVX-NEXT:    xorl %eax, %eax
173; AVX-NEXT:    vptest %ymm0, %ymm0
174; AVX-NEXT:    setne %al
175; AVX-NEXT:    vzeroupper
176; AVX-NEXT:    retq
177  %t0 = bitcast <8 x i32> %input to i256
178  %t1 = icmp ne i256 %t0, 0
179  %t2 = zext i1 %t1 to i32
180  ret i32 %t2
181}
182
183define i32 @vectest512(<16 x i32> %input) {
184; SSE41-LABEL: vectest512:
185; SSE41:       # %bb.0:
186; SSE41-NEXT:    por %xmm3, %xmm1
187; SSE41-NEXT:    por %xmm2, %xmm1
188; SSE41-NEXT:    por %xmm0, %xmm1
189; SSE41-NEXT:    xorl %eax, %eax
190; SSE41-NEXT:    ptest %xmm1, %xmm1
191; SSE41-NEXT:    setne %al
192; SSE41-NEXT:    retq
193;
194; AVX1-LABEL: vectest512:
195; AVX1:       # %bb.0:
196; AVX1-NEXT:    vorps %ymm1, %ymm0, %ymm0
197; AVX1-NEXT:    xorl %eax, %eax
198; AVX1-NEXT:    vptest %ymm0, %ymm0
199; AVX1-NEXT:    setne %al
200; AVX1-NEXT:    vzeroupper
201; AVX1-NEXT:    retq
202;
203; AVX512-LABEL: vectest512:
204; AVX512:       # %bb.0:
205; AVX512-NEXT:    vextracti32x4 $3, %zmm0, %xmm1
206; AVX512-NEXT:    vmovq %xmm1, %rax
207; AVX512-NEXT:    vextracti128 $1, %ymm0, %xmm2
208; AVX512-NEXT:    vmovq %xmm2, %rcx
209; AVX512-NEXT:    orq %rax, %rcx
210; AVX512-NEXT:    vextracti32x4 $2, %zmm0, %xmm3
211; AVX512-NEXT:    vmovq %xmm3, %rax
212; AVX512-NEXT:    orq %rcx, %rax
213; AVX512-NEXT:    vmovq %xmm0, %rcx
214; AVX512-NEXT:    orq %rax, %rcx
215; AVX512-NEXT:    vpextrq $1, %xmm1, %rax
216; AVX512-NEXT:    vpextrq $1, %xmm2, %rdx
217; AVX512-NEXT:    orq %rax, %rdx
218; AVX512-NEXT:    vpextrq $1, %xmm3, %rax
219; AVX512-NEXT:    orq %rdx, %rax
220; AVX512-NEXT:    vpextrq $1, %xmm0, %rdx
221; AVX512-NEXT:    orq %rax, %rdx
222; AVX512-NEXT:    xorl %eax, %eax
223; AVX512-NEXT:    orq %rcx, %rdx
224; AVX512-NEXT:    setne %al
225; AVX512-NEXT:    vzeroupper
226; AVX512-NEXT:    retq
227  %t0 = bitcast <16 x i32> %input to i512
228  %t1 = icmp ne i512 %t0, 0
229  %t2 = zext i1 %t1 to i32
230  ret i32 %t2
231}
232
233define i32 @vecsel128(<4 x i32> %input, i32 %a, i32 %b) {
234; SSE41-LABEL: vecsel128:
235; SSE41:       # %bb.0:
236; SSE41-NEXT:    ptest %xmm0, %xmm0
237; SSE41-NEXT:    cmovel %esi, %edi
238; SSE41-NEXT:    movl %edi, %eax
239; SSE41-NEXT:    retq
240;
241; AVX-LABEL: vecsel128:
242; AVX:       # %bb.0:
243; AVX-NEXT:    vptest %xmm0, %xmm0
244; AVX-NEXT:    cmovel %esi, %edi
245; AVX-NEXT:    movl %edi, %eax
246; AVX-NEXT:    retq
247  %t0 = bitcast <4 x i32> %input to i128
248  %t1 = icmp ne i128 %t0, 0
249  %t2 = select i1 %t1, i32 %a, i32 %b
250  ret i32 %t2
251}
252
253define i32 @vecsel256(<8 x i32> %input, i32 %a, i32 %b) {
254; SSE41-LABEL: vecsel256:
255; SSE41:       # %bb.0:
256; SSE41-NEXT:    por %xmm1, %xmm0
257; SSE41-NEXT:    ptest %xmm0, %xmm0
258; SSE41-NEXT:    cmovel %esi, %edi
259; SSE41-NEXT:    movl %edi, %eax
260; SSE41-NEXT:    retq
261;
262; AVX-LABEL: vecsel256:
263; AVX:       # %bb.0:
264; AVX-NEXT:    vptest %ymm0, %ymm0
265; AVX-NEXT:    cmovel %esi, %edi
266; AVX-NEXT:    movl %edi, %eax
267; AVX-NEXT:    vzeroupper
268; AVX-NEXT:    retq
269  %t0 = bitcast <8 x i32> %input to i256
270  %t1 = icmp ne i256 %t0, 0
271  %t2 = select i1 %t1, i32 %a, i32 %b
272  ret i32 %t2
273}
274
275define i32 @vecsel512(<16 x i32> %input, i32 %a, i32 %b) {
276; SSE41-LABEL: vecsel512:
277; SSE41:       # %bb.0:
278; SSE41-NEXT:    por %xmm3, %xmm1
279; SSE41-NEXT:    por %xmm2, %xmm1
280; SSE41-NEXT:    por %xmm0, %xmm1
281; SSE41-NEXT:    ptest %xmm1, %xmm1
282; SSE41-NEXT:    cmovel %esi, %edi
283; SSE41-NEXT:    movl %edi, %eax
284; SSE41-NEXT:    retq
285;
286; AVX1-LABEL: vecsel512:
287; AVX1:       # %bb.0:
288; AVX1-NEXT:    vorps %ymm1, %ymm0, %ymm0
289; AVX1-NEXT:    vptest %ymm0, %ymm0
290; AVX1-NEXT:    cmovel %esi, %edi
291; AVX1-NEXT:    movl %edi, %eax
292; AVX1-NEXT:    vzeroupper
293; AVX1-NEXT:    retq
294;
295; AVX512-LABEL: vecsel512:
296; AVX512:       # %bb.0:
297; AVX512-NEXT:    vextracti32x4 $3, %zmm0, %xmm1
298; AVX512-NEXT:    vmovq %xmm1, %rax
299; AVX512-NEXT:    vextracti128 $1, %ymm0, %xmm2
300; AVX512-NEXT:    vmovq %xmm2, %rcx
301; AVX512-NEXT:    orq %rax, %rcx
302; AVX512-NEXT:    vextracti32x4 $2, %zmm0, %xmm3
303; AVX512-NEXT:    vmovq %xmm3, %rax
304; AVX512-NEXT:    orq %rcx, %rax
305; AVX512-NEXT:    vmovq %xmm0, %rcx
306; AVX512-NEXT:    orq %rax, %rcx
307; AVX512-NEXT:    vpextrq $1, %xmm1, %rax
308; AVX512-NEXT:    vpextrq $1, %xmm2, %rdx
309; AVX512-NEXT:    orq %rax, %rdx
310; AVX512-NEXT:    vpextrq $1, %xmm3, %rax
311; AVX512-NEXT:    orq %rdx, %rax
312; AVX512-NEXT:    vpextrq $1, %xmm0, %rdx
313; AVX512-NEXT:    orq %rax, %rdx
314; AVX512-NEXT:    orq %rcx, %rdx
315; AVX512-NEXT:    cmovel %esi, %edi
316; AVX512-NEXT:    movl %edi, %eax
317; AVX512-NEXT:    vzeroupper
318; AVX512-NEXT:    retq
319  %t0 = bitcast <16 x i32> %input to i512
320  %t1 = icmp ne i512 %t0, 0
321  %t2 = select i1 %t1, i32 %a, i32 %b
322  ret i32 %t2
323}
324