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1; Show that we know how to translate and.
2
3; NOTE: We use -O2 to get rid of memory stores.
4
5; REQUIRES: allow_dump
6
7; Compile using standalone assembler.
8; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
9; RUN:   | FileCheck %s --check-prefix=ASM
10
11; Show bytes in assembled standalone code.
12; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
13; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
14
15; Compile using integrated assembler.
16; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
17; RUN:   | FileCheck %s --check-prefix=IASM
18
19; Show bytes in assembled integrated code.
20; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
21; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
22
23define internal i32 @And1WithR0(i32 %p) {
24  %v = and i32 %p, 1
25  ret i32 %v
26}
27
28; ASM-LABEL:And1WithR0:
29; ASM-NEXT:.LAnd1WithR0$__0:
30; ASM-NEXT:     and     r0, r0, #1
31
32; DIS-LABEL:00000000 <And1WithR0>:
33; DIS-NEXT:   0:        e2000001
34
35; IASM-LABEL:And1WithR0:
36; IASM-NEXT:.LAnd1WithR0$__0:
37; IASM-NEXT:     .byte 0x1
38; IASM-NEXT:     .byte 0x0
39; IASM-NEXT:     .byte 0x0
40; IASM-NEXT:     .byte 0xe2
41
42define internal i32 @And2Regs(i32 %p1, i32 %p2) {
43  %v = and i32 %p1, %p2
44  ret i32 %v
45}
46
47; ASM-LABEL:And2Regs:
48; ASM-NEXT:.LAnd2Regs$__0:
49; ASM-NEXT:     and     r0, r0, r1
50
51; DIS-LABEL:00000010 <And2Regs>:
52; DIS-NEXT:  10:        e0000001
53
54; IASM-LABEL:And2Regs:
55; IASM-NEXT:.LAnd2Regs$__0:
56; IASM-NEXT:     .byte 0x1
57; IASM-NEXT:     .byte 0x0
58; IASM-NEXT:     .byte 0x0
59; IASM-NEXT:     .byte 0xe0
60
61define internal i64 @AndI64WithR0R1(i64 %p) {
62  %v = and i64 %p, 1
63  ret i64 %v
64}
65
66; ASM-LABEL:AndI64WithR0R1:
67; ASM-NEXT:.LAndI64WithR0R1$__0:
68; ASM-NEXT:     and     r0, r0, #1
69; ASM-NEXT:     and     r1, r1, #0
70
71; DIS-LABEL:00000020 <AndI64WithR0R1>:
72; DIS-NEXT:  20:        e2000001
73; DIS-NEXT:  24:        e2011000
74
75; IASM-LABEL:AndI64WithR0R1:
76; IASM-NEXT:.LAndI64WithR0R1$__0:
77; IASM-NEXT:     .byte 0x1
78; IASM-NEXT:     .byte 0x0
79; IASM-NEXT:     .byte 0x0
80; IASM-NEXT:     .byte 0xe2
81; IASM-NEXT:     .byte 0x0
82; IASM-NEXT:     .byte 0x10
83; IASM-NEXT:     .byte 0x1
84; IASM-NEXT:     .byte 0xe2
85
86define internal i64 @AndI64Regs(i64 %p1, i64 %p2) {
87  %v = and i64 %p1, %p2
88  ret i64 %v
89}
90
91; ASM-LABEL:AndI64Regs:
92; ASM-NEXT:.LAndI64Regs$__0:
93; ASM-NEXT:     and     r0, r0, r2
94; ASM-NEXT:     and     r1, r1, r3
95
96; DIS-LABEL:00000030 <AndI64Regs>:
97; DIS-NEXT:  30:        e0000002
98; DIS-NEXT:  34:        e0011003
99
100; IASM-LABEL:AndI64Regs:
101; IASM-NEXT:.LAndI64Regs$__0:
102; IASM-NEXT:     .byte 0x2
103; IASM-NEXT:     .byte 0x0
104; IASM-NEXT:     .byte 0x0
105; IASM-NEXT:     .byte 0xe0
106; IASM-NEXT:     .byte 0x3
107; IASM-NEXT:     .byte 0x10
108; IASM-NEXT:     .byte 0x1
109; IASM-NEXT:     .byte 0xe0
110