1; Test that we handle icmp and fcmp on vectors. 2 3; REQUIRES: allow_dump 4 5; Compile using standalone assembler. 6; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ 7; RUN: | FileCheck %s --check-prefix=ASM 8 9; Show bytes in assembled standalone code. 10; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ 11; RUN: --args -O2 | FileCheck %s --check-prefix=DIS 12 13; Compile using integrated assembler. 14; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \ 15; RUN: | FileCheck %s --check-prefix=IASM 16 17; Show bytes in assembled integrated code. 18; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ 19; RUN: --args -O2 | FileCheck %s --check-prefix=DIS 20 21define internal <4 x i32> @cmpEqV4I32(<4 x i32> %a, <4 x i32> %b) { 22; ASM-LABEL:cmpEqV4I32: 23; DIS-LABEL:00000000 <cmpEqV4I32>: 24; IASM-LABEL:cmpEqV4I32: 25 26entry: 27 %cmp = icmp eq <4 x i32> %a, %b 28 29; ASM: vceq.i32 q0, q0, q1 30; DIS: 0: f3200852 31; IASM-NOT: vceq 32 33 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 34 ret <4 x i32> %cmp.ret_ext 35} 36 37define internal <4 x i32> @cmpNeV4I32(<4 x i32> %a, <4 x i32> %b) { 38; ASM-LABEL:cmpNeV4I32: 39; DIS-LABEL:00000010 <cmpNeV4I32>: 40; IASM-LABEL:cmpNeV4I32: 41 42entry: 43 %cmp = icmp ne <4 x i32> %a, %b 44 45; ASM: vceq.i32 q0, q0, q1 46; ASM-NEXT: vmvn.i32 q0, q0 47; DIS: 10: f3200852 48; DIS-NEXT: 14: f3b005c0 49; IASM-NOT: vceq 50; IASM-NOT: vmvn 51 52 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 53 ret <4 x i32> %cmp.ret_ext 54} 55 56define internal <4 x i32> @cmpUgtV4I32(<4 x i32> %a, <4 x i32> %b) { 57; ASM-LABEL:cmpUgtV4I32: 58; DIS-LABEL:00000030 <cmpUgtV4I32>: 59; IASM-LABEL:cmpUgtV4I32: 60 61entry: 62 %cmp = icmp ugt <4 x i32> %a, %b 63 64; ASM: vcgt.u32 q0, q0, q1 65; DIS: 30: f3200342 66; IASM-NOT: vcgt 67 68 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 69 ret <4 x i32> %cmp.ret_ext 70} 71 72define internal <4 x i32> @cmpUgeV4I32(<4 x i32> %a, <4 x i32> %b) { 73; ASM-LABEL:cmpUgeV4I32: 74; DIS-LABEL:00000040 <cmpUgeV4I32>: 75; IASM-LABEL:cmpUgeV4I32: 76 77entry: 78 %cmp = icmp uge <4 x i32> %a, %b 79 80; ASM: vcge.u32 q0, q0, q1 81; DIS: 40: f3200352 82; IASM-NOT: vcge 83 84 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 85 ret <4 x i32> %cmp.ret_ext 86} 87 88define internal <4 x i32> @cmpUltV4I32(<4 x i32> %a, <4 x i32> %b) { 89; ASM-LABEL:cmpUltV4I32: 90; DIS-LABEL:00000050 <cmpUltV4I32>: 91; IASM-LABEL:cmpUltV4I32: 92 93entry: 94 %cmp = icmp ult <4 x i32> %a, %b 95 96; ASM: vcgt.u32 q1, q1, q0 97; DIS: 50: f3222340 98; IASM-NOT: vcgt 99 100 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 101 ret <4 x i32> %cmp.ret_ext 102} 103 104define internal <4 x i32> @cmpUleV4I32(<4 x i32> %a, <4 x i32> %b) { 105; ASM-LABEL:cmpUleV4I32: 106; DIS-LABEL:00000070 <cmpUleV4I32>: 107; IASM-LABEL:cmpUleV4I32: 108 109entry: 110 %cmp = icmp ule <4 x i32> %a, %b 111 112; ASM: vcge.u32 q1, q1, q0 113; DIS: 70: f3222350 114; IASM-NOT: vcge 115 116 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 117 ret <4 x i32> %cmp.ret_ext 118} 119 120define internal <4 x i32> @cmpSgtV4I32(<4 x i32> %a, <4 x i32> %b) { 121; ASM-LABEL:cmpSgtV4I32: 122; DIS-LABEL:00000090 <cmpSgtV4I32>: 123; IASM-LABEL:cmpSgtV4I32: 124 125entry: 126 %cmp = icmp sgt <4 x i32> %a, %b 127 128; ASM: vcgt.s32 q0, q0, q1 129; DIS: 90: f2200342 130; IASM-NOT: vcgt 131 132 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 133 ret <4 x i32> %cmp.ret_ext 134} 135 136define internal <4 x i32> @cmpSgeV4I32(<4 x i32> %a, <4 x i32> %b) { 137; ASM-LABEL:cmpSgeV4I32: 138; DIS-LABEL:000000a0 <cmpSgeV4I32>: 139; IASM-LABEL:cmpSgeV4I32: 140 141entry: 142 %cmp = icmp sge <4 x i32> %a, %b 143 144; ASM: vcge.s32 q0, q0, q1 145; DIS: a0: f2200352 146; IASM-NOT: vcge 147 148 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 149 ret <4 x i32> %cmp.ret_ext 150} 151 152define internal <4 x i32> @cmpSltV4I32(<4 x i32> %a, <4 x i32> %b) { 153; ASM-LABEL:cmpSltV4I32: 154; DIS-LABEL:000000b0 <cmpSltV4I32>: 155; IASM-LABEL:cmpSltV4I32: 156 157entry: 158 %cmp = icmp slt <4 x i32> %a, %b 159 160; ASM: vcgt.s32 q1, q1, q0 161; DIS: b0: f2222340 162; IASM-NOT: vcgt 163 164 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 165 ret <4 x i32> %cmp.ret_ext 166} 167 168define internal <4 x i32> @cmpSleV4I32(<4 x i32> %a, <4 x i32> %b) { 169; ASM-LABEL:cmpSleV4I32: 170; DIS-LABEL:000000d0 <cmpSleV4I32>: 171; IASM-LABEL:cmpSleV4I32: 172 173entry: 174 %cmp = icmp sle <4 x i32> %a, %b 175 176; ASM: vcge.s32 q1, q1, q0 177; DIS: d0: f2222350 178; IASM-NOT: vcge 179 180 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 181 ret <4 x i32> %cmp.ret_ext 182} 183 184define internal <4 x i32> @cmpEqV4I1(<4 x i32> %a, <4 x i32> %b) { 185; ASM-LABEL:cmpEqV4I1: 186; DIS-LABEL:000000f0 <cmpEqV4I1>: 187; IASM-LABEL:cmpEqV4I1: 188 189entry: 190 %a1 = trunc <4 x i32> %a to <4 x i1> 191 %b1 = trunc <4 x i32> %b to <4 x i1> 192 %cmp = icmp eq <4 x i1> %a1, %b1 193 194; ASM: vshl.u32 q0, q0, #31 195; ASM-NEXT: vshl.u32 q1, q1, #31 196; ASM-NEXT: vceq.i32 q0, q0, q1 197; DIS: f0: f2bf0550 198; DIS-NEXT: f4: f2bf2552 199; DIS-NEXT: f8: f3200852 200; IASM-NOT: vshl 201; IASM-NOT: vceq 202 203 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 204 ret <4 x i32> %cmp.ret_ext 205} 206 207define internal <4 x i32> @cmpNeV4I1(<4 x i32> %a, <4 x i32> %b) { 208; ASM-LABEL:cmpNeV4I1: 209; DIS-LABEL:00000110 <cmpNeV4I1>: 210; IASM-LABEL:cmpNeV4I1: 211 212entry: 213 %a1 = trunc <4 x i32> %a to <4 x i1> 214 %b1 = trunc <4 x i32> %b to <4 x i1> 215 %cmp = icmp ne <4 x i1> %a1, %b1 216 217; ASM: vshl.u32 q0, q0, #31 218; ASM-NEXT: vshl.u32 q1, q1, #31 219; ASM-NEXT: vceq.i32 q0, q0, q1 220; ASM-NEXT: vmvn.i32 q0, q0 221; DIS: 110: f2bf0550 222; DIS-NEXT: 114: f2bf2552 223; DIS-NEXT: 118: f3200852 224; DIS-NEXT: 11c: f3b005c0 225; IASM-NOT: vshl 226; IASM-NOT: vceq 227; IASM-NOT: vmvn 228 229 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 230 ret <4 x i32> %cmp.ret_ext 231} 232 233define internal <4 x i32> @cmpUgtV4I1(<4 x i32> %a, <4 x i32> %b) { 234; ASM-LABEL:cmpUgtV4I1: 235; DIS-LABEL:00000130 <cmpUgtV4I1>: 236; IASM-LABEL:cmpUgtV4I1: 237 238entry: 239 %a1 = trunc <4 x i32> %a to <4 x i1> 240 %b1 = trunc <4 x i32> %b to <4 x i1> 241 %cmp = icmp ugt <4 x i1> %a1, %b1 242 243; ASM: vshl.u32 q0, q0, #31 244; ASM-NEXT: vshl.u32 q1, q1, #31 245; ASM-NEXT: vcgt.u32 q0, q0, q1 246; DIS: 130: f2bf0550 247; DIS-NEXT: 134: f2bf2552 248; DIS-NEXT: 138: f3200342 249; IASM-NOT: vshl 250; IASM-NOT: vcgt 251 252 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 253 ret <4 x i32> %cmp.ret_ext 254} 255 256define internal <4 x i32> @cmpUgeV4I1(<4 x i32> %a, <4 x i32> %b) { 257; ASM-LABEL:cmpUgeV4I1: 258; DIS-LABEL:00000150 <cmpUgeV4I1>: 259; IASM-LABEL:cmpUgeV4I1: 260 261entry: 262 %a1 = trunc <4 x i32> %a to <4 x i1> 263 %b1 = trunc <4 x i32> %b to <4 x i1> 264 %cmp = icmp uge <4 x i1> %a1, %b1 265 266; ASM: vshl.u32 q0, q0, #31 267; ASM-NEXT: vshl.u32 q1, q1, #31 268; ASM-NEXT: vcge.u32 q0, q0, q1 269; DIS: 150: f2bf0550 270; DIS-NEXT: 154: f2bf2552 271; DIS-NEXT: 158: f3200352 272; IASM-NOT: vshl 273; IASM-NOT: vcge 274 275 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 276 ret <4 x i32> %cmp.ret_ext 277} 278 279define internal <4 x i32> @cmpUltV4I1(<4 x i32> %a, <4 x i32> %b) { 280; ASM-LABEL:cmpUltV4I1: 281; DIS-LABEL:00000170 <cmpUltV4I1>: 282; IASM-LABEL:cmpUltV4I1: 283 284entry: 285 %a1 = trunc <4 x i32> %a to <4 x i1> 286 %b1 = trunc <4 x i32> %b to <4 x i1> 287 %cmp = icmp ult <4 x i1> %a1, %b1 288 289; ASM: vshl.u32 q0, q0, #31 290; ASM-NEXT: vshl.u32 q1, q1, #31 291; ASM-NEXT: vcgt.u32 q1, q1, q0 292; DIS: 170: f2bf0550 293; DIS-NEXT: 174: f2bf2552 294; DIS-NEXT: 178: f3222340 295; IASM-NOT: vshl 296; IASM-NOT: vcgt 297 298 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 299 ret <4 x i32> %cmp.ret_ext 300} 301 302define internal <4 x i32> @cmpUleV4I1(<4 x i32> %a, <4 x i32> %b) { 303; ASM-LABEL:cmpUleV4I1: 304; DIS-LABEL:00000190 <cmpUleV4I1>: 305; IASM-LABEL:cmpUleV4I1: 306 307entry: 308 %a1 = trunc <4 x i32> %a to <4 x i1> 309 %b1 = trunc <4 x i32> %b to <4 x i1> 310 %cmp = icmp ule <4 x i1> %a1, %b1 311 312; ASM: vshl.u32 q0, q0, #31 313; ASM-NEXT: vshl.u32 q1, q1, #31 314; ASM-NEXT: vcge.u32 q1, q1, q0 315; DIS: 190: f2bf0550 316; DIS-NEXT: 194: f2bf2552 317; DIS-NEXT: 198: f3222350 318; IASM-NOT: vshl 319; IASM-NOT: vcge 320 321 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 322 ret <4 x i32> %cmp.ret_ext 323} 324 325define internal <4 x i32> @cmpSgtV4I1(<4 x i32> %a, <4 x i32> %b) { 326; ASM-LABEL:cmpSgtV4I1: 327; DIS-LABEL:000001b0 <cmpSgtV4I1>: 328; IASM-LABEL:cmpSgtV4I1: 329 330entry: 331 %a1 = trunc <4 x i32> %a to <4 x i1> 332 %b1 = trunc <4 x i32> %b to <4 x i1> 333 %cmp = icmp sgt <4 x i1> %a1, %b1 334 335; ASM: vshl.u32 q0, q0, #31 336; ASM-NEXT: vshl.u32 q1, q1, #31 337; ASM-NEXT: vcgt.s32 q0, q0, q1 338; DIS: 1b0: f2bf0550 339; DIS-NEXT: 1b4: f2bf2552 340; DIS-NEXT: 1b8: f2200342 341; IASM-NOT: vshl 342; IASM-NOT: vcgt 343 344 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 345 ret <4 x i32> %cmp.ret_ext 346} 347 348define internal <4 x i32> @cmpSgeV4I1(<4 x i32> %a, <4 x i32> %b) { 349; ASM-LABEL:cmpSgeV4I1: 350; DIS-LABEL:000001d0 <cmpSgeV4I1>: 351; IASM-LABEL:cmpSgeV4I1: 352 353entry: 354 %a1 = trunc <4 x i32> %a to <4 x i1> 355 %b1 = trunc <4 x i32> %b to <4 x i1> 356 %cmp = icmp sge <4 x i1> %a1, %b1 357 358; ASM: vshl.u32 q0, q0, #31 359; ASM-NEXT: vshl.u32 q1, q1, #31 360; ASM-NEXT: vcge.s32 q0, q0, q1 361; DIS: 1d0: f2bf0550 362; DIS-NEXT: 1d4: f2bf2552 363; DIS-NEXT: 1d8: f2200352 364; IASM-NOT: vshl 365; IASM-NOT: vcge 366 367 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 368 ret <4 x i32> %cmp.ret_ext 369} 370 371define internal <4 x i32> @cmpSltV4I1(<4 x i32> %a, <4 x i32> %b) { 372; ASM-LABEL:cmpSltV4I1: 373; DIS-LABEL:000001f0 <cmpSltV4I1>: 374; IASM-LABEL:cmpSltV4I1: 375 376entry: 377 %a1 = trunc <4 x i32> %a to <4 x i1> 378 %b1 = trunc <4 x i32> %b to <4 x i1> 379 %cmp = icmp slt <4 x i1> %a1, %b1 380 381; ASM: vshl.u32 q0, q0, #31 382; ASM-NEXT: vshl.u32 q1, q1, #31 383; ASM-NEXT: vcgt.s32 q1, q1, q0 384; DIS: 1f0: f2bf0550 385; DIS-NEXT: 1f4: f2bf2552 386; DIS-NEXT: 1f8: f2222340 387; IASM-NOT: vshl 388; IASM-NOT: vcgt 389 390 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 391 ret <4 x i32> %cmp.ret_ext 392} 393 394define internal <4 x i32> @cmpSleV4I1(<4 x i32> %a, <4 x i32> %b) { 395; ASM-LABEL:cmpSleV4I1: 396; DIS-LABEL:00000210 <cmpSleV4I1>: 397; IASM-LABEL:cmpSleV4I1: 398 399entry: 400 %a1 = trunc <4 x i32> %a to <4 x i1> 401 %b1 = trunc <4 x i32> %b to <4 x i1> 402 %cmp = icmp sle <4 x i1> %a1, %b1 403 404; ASM: vshl.u32 q0, q0, #31 405; ASM-NEXT: vshl.u32 q1, q1, #31 406; ASM-NEXT: vcge.s32 q1, q1, q0 407; DIS: 210: f2bf0550 408; DIS-NEXT: 214: f2bf2552 409; DIS-NEXT: 218: f2222350 410; IASM-NOT: vshl 411; IASM-NOT: vcge 412 413 %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32> 414 ret <4 x i32> %cmp.ret_ext 415} 416 417define internal <8 x i16> @cmpEqV8I16(<8 x i16> %a, <8 x i16> %b) { 418; ASM-LABEL:cmpEqV8I16: 419; DIS-LABEL:00000230 <cmpEqV8I16>: 420; IASM-LABEL:cmpEqV8I16: 421 422entry: 423 %cmp = icmp eq <8 x i16> %a, %b 424 425; ASM: vceq.i16 q0, q0, q1 426; DIS: 230: f3100852 427; IASM-NOT: vceq 428 429 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 430 ret <8 x i16> %cmp.ret_ext 431} 432 433define internal <8 x i16> @cmpNeV8I16(<8 x i16> %a, <8 x i16> %b) { 434; ASM-LABEL:cmpNeV8I16: 435; DIS-LABEL:00000240 <cmpNeV8I16>: 436; IASM-LABEL:cmpNeV8I16: 437 438entry: 439 %cmp = icmp ne <8 x i16> %a, %b 440 441; ASM: vceq.i16 q0, q0, q1 442; ASM-NEXT: vmvn.i16 q0, q0 443; DIS: 240: f3100852 444; DIS-NEXT: 244: f3b005c0 445; IASM-NOT: vceq 446; IASM-NOT: vmvn 447 448 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 449 ret <8 x i16> %cmp.ret_ext 450} 451 452define internal <8 x i16> @cmpUgtV8I16(<8 x i16> %a, <8 x i16> %b) { 453; ASM-LABEL:cmpUgtV8I16: 454; DIS-LABEL:00000260 <cmpUgtV8I16>: 455; IASM-LABEL:cmpUgtV8I16: 456 457entry: 458 %cmp = icmp ugt <8 x i16> %a, %b 459 460; ASM: vcgt.u16 q0, q0, q1 461; DIS: 260: f3100342 462; IASM-NOT: vcgt 463 464 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 465 ret <8 x i16> %cmp.ret_ext 466} 467 468define internal <8 x i16> @cmpUgeV8I16(<8 x i16> %a, <8 x i16> %b) { 469; ASM-LABEL:cmpUgeV8I16: 470; DIS-LABEL:00000270 <cmpUgeV8I16>: 471; IASM-LABEL:cmpUgeV8I16: 472 473entry: 474 %cmp = icmp uge <8 x i16> %a, %b 475 476; ASM: vcge.u16 q0, q0, q1 477; DIS: 270: f3100352 478; IASM-NOT: vcge 479 480 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 481 ret <8 x i16> %cmp.ret_ext 482} 483 484define internal <8 x i16> @cmpUltV8I16(<8 x i16> %a, <8 x i16> %b) { 485; ASM-LABEL:cmpUltV8I16: 486; DIS-LABEL:00000280 <cmpUltV8I16>: 487; IASM-LABEL:cmpUltV8I16: 488 489entry: 490 %cmp = icmp ult <8 x i16> %a, %b 491 492; ASM: vcgt.u16 q1, q1, q0 493; DIS: 280: f3122340 494; IASM-NOT: vcgt 495 496 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 497 ret <8 x i16> %cmp.ret_ext 498} 499 500define internal <8 x i16> @cmpUleV8I16(<8 x i16> %a, <8 x i16> %b) { 501; ASM-LABEL:cmpUleV8I16: 502; DIS-LABEL:000002a0 <cmpUleV8I16>: 503; IASM-LABEL:cmpUleV8I16: 504 505entry: 506 %cmp = icmp ule <8 x i16> %a, %b 507 508; ASM: vcge.u16 q1, q1, q0 509; DIS: 2a0: f3122350 510; IASM-NOT: vcge 511 512 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 513 ret <8 x i16> %cmp.ret_ext 514} 515 516define internal <8 x i16> @cmpSgtV8I16(<8 x i16> %a, <8 x i16> %b) { 517; ASM-LABEL:cmpSgtV8I16: 518; DIS-LABEL:000002c0 <cmpSgtV8I16>: 519; IASM-LABEL:cmpSgtV8I16: 520 521entry: 522 %cmp = icmp sgt <8 x i16> %a, %b 523 524; ASM: vcgt.s16 q0, q0, q1 525; DIS: 2c0: f2100342 526; IASM-NOT: vcgt 527 528 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 529 ret <8 x i16> %cmp.ret_ext 530} 531 532define internal <8 x i16> @cmpSgeV8I16(<8 x i16> %a, <8 x i16> %b) { 533; ASM-LABEL:cmpSgeV8I16: 534; DIS-LABEL:000002d0 <cmpSgeV8I16>: 535; IASM-LABEL:cmpSgeV8I16: 536 537entry: 538 %cmp = icmp sge <8 x i16> %a, %b 539 540; ASM: vcge.s16 q0, q0, q1 541; DIS: 2d0: f2100352 542; IASM-NOT: vcge 543 544 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 545 ret <8 x i16> %cmp.ret_ext 546} 547 548define internal <8 x i16> @cmpSltV8I16(<8 x i16> %a, <8 x i16> %b) { 549; ASM-LABEL:cmpSltV8I16: 550; DIS-LABEL:000002e0 <cmpSltV8I16>: 551; IASM-LABEL:cmpSltV8I16: 552 553entry: 554 %cmp = icmp slt <8 x i16> %a, %b 555 556; ASM: vcgt.s16 q1, q1, q0 557; DIS: 2e0: f2122340 558; IASM-NOT: vcgt 559 560 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 561 ret <8 x i16> %cmp.ret_ext 562} 563 564define internal <8 x i16> @cmpSleV8I16(<8 x i16> %a, <8 x i16> %b) { 565; ASM-LABEL:cmpSleV8I16: 566; DIS-LABEL:00000300 <cmpSleV8I16>: 567; IASM-LABEL:cmpSleV8I16: 568 569entry: 570 %cmp = icmp sle <8 x i16> %a, %b 571 572; ASM: vcge.s16 q1, q1, q0 573; DIS: 300: f2122350 574; IASM-NOT: vcge 575 576 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 577 ret <8 x i16> %cmp.ret_ext 578} 579 580define internal <8 x i16> @cmpEqV8I1(<8 x i16> %a, <8 x i16> %b) { 581; ASM-LABEL:cmpEqV8I1: 582; DIS-LABEL:00000320 <cmpEqV8I1>: 583; IASM-LABEL:cmpEqV8I1: 584 585entry: 586 %a1 = trunc <8 x i16> %a to <8 x i1> 587 %b1 = trunc <8 x i16> %b to <8 x i1> 588 %cmp = icmp eq <8 x i1> %a1, %b1 589 590; ASM: vshl.u16 q0, q0, #15 591; ASM-NEXT: vshl.u16 q1, q1, #15 592; ASM-NEXT: vceq.i16 q0, q0, q1 593; DIS: 320: f29f0550 594; DIS-NEXT: 324: f29f2552 595; DIS-NEXT: 328: f3100852 596; IASM-NOT: vshl 597; IASM-NOT: vceq 598 599 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 600 ret <8 x i16> %cmp.ret_ext 601} 602 603define internal <8 x i16> @cmpNeV8I1(<8 x i16> %a, <8 x i16> %b) { 604; ASM-LABEL:cmpNeV8I1: 605; DIS-LABEL:00000340 <cmpNeV8I1>: 606; IASM-LABEL:cmpNeV8I1: 607 608entry: 609 %a1 = trunc <8 x i16> %a to <8 x i1> 610 %b1 = trunc <8 x i16> %b to <8 x i1> 611 %cmp = icmp ne <8 x i1> %a1, %b1 612 613; ASM: vshl.u16 q0, q0, #15 614; ASM-NEXT: vshl.u16 q1, q1, #15 615; ASM-NEXT: vceq.i16 q0, q0, q1 616; ASM-NEXT: vmvn.i16 q0, q0 617; DIS: 340: f29f0550 618; DIS-NEXT: 344: f29f2552 619; DIS-NEXT: 348: f3100852 620; DIS-NEXT: 34c: f3b005c0 621; IASM-NOT: vshl 622; IASM-NOT: vceq 623; IASM-NOT: vmvn 624 625 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 626 ret <8 x i16> %cmp.ret_ext 627} 628 629define internal <8 x i16> @cmpUgtV8I1(<8 x i16> %a, <8 x i16> %b) { 630; ASM-LABEL:cmpUgtV8I1: 631; DIS-LABEL:00000360 <cmpUgtV8I1>: 632; IASM-LABEL:cmpUgtV8I1: 633 634entry: 635 %a1 = trunc <8 x i16> %a to <8 x i1> 636 %b1 = trunc <8 x i16> %b to <8 x i1> 637 %cmp = icmp ugt <8 x i1> %a1, %b1 638 639; ASM: vshl.u16 q0, q0, #15 640; ASM-NEXT: vshl.u16 q1, q1, #15 641; ASM-NEXT: vcgt.u16 q0, q0, q1 642; DIS: 360: f29f0550 643; DIS-NEXT: 364: f29f2552 644; DIS-NEXT: 368: f3100342 645; IASM-NOT: vshl 646; IASM-NOT: vcgt 647 648 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 649 ret <8 x i16> %cmp.ret_ext 650} 651 652define internal <8 x i16> @cmpUgeV8I1(<8 x i16> %a, <8 x i16> %b) { 653; ASM-LABEL:cmpUgeV8I1: 654; DIS-LABEL:00000380 <cmpUgeV8I1>: 655; IASM-LABEL:cmpUgeV8I1: 656 657entry: 658 %a1 = trunc <8 x i16> %a to <8 x i1> 659 %b1 = trunc <8 x i16> %b to <8 x i1> 660 %cmp = icmp uge <8 x i1> %a1, %b1 661 662; ASM: vshl.u16 q0, q0, #15 663; ASM-NEXT: vshl.u16 q1, q1, #15 664; ASM-NEXT: vcge.u16 q0, q0, q1 665; DIS: 380: f29f0550 666; DIS-NEXT: 384: f29f2552 667; DIS-NEXT: 388: f3100352 668; IASM-NOT: vshl 669; IASM-NOT: vcge 670 671 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 672 ret <8 x i16> %cmp.ret_ext 673} 674 675define internal <8 x i16> @cmpUltV8I1(<8 x i16> %a, <8 x i16> %b) { 676; ASM-LABEL:cmpUltV8I1: 677; DIS-LABEL:000003a0 <cmpUltV8I1>: 678; IASM-LABEL:cmpUltV8I1: 679 680entry: 681 %a1 = trunc <8 x i16> %a to <8 x i1> 682 %b1 = trunc <8 x i16> %b to <8 x i1> 683 %cmp = icmp ult <8 x i1> %a1, %b1 684 685; ASM: vshl.u16 q0, q0, #15 686; ASM-NEXT: vshl.u16 q1, q1, #15 687; ASM-NEXT: vcgt.u16 q1, q1, q0 688; DIS: 3a0: f29f0550 689; DIS-NEXT: 3a4: f29f2552 690; DIS-NEXT: 3a8: f3122340 691; IASM-NOT: vshl 692; IASM-NOT: vcgt 693 694 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 695 ret <8 x i16> %cmp.ret_ext 696} 697 698define internal <8 x i16> @cmpUleV8I1(<8 x i16> %a, <8 x i16> %b) { 699; ASM-LABEL:cmpUleV8I1: 700; DIS-LABEL:000003c0 <cmpUleV8I1>: 701; IASM-LABEL:cmpUleV8I1: 702 703entry: 704 %a1 = trunc <8 x i16> %a to <8 x i1> 705 %b1 = trunc <8 x i16> %b to <8 x i1> 706 %cmp = icmp ule <8 x i1> %a1, %b1 707 708; ASM: vshl.u16 q0, q0, #15 709; ASM-NEXT: vshl.u16 q1, q1, #15 710; ASM-NEXT: vcge.u16 q1, q1, q0 711; DIS: 3c0: f29f0550 712; DIS-NEXT: 3c4: f29f2552 713; DIS-NEXT: 3c8: f3122350 714; IASM-NOT: vshl 715; IASM-NOT: vcge 716 717 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 718 ret <8 x i16> %cmp.ret_ext 719} 720 721define internal <8 x i16> @cmpSgtV8I1(<8 x i16> %a, <8 x i16> %b) { 722; ASM-LABEL:cmpSgtV8I1: 723; DIS-LABEL:000003e0 <cmpSgtV8I1>: 724; IASM-LABEL:cmpSgtV8I1: 725 726entry: 727 %a1 = trunc <8 x i16> %a to <8 x i1> 728 %b1 = trunc <8 x i16> %b to <8 x i1> 729 %cmp = icmp sgt <8 x i1> %a1, %b1 730 731; ASM: vshl.u16 q0, q0, #15 732; ASM-NEXT: vshl.u16 q1, q1, #15 733; ASM-NEXT: vcgt.s16 q0, q0, q1 734; DIS: 3e0: f29f0550 735; DIS-NEXT: 3e4: f29f2552 736; DIS-NEXT: 3e8: f2100342 737; IASM-NOT: vshl 738; IASM-NOT: vcgt 739 740 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 741 ret <8 x i16> %cmp.ret_ext 742} 743 744define internal <8 x i16> @cmpSgeV8I1(<8 x i16> %a, <8 x i16> %b) { 745; ASM-LABEL:cmpSgeV8I1: 746; DIS-LABEL:00000400 <cmpSgeV8I1>: 747; IASM-LABEL:cmpSgeV8I1: 748 749entry: 750 %a1 = trunc <8 x i16> %a to <8 x i1> 751 %b1 = trunc <8 x i16> %b to <8 x i1> 752 %cmp = icmp sge <8 x i1> %a1, %b1 753 754; ASM: vshl.u16 q0, q0, #15 755; ASM-NEXT: vshl.u16 q1, q1, #15 756; ASM-NEXT: vcge.s16 q0, q0, q1 757; DIS: 400: f29f0550 758; DIS-NEXT: 404: f29f2552 759; DIS-NEXT: 408: f2100352 760; IASM-NOT: vshl 761; IASM-NOT: vcge 762 763 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 764 ret <8 x i16> %cmp.ret_ext 765} 766 767define internal <8 x i16> @cmpSltV8I1(<8 x i16> %a, <8 x i16> %b) { 768; ASM-LABEL:cmpSltV8I1: 769; DIS-LABEL:00000420 <cmpSltV8I1>: 770; IASM-LABEL:cmpSltV8I1: 771 772entry: 773 %a1 = trunc <8 x i16> %a to <8 x i1> 774 %b1 = trunc <8 x i16> %b to <8 x i1> 775 %cmp = icmp slt <8 x i1> %a1, %b1 776 777; ASM: vshl.u16 q0, q0, #15 778; ASM-NEXT: vshl.u16 q1, q1, #15 779; ASM-NEXT: vcgt.s16 q1, q1, q0 780; DIS: 420: f29f0550 781; DIS-NEXT: 424: f29f2552 782; DIS-NEXT: 428: f2122340 783; IASM-NOT: vshl 784; IASM-NOT: vcgt 785 786 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 787 ret <8 x i16> %cmp.ret_ext 788} 789 790define internal <8 x i16> @cmpSleV8I1(<8 x i16> %a, <8 x i16> %b) { 791; ASM-LABEL:cmpSleV8I1: 792; DIS-LABEL:00000440 <cmpSleV8I1>: 793; IASM-LABEL:cmpSleV8I1: 794 795entry: 796 %a1 = trunc <8 x i16> %a to <8 x i1> 797 %b1 = trunc <8 x i16> %b to <8 x i1> 798 %cmp = icmp sle <8 x i1> %a1, %b1 799 800; ASM: vshl.u16 q0, q0, #15 801; ASM-NEXT: vshl.u16 q1, q1, #15 802; ASM-NEXT: vcge.s16 q1, q1, q0 803; DIS: 440: f29f0550 804; DIS-NEXT: 444: f29f2552 805; DIS-NEXT: 448: f2122350 806; IASM-NOT: vshl 807; IASM-NOT: vcge 808 809 %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16> 810 ret <8 x i16> %cmp.ret_ext 811} 812 813define internal <16 x i8> @cmpEqV16I8(<16 x i8> %a, <16 x i8> %b) { 814; ASM-LABEL:cmpEqV16I8: 815; DIS-LABEL:00000460 <cmpEqV16I8>: 816; IASM-LABEL:cmpEqV16I8: 817 818entry: 819 %cmp = icmp eq <16 x i8> %a, %b 820 821; ASM: vceq.i8 q0, q0, q1 822; DIS: 460: f3000852 823; IASM-NOT: vceq 824 825 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 826 ret <16 x i8> %cmp.ret_ext 827} 828 829define internal <16 x i8> @cmpNeV16I8(<16 x i8> %a, <16 x i8> %b) { 830; ASM-LABEL:cmpNeV16I8: 831; DIS-LABEL:00000470 <cmpNeV16I8>: 832; IASM-LABEL:cmpNeV16I8: 833 834entry: 835 %cmp = icmp ne <16 x i8> %a, %b 836 837; ASM: vceq.i8 q0, q0, q1 838; ASM-NEXT: vmvn.i8 q0, q0 839; DIS: 470: f3000852 840; DIS-NEXT: 474: f3b005c0 841; IASM-NOT: vceq 842; IASM-NOT: vmvn 843 844 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 845 ret <16 x i8> %cmp.ret_ext 846} 847 848define internal <16 x i8> @cmpUgtV16I8(<16 x i8> %a, <16 x i8> %b) { 849; ASM-LABEL:cmpUgtV16I8: 850; DIS-LABEL:00000490 <cmpUgtV16I8>: 851; IASM-LABEL:cmpUgtV16I8: 852 853entry: 854 %cmp = icmp ugt <16 x i8> %a, %b 855 856; ASM: vcgt.u8 q0, q0, q1 857; DIS: 490: f3000342 858; IASM-NOT: vcgt 859 860 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 861 ret <16 x i8> %cmp.ret_ext 862} 863 864define internal <16 x i8> @cmpUgeV16I8(<16 x i8> %a, <16 x i8> %b) { 865; ASM-LABEL:cmpUgeV16I8: 866; DIS-LABEL:000004a0 <cmpUgeV16I8>: 867; IASM-LABEL:cmpUgeV16I8: 868 869entry: 870 %cmp = icmp uge <16 x i8> %a, %b 871 872; ASM: vcge.u8 q0, q0, q1 873; DIS: 4a0: f3000352 874; IASM-NOT: vcge 875 876 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 877 ret <16 x i8> %cmp.ret_ext 878} 879 880define internal <16 x i8> @cmpUltV16I8(<16 x i8> %a, <16 x i8> %b) { 881; ASM-LABEL:cmpUltV16I8: 882; DIS-LABEL:000004b0 <cmpUltV16I8>: 883; IASM-LABEL:cmpUltV16I8: 884 885entry: 886 %cmp = icmp ult <16 x i8> %a, %b 887 888; ASM: vcgt.u8 q1, q1, q0 889; DIS: 4b0: f3022340 890; IASM-NOT: vcgt 891 892 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 893 ret <16 x i8> %cmp.ret_ext 894} 895 896define internal <16 x i8> @cmpUleV16I8(<16 x i8> %a, <16 x i8> %b) { 897; ASM-LABEL:cmpUleV16I8: 898; DIS-LABEL:000004d0 <cmpUleV16I8>: 899; IASM-LABEL:cmpUleV16I8: 900 901entry: 902 %cmp = icmp ule <16 x i8> %a, %b 903 904; ASM: vcge.u8 q1, q1, q0 905; DIS: 4d0: f3022350 906; IASM-NOT: vcge 907 908 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 909 ret <16 x i8> %cmp.ret_ext 910} 911 912define internal <16 x i8> @cmpSgtV16I8(<16 x i8> %a, <16 x i8> %b) { 913; ASM-LABEL:cmpSgtV16I8: 914; DIS-LABEL:000004f0 <cmpSgtV16I8>: 915; IASM-LABEL:cmpSgtV16I8: 916 917entry: 918 %cmp = icmp sgt <16 x i8> %a, %b 919 920; ASM: vcgt.s8 q0, q0, q1 921; DIS: 4f0: f2000342 922; IASM-NOT: vcgt 923 924 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 925 ret <16 x i8> %cmp.ret_ext 926} 927 928define internal <16 x i8> @cmpSgeV16I8(<16 x i8> %a, <16 x i8> %b) { 929; ASM-LABEL:cmpSgeV16I8: 930; DIS-LABEL:00000500 <cmpSgeV16I8>: 931; IASM-LABEL:cmpSgeV16I8: 932 933entry: 934 %cmp = icmp sge <16 x i8> %a, %b 935 936; ASM: vcge.s8 q0, q0, q1 937; DIS: 500: f2000352 938; IASM-NOT: vcge 939 940 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 941 ret <16 x i8> %cmp.ret_ext 942} 943 944define internal <16 x i8> @cmpSltV16I8(<16 x i8> %a, <16 x i8> %b) { 945; ASM-LABEL:cmpSltV16I8: 946; DIS-LABEL:00000510 <cmpSltV16I8>: 947; IASM-LABEL:cmpSltV16I8: 948 949entry: 950 %cmp = icmp slt <16 x i8> %a, %b 951 952; ASM: vcgt.s8 q1, q1, q0 953; DIS: 510: f2022340 954; IASM-NOT: vcgt 955 956 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 957 ret <16 x i8> %cmp.ret_ext 958} 959 960define internal <16 x i8> @cmpSleV16I8(<16 x i8> %a, <16 x i8> %b) { 961; ASM-LABEL:cmpSleV16I8: 962; DIS-LABEL:00000530 <cmpSleV16I8>: 963; IASM-LABEL:cmpSleV16I8: 964 965entry: 966 %cmp = icmp sle <16 x i8> %a, %b 967 968; ASM: vcge.s8 q1, q1, q0 969; DIS: 530: f2022350 970; IASM-NOT: vcge 971 972 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 973 ret <16 x i8> %cmp.ret_ext 974} 975 976define internal <16 x i8> @cmpEqV16I1(<16 x i8> %a, <16 x i8> %b) { 977; ASM-LABEL:cmpEqV16I1: 978; DIS-LABEL:00000550 <cmpEqV16I1>: 979; IASM-LABEL:cmpEqV16I1: 980 981entry: 982 %a1 = trunc <16 x i8> %a to <16 x i1> 983 %b1 = trunc <16 x i8> %b to <16 x i1> 984 %cmp = icmp eq <16 x i1> %a1, %b1 985 986; ASM: vshl.u8 q0, q0, #7 987; ASM-NEXT: vshl.u8 q1, q1, #7 988; ASM-NEXT: vceq.i8 q0, q0, q1 989; DIS: 550: f28f0550 990; DIS-NEXT: 554: f28f2552 991; DIS-NEXT: 558: f3000852 992; IASM-NOT: vshl 993; IASM-NOT: vceq 994 995 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 996 ret <16 x i8> %cmp.ret_ext 997} 998 999define internal <16 x i8> @cmpNeV16I1(<16 x i8> %a, <16 x i8> %b) { 1000; ASM-LABEL:cmpNeV16I1: 1001; DIS-LABEL:00000570 <cmpNeV16I1>: 1002; IASM-LABEL:cmpNeV16I1: 1003 1004entry: 1005 %a1 = trunc <16 x i8> %a to <16 x i1> 1006 %b1 = trunc <16 x i8> %b to <16 x i1> 1007 %cmp = icmp ne <16 x i1> %a1, %b1 1008 1009; ASM: vshl.u8 q0, q0, #7 1010; ASM-NEXT: vshl.u8 q1, q1, #7 1011; ASM-NEXT: vceq.i8 q0, q0, q1 1012; ASM-NEXT: vmvn.i8 q0, q0 1013; DIS: 570: f28f0550 1014; DIS-NEXT: 574: f28f2552 1015; DIS-NEXT: 578: f3000852 1016; DIS-NEXT: 57c: f3b005c0 1017; IASM-NOT: vshl 1018; IASM-NOT: vceq 1019; IASM-NOT: vmvn 1020 1021 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 1022 ret <16 x i8> %cmp.ret_ext 1023} 1024 1025define internal <16 x i8> @cmpUgtV16I1(<16 x i8> %a, <16 x i8> %b) { 1026; ASM-LABEL:cmpUgtV16I1: 1027; DIS-LABEL:00000590 <cmpUgtV16I1>: 1028; IASM-LABEL:cmpUgtV16I1: 1029 1030entry: 1031 %a1 = trunc <16 x i8> %a to <16 x i1> 1032 %b1 = trunc <16 x i8> %b to <16 x i1> 1033 %cmp = icmp ugt <16 x i1> %a1, %b1 1034 1035; ASM: vshl.u8 q0, q0, #7 1036; ASM-NEXT: vshl.u8 q1, q1, #7 1037; ASM-NEXT: vcgt.u8 q0, q0, q1 1038; DIS: 590: f28f0550 1039; DIS-NEXT: 594: f28f2552 1040; DIS-NEXT: 598: f3000342 1041; IASM-NOT: vshl 1042; IASM-NOT: vcgt 1043 1044 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 1045 ret <16 x i8> %cmp.ret_ext 1046} 1047 1048define internal <16 x i8> @cmpUgeV16I1(<16 x i8> %a, <16 x i8> %b) { 1049; ASM-LABEL:cmpUgeV16I1: 1050; DIS-LABEL:000005b0 <cmpUgeV16I1>: 1051; IASM-LABEL:cmpUgeV16I1: 1052 1053entry: 1054 %a1 = trunc <16 x i8> %a to <16 x i1> 1055 %b1 = trunc <16 x i8> %b to <16 x i1> 1056 %cmp = icmp uge <16 x i1> %a1, %b1 1057 1058; ASM: vshl.u8 q0, q0, #7 1059; ASM-NEXT: vshl.u8 q1, q1, #7 1060; ASM-NEXT: vcge.u8 q0, q0, q1 1061; DIS: 5b0: f28f0550 1062; DIS-NEXT: 5b4: f28f2552 1063; DIS-NEXT: 5b8: f3000352 1064; IASM-NOT: vshl 1065; IASM-NOT: vcge 1066 1067 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 1068 ret <16 x i8> %cmp.ret_ext 1069} 1070 1071define internal <16 x i8> @cmpUltV16I1(<16 x i8> %a, <16 x i8> %b) { 1072; ASM-LABEL:cmpUltV16I1: 1073; DIS-LABEL:000005d0 <cmpUltV16I1>: 1074; IASM-LABEL:cmpUltV16I1: 1075 1076entry: 1077 %a1 = trunc <16 x i8> %a to <16 x i1> 1078 %b1 = trunc <16 x i8> %b to <16 x i1> 1079 %cmp = icmp ult <16 x i1> %a1, %b1 1080 1081; ASM: vshl.u8 q0, q0, #7 1082; ASM-NEXT: vshl.u8 q1, q1, #7 1083; ASM-NEXT: vcgt.u8 q1, q1, q0 1084; DIS: 5d0: f28f0550 1085; DIS-NEXT: 5d4: f28f2552 1086; DIS-NEXT: 5d8: f3022340 1087; IASM-NOT: vshl 1088; IASM-NOT: vcgt 1089 1090 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 1091 ret <16 x i8> %cmp.ret_ext 1092} 1093 1094define internal <16 x i8> @cmpUleV16I1(<16 x i8> %a, <16 x i8> %b) { 1095; ASM-LABEL:cmpUleV16I1: 1096; DIS-LABEL:000005f0 <cmpUleV16I1>: 1097; IASM-LABEL:cmpUleV16I1: 1098 1099entry: 1100 %a1 = trunc <16 x i8> %a to <16 x i1> 1101 %b1 = trunc <16 x i8> %b to <16 x i1> 1102 %cmp = icmp ule <16 x i1> %a1, %b1 1103 1104; ASM: vshl.u8 q0, q0, #7 1105; ASM-NEXT: vshl.u8 q1, q1, #7 1106; ASM-NEXT: vcge.u8 q1, q1, q0 1107; DIS: 5f0: f28f0550 1108; DIS-NEXT: 5f4: f28f2552 1109; DIS-NEXT: 5f8: f3022350 1110; IASM-NOT: vshl 1111; IASM-NOT: vcge 1112 1113 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 1114 ret <16 x i8> %cmp.ret_ext 1115} 1116 1117define internal <16 x i8> @cmpSgtV16I1(<16 x i8> %a, <16 x i8> %b) { 1118; ASM-LABEL:cmpSgtV16I1: 1119; DIS-LABEL:00000610 <cmpSgtV16I1>: 1120; IASM-LABEL:cmpSgtV16I1: 1121 1122entry: 1123 %a1 = trunc <16 x i8> %a to <16 x i1> 1124 %b1 = trunc <16 x i8> %b to <16 x i1> 1125 %cmp = icmp sgt <16 x i1> %a1, %b1 1126 1127; ASM: vshl.u8 q0, q0, #7 1128; ASM-NEXT: vshl.u8 q1, q1, #7 1129; ASM-NEXT: vcgt.s8 q0, q0, q1 1130; DIS: 610: f28f0550 1131; DIS-NEXT: 614: f28f2552 1132; DIS-NEXT: 618: f2000342 1133; IASM-NOT: vshl 1134; IASM-NOT: vcgt 1135 1136 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 1137 ret <16 x i8> %cmp.ret_ext 1138} 1139 1140define internal <16 x i8> @cmpSgeV16I1(<16 x i8> %a, <16 x i8> %b) { 1141; ASM-LABEL:cmpSgeV16I1: 1142; DIS-LABEL:00000630 <cmpSgeV16I1>: 1143; IASM-LABEL:cmpSgeV16I1: 1144 1145entry: 1146 %a1 = trunc <16 x i8> %a to <16 x i1> 1147 %b1 = trunc <16 x i8> %b to <16 x i1> 1148 %cmp = icmp sge <16 x i1> %a1, %b1 1149 1150; ASM: vshl.u8 q0, q0, #7 1151; ASM-NEXT: vshl.u8 q1, q1, #7 1152; ASM-NEXT: vcge.s8 q0, q0, q1 1153; DIS: 630: f28f0550 1154; DIS-NEXT: 634: f28f2552 1155; DIS-NEXT: 638: f2000352 1156; IASM-NOT: vshl 1157; IASM-NOT: vcge 1158 1159 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 1160 ret <16 x i8> %cmp.ret_ext 1161} 1162 1163define internal <16 x i8> @cmpSltV16I1(<16 x i8> %a, <16 x i8> %b) { 1164; ASM-LABEL:cmpSltV16I1: 1165; DIS-LABEL:00000650 <cmpSltV16I1>: 1166; IASM-LABEL:cmpSltV16I1: 1167 1168entry: 1169 %a1 = trunc <16 x i8> %a to <16 x i1> 1170 %b1 = trunc <16 x i8> %b to <16 x i1> 1171 %cmp = icmp slt <16 x i1> %a1, %b1 1172 1173; ASM: vshl.u8 q0, q0, #7 1174; ASM-NEXT: vshl.u8 q1, q1, #7 1175; ASM-NEXT: vcgt.s8 q1, q1, q0 1176; DIS: 650: f28f0550 1177; DIS-NEXT: 654: f28f2552 1178; DIS-NEXT: 658: f2022340 1179; IASM-NOT: vshl 1180; IASM-NOT: vcgt 1181 1182 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 1183 ret <16 x i8> %cmp.ret_ext 1184} 1185 1186define internal <16 x i8> @cmpSleV16I1(<16 x i8> %a, <16 x i8> %b) { 1187; ASM-LABEL:cmpSleV16I1: 1188; DIS-LABEL:00000670 <cmpSleV16I1>: 1189; IASM-LABEL:cmpSleV16I1: 1190 1191entry: 1192 %a1 = trunc <16 x i8> %a to <16 x i1> 1193 %b1 = trunc <16 x i8> %b to <16 x i1> 1194 %cmp = icmp sle <16 x i1> %a1, %b1 1195 1196; ASM: vshl.u8 q0, q0, #7 1197; ASM-NEXT: vshl.u8 q1, q1, #7 1198; ASM-NEXT: vcge.s8 q1, q1, q0 1199; DIS: 670: f28f0550 1200; DIS-NEXT: 674: f28f2552 1201; DIS-NEXT: 678: f2022350 1202; IASM-NOT: vshl 1203; IASM-NOT: vcge 1204 1205 %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8> 1206 ret <16 x i8> %cmp.ret_ext 1207} 1208 1209define internal <4 x i32> @cmpFalseV4Float(<4 x float> %a, <4 x float> %b) { 1210; ASM-LABEL:cmpFalseV4Float: 1211; DIS-LABEL:00000690 <cmpFalseV4Float>: 1212; IASM-LABEL:cmpFalseV4Float: 1213 1214entry: 1215 %cmp = fcmp false <4 x float> %a, %b 1216 1217; ASM: vmov.i32 q0, #0 1218; DIS: 690: f2800050 1219; IASM-NOT: vmov 1220 1221 %zext = zext <4 x i1> %cmp to <4 x i32> 1222 ret <4 x i32> %zext 1223} 1224 1225define internal <4 x i32> @cmpOeqV4Float(<4 x float> %a, <4 x float> %b) { 1226; ASM-LABEL:cmpOeqV4Float: 1227; DIS-LABEL:000006a0 <cmpOeqV4Float>: 1228; IASM-LABEL:cmpOeqV4Float: 1229 1230entry: 1231 %cmp = fcmp oeq <4 x float> %a, %b 1232 1233; ASM: vceq.f32 q0, q0, q1 1234; DIS: 6a0: f2000e42 1235; IASM-NOT: vceq 1236 1237 %zext = zext <4 x i1> %cmp to <4 x i32> 1238 ret <4 x i32> %zext 1239} 1240 1241define internal <4 x i32> @cmpOgtV4Float(<4 x float> %a, <4 x float> %b) { 1242; ASM-LABEL:cmpOgtV4Float: 1243; DIS-LABEL:000006b0 <cmpOgtV4Float>: 1244; IASM-LABEL:cmpOgtV4Float: 1245 1246entry: 1247 %cmp = fcmp ogt <4 x float> %a, %b 1248 1249; ASM: vcgt.f32 q0, q0, q1 1250; DIS: 6b0: f3200e42 1251; IASM-NOT: vcgt 1252 1253 %zext = zext <4 x i1> %cmp to <4 x i32> 1254 ret <4 x i32> %zext 1255} 1256 1257define internal <4 x i32> @cmpOgeV4Float(<4 x float> %a, <4 x float> %b) { 1258; ASM-LABEL:cmpOgeV4Float: 1259; DIS-LABEL:000006c0 <cmpOgeV4Float>: 1260; IASM-LABEL:cmpOgeV4Float: 1261 1262entry: 1263 %cmp = fcmp oge <4 x float> %a, %b 1264 1265; ASM: vcge.f32 q0, q0, q1 1266; DIS: 6c0: f3000e42 1267; IASM-NOT: vcge 1268 1269 %zext = zext <4 x i1> %cmp to <4 x i32> 1270 ret <4 x i32> %zext 1271} 1272 1273define internal <4 x i32> @cmpOltV4Float(<4 x float> %a, <4 x float> %b) { 1274; ASM-LABEL:cmpOltV4Float: 1275; DIS-LABEL:000006d0 <cmpOltV4Float>: 1276; IASM-LABEL:cmpOltV4Float: 1277 1278entry: 1279 %cmp = fcmp olt <4 x float> %a, %b 1280 1281; ASM: vcgt.f32 q1, q1, q0 1282; DIS: 6d0: f3222e40 1283; IASM-NOT: vcgt 1284 1285 %zext = zext <4 x i1> %cmp to <4 x i32> 1286 ret <4 x i32> %zext 1287} 1288 1289define internal <4 x i32> @cmpOleV4Float(<4 x float> %a, <4 x float> %b) { 1290; ASM-LABEL:cmpOleV4Float: 1291; DIS-LABEL:000006f0 <cmpOleV4Float>: 1292; IASM-LABEL:cmpOleV4Float: 1293 1294entry: 1295 %cmp = fcmp ole <4 x float> %a, %b 1296 1297; ASM: vcge.f32 q1, q1, q0 1298; DIS: 6f0: f3022e40 1299; IASM-NOT: vcge 1300 1301 %zext = zext <4 x i1> %cmp to <4 x i32> 1302 ret <4 x i32> %zext 1303} 1304 1305define internal <4 x i32> @cmpOrdV4Float(<4 x float> %a, <4 x float> %b) { 1306; ASM-LABEL:cmpOrdV4Float: 1307; DIS-LABEL:00000710 <cmpOrdV4Float>: 1308; IASM-LABEL:cmpOrdV4Float: 1309 1310entry: 1311 %cmp = fcmp ord <4 x float> %a, %b 1312 1313; ASM: vcge.f32 q2, q0, q1 1314; ASM-NEXT: vcgt.f32 q1, q1, q0 1315; DIS: 710: f3004e42 1316; DIS-NEXT: 714: f3222e40 1317; IASM-NOT: vcge 1318; IASM-NOT: vcgt 1319 1320 %zext = zext <4 x i1> %cmp to <4 x i32> 1321 ret <4 x i32> %zext 1322} 1323 1324define internal <4 x i32> @cmpUeqV4Float(<4 x float> %a, <4 x float> %b) { 1325; ASM-LABEL:cmpUeqV4Float: 1326; DIS-LABEL:00000730 <cmpUeqV4Float>: 1327; IASM-LABEL:cmpUeqV4Float: 1328 1329entry: 1330 %cmp = fcmp ueq <4 x float> %a, %b 1331 1332; ASM: vcgt.f32 q2, q0, q1 1333; ASM-NEXT: vcgt.f32 q1, q1, q0 1334; ASM-NEXT: vorr.i32 q2, q2, q1 1335; ASM-NEXT: vmvn.i32 q2, q2 1336; DIS: 730: f3204e42 1337; DIS-NEXT: 734: f3222e40 1338; DIS-NEXT: 738: f2244152 1339; DIS-NEXT: 73c: f3b045c4 1340; IASM-NOT: vcgt 1341; IASM-NOT: vorr 1342; IASM-NOT: vmvn 1343 1344 %zext = zext <4 x i1> %cmp to <4 x i32> 1345 ret <4 x i32> %zext 1346} 1347 1348define internal <4 x i32> @cmpUgtV4Float(<4 x float> %a, <4 x float> %b) { 1349; ASM-LABEL:cmpUgtV4Float: 1350; DIS-LABEL:00000750 <cmpUgtV4Float>: 1351; IASM-LABEL:cmpUgtV4Float: 1352 1353entry: 1354 %cmp = fcmp ugt <4 x float> %a, %b 1355 1356; ASM: vcge.f32 q1, q1, q0 1357; ASM-NEXT: vmvn.i32 q1, q1 1358; DIS: 750: f3022e40 1359; DIS-NEXT: 754: f3b025c2 1360; IASM-NOT: vcge 1361; IASM-NOT: vmvn 1362 1363 %zext = zext <4 x i1> %cmp to <4 x i32> 1364 ret <4 x i32> %zext 1365} 1366 1367define internal <4 x i32> @cmpUgeV4Float(<4 x float> %a, <4 x float> %b) { 1368; ASM-LABEL:cmpUgeV4Float: 1369; DIS-LABEL:00000770 <cmpUgeV4Float>: 1370; IASM-LABEL:cmpUgeV4Float: 1371 1372entry: 1373 %cmp = fcmp uge <4 x float> %a, %b 1374 1375; ASM: vcgt.f32 q1, q1, q0 1376; ASM-NEXT: vmvn.i32 q1, q1 1377; DIS: 770: f3222e40 1378; DIS-NEXT: 774: f3b025c2 1379; IASM-NOT: vcgt 1380; IASM-NOT: vmvn 1381 1382 %zext = zext <4 x i1> %cmp to <4 x i32> 1383 ret <4 x i32> %zext 1384} 1385 1386define internal <4 x i32> @cmpUltV4Float(<4 x float> %a, <4 x float> %b) { 1387; ASM-LABEL:cmpUltV4Float: 1388; DIS-LABEL:00000790 <cmpUltV4Float>: 1389; IASM-LABEL:cmpUltV4Float: 1390 1391entry: 1392 %cmp = fcmp ult <4 x float> %a, %b 1393 1394; ASM: vcge.f32 q0, q0, q1 1395; ASM-NEXT: vmvn.i32 q0, q0 1396; DIS: 790: f3000e42 1397; DIS-NEXT: 794: f3b005c0 1398; IASM-NOT: vcge 1399; IASM-NOT: vmvn 1400 1401 %zext = zext <4 x i1> %cmp to <4 x i32> 1402 ret <4 x i32> %zext 1403} 1404 1405define internal <4 x i32> @cmpUleV4Float(<4 x float> %a, <4 x float> %b) { 1406; ASM-LABEL:cmpUleV4Float: 1407; DIS-LABEL:000007b0 <cmpUleV4Float>: 1408; IASM-LABEL:cmpUleV4Float: 1409 1410entry: 1411 %cmp = fcmp ule <4 x float> %a, %b 1412 1413; ASM: vcgt.f32 q0, q0, q1 1414; ASM-NEXT: vmvn.i32 q0, q0 1415; DIS: 7b0: f3200e42 1416; DIS-NEXT: 7b4: f3b005c0 1417; IASM-NOT: vcgt 1418; IASM-NOT: vmvn 1419 1420 %zext = zext <4 x i1> %cmp to <4 x i32> 1421 ret <4 x i32> %zext 1422} 1423 1424define internal <4 x i32> @cmpTrueV4Float(<4 x float> %a, <4 x float> %b) { 1425; ASM-LABEL:cmpTrueV4Float: 1426; DIS-LABEL:000007d0 <cmpTrueV4Float>: 1427; IASM-LABEL:cmpTrueV4Float: 1428 1429entry: 1430 %cmp = fcmp true <4 x float> %a, %b 1431 1432; ASM: vmov.i32 q0, #1 1433; DIS: 7d0: f2800051 1434; IASM-NOT: vmov 1435 1436 %zext = zext <4 x i1> %cmp to <4 x i32> 1437 ret <4 x i32> %zext 1438} 1439