1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * Contributor: Mahavir Jain <mjain@marvell.com>
7 */
8
9 #include <common.h>
10 #include <time.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/armada100.h>
13
14 /*
15 * Timer registers
16 * Refer Section A.6 in Datasheet
17 */
18 struct armd1tmr_registers {
19 u32 clk_ctrl; /* Timer clk control reg */
20 u32 match[9]; /* Timer match registers */
21 u32 count[3]; /* Timer count registers */
22 u32 status[3];
23 u32 ie[3];
24 u32 preload[3]; /* Timer preload value */
25 u32 preload_ctrl[3];
26 u32 wdt_match_en;
27 u32 wdt_match_r;
28 u32 wdt_val;
29 u32 wdt_sts;
30 u32 icr[3];
31 u32 wdt_icr;
32 u32 cer; /* Timer count enable reg */
33 u32 cmr;
34 u32 ilr[3];
35 u32 wcr;
36 u32 wfar;
37 u32 wsar;
38 u32 cvwr;
39 };
40
41 #define TIMER 0 /* Use TIMER 0 */
42 /* Each timer has 3 match registers */
43 #define MATCH_CMP(x) ((3 * TIMER) + x)
44 #define TIMER_LOAD_VAL 0xffffffff
45 #define COUNT_RD_REQ 0x1
46
47 DECLARE_GLOBAL_DATA_PTR;
48 /* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
49
50 /* For preventing risk of instability in reading counter value,
51 * first set read request to register cvwr and then read same
52 * register after it captures counter value.
53 */
read_timer(void)54 ulong read_timer(void)
55 {
56 struct armd1tmr_registers *armd1timers =
57 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
58 volatile int loop=100;
59
60 writel(COUNT_RD_REQ, &armd1timers->cvwr);
61 while (loop--);
62 return(readl(&armd1timers->cvwr));
63 }
64
get_timer_masked(void)65 static ulong get_timer_masked(void)
66 {
67 ulong now = read_timer();
68
69 if (now >= gd->arch.tbl) {
70 /* normal mode */
71 gd->arch.tbu += now - gd->arch.tbl;
72 } else {
73 /* we have an overflow ... */
74 gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
75 }
76 gd->arch.tbl = now;
77
78 return gd->arch.tbu;
79 }
80
get_timer(ulong base)81 ulong get_timer(ulong base)
82 {
83 return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
84 base);
85 }
86
__udelay(unsigned long usec)87 void __udelay(unsigned long usec)
88 {
89 ulong delayticks;
90 ulong endtime;
91
92 delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
93 endtime = get_timer_masked() + delayticks;
94
95 while (get_timer_masked() < endtime);
96 }
97
98 /*
99 * init the Timer
100 */
timer_init(void)101 int timer_init(void)
102 {
103 struct armd1apb1_registers *apb1clkres =
104 (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
105 struct armd1tmr_registers *armd1timers =
106 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
107
108 /* Enable Timer clock at 3.25 MHZ */
109 writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
110
111 /* load value into timer */
112 writel(0x0, &armd1timers->clk_ctrl);
113 /* Use Timer 0 Match Resiger 0 */
114 writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
115 /* Preload value is 0 */
116 writel(0x0, &armd1timers->preload[TIMER]);
117 /* Enable match comparator 0 for Timer 0 */
118 writel(0x1, &armd1timers->preload_ctrl[TIMER]);
119
120 /* Enable timer 0 */
121 writel(0x1, &armd1timers->cer);
122 /* init the gd->arch.tbu and gd->arch.tbl value */
123 gd->arch.tbl = read_timer();
124 gd->arch.tbu = 0;
125
126 return 0;
127 }
128
129 #define MPMU_APRR_WDTR (1<<4)
130 #define TMR_WFAR 0xbaba /* WDT Register First key */
131 #define TMP_WSAR 0xeb10 /* WDT Register Second key */
132
133 /*
134 * This function uses internal Watchdog Timer
135 * based reset mechanism.
136 * Steps to write watchdog registers (protected access)
137 * 1. Write key value to TMR_WFAR reg.
138 * 2. Write key value to TMP_WSAR reg.
139 * 3. Perform write operation.
140 */
reset_cpu(unsigned long ignored)141 void reset_cpu (unsigned long ignored)
142 {
143 struct armd1mpmu_registers *mpmu =
144 (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
145 struct armd1tmr_registers *armd1timers =
146 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
147 u32 val;
148
149 /* negate hardware reset to the WDT after system reset */
150 val = readl(&mpmu->aprr);
151 val = val | MPMU_APRR_WDTR;
152 writel(val, &mpmu->aprr);
153
154 /* reset/enable WDT clock */
155 writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
156 readl(&mpmu->wdtpcr);
157 writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
158 readl(&mpmu->wdtpcr);
159
160 /* clear previous WDT status */
161 writel(TMR_WFAR, &armd1timers->wfar);
162 writel(TMP_WSAR, &armd1timers->wsar);
163 writel(0, &armd1timers->wdt_sts);
164
165 /* set match counter */
166 writel(TMR_WFAR, &armd1timers->wfar);
167 writel(TMP_WSAR, &armd1timers->wsar);
168 writel(0xf, &armd1timers->wdt_match_r);
169
170 /* enable WDT reset */
171 writel(TMR_WFAR, &armd1timers->wfar);
172 writel(TMP_WSAR, &armd1timers->wsar);
173 writel(0x3, &armd1timers->wdt_match_en);
174
175 while(1);
176 }
177
178 /*
179 * This function is derived from PowerPC code (read timebase as long long).
180 * On ARM it just returns the timer value.
181 */
get_ticks(void)182 unsigned long long get_ticks(void)
183 {
184 return get_timer(0);
185 }
186
187 /*
188 * This function is derived from PowerPC code (timebase clock frequency).
189 * On ARM it returns the number of timer ticks per second.
190 */
get_tbclk(void)191 ulong get_tbclk (void)
192 {
193 return (ulong)CONFIG_SYS_HZ;
194 }
195