1SoC overview 2 3 1. LS1043A 4 2. LS1088A 5 3. LS2080A 6 4. LS1012A 7 5. LS1046A 8 6. LS2088A 9 7. LS2081A 10 8. LX2160A 11 9. LS1028A 12 13LS1043A 14--------- 15The LS1043A integrated multicore processor combines four ARM Cortex-A53 16processor cores with datapath acceleration optimized for L2/3 packet 17processing, single pass security offload and robust traffic management 18and quality of service. 19 20The LS1043A SoC includes the following function and features: 21 - Four 64-bit ARM Cortex-A53 CPUs 22 - 1 MB unified L2 Cache 23 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving 24 support 25 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the 26 the following functions: 27 - Packet parsing, classification, and distribution (FMan) 28 - Queue management for scheduling, packet sequencing, and congestion 29 management (QMan) 30 - Hardware buffer management for buffer allocation and de-allocation (BMan) 31 - Cryptography acceleration (SEC) 32 - Ethernet interfaces by FMan 33 - Up to 1 x XFI supporting 10G interface 34 - Up to 1 x QSGMII 35 - Up to 4 x SGMII supporting 1000Mbps 36 - Up to 2 x SGMII supporting 2500Mbps 37 - Up to 2 x RGMII supporting 1000Mbps 38 - High-speed peripheral interfaces 39 - Three PCIe 2.0 controllers, one supporting x4 operation 40 - One serial ATA (SATA 3.0) controllers 41 - Additional peripheral interfaces 42 - Three high-speed USB 3.0 controllers with integrated PHY 43 - Enhanced secure digital host controller (eSDXC/eMMC) 44 - Quad Serial Peripheral Interface (QSPI) Controller 45 - Serial peripheral interface (SPI) controller 46 - Four I2C controllers 47 - Two DUARTs 48 - Integrated flash controller supporting NAND and NOR flash 49 - QorIQ platform's trust architecture 2.1 50 51LS1088A 52-------- 53The QorIQ LS1088A processor is built on the Layerscape 54architecture combining eight ARM A53 processor cores 55with advanced, high-performance datapath acceleration 56and networks, peripheral interfaces required for 57networking, wireless infrastructure, and general-purpose 58embedded applications. 59 60LS1088A is compliant with the Layerscape Chassis Generation 3. 61 62Features summary: 63 - 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs 64 - Cores are in 2 cluster of 4-cores each 65 - 1MB L2 - Cache per cluster 66 - Cache coherent interconnect (CCI-400) 67 - 1 64-bit DDR4 SDRAM memory controller with ECC 68 - Data path acceleration architecture 2.0 (DPAA2) 69 - 4-Lane 10GHz SerDes comprising of WRIOP 70 - 4-Lane 10GHz SerDes comprising of PCI, SATA, uQE(TDM/HLDC/UART) 71 - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs 72 - QSPI, SPI, IFC2.0 supporting NAND, NOR flash 73 - 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc 74 - 2 DUARTs 75 - 4 I2C, GPIO 76 - Thermal monitor unit(TMU) 77 - 4 Flextimers and 1 generic timer 78 - Support for hardware virtualization and partitioning enforcement 79 - QorIQ platform's trust architecture 3.0 80 - Service processor (SP) provides pre-boot initialization and secure-boot 81 capabilities 82 83LS2080A 84-------- 85The LS2080A integrated multicore processor combines eight ARM Cortex-A57 86processor cores with high-performance data path acceleration logic and network 87and peripheral bus interfaces required for networking, telecom/datacom, 88wireless infrastructure, and mil/aerospace applications. 89 90The LS2080A SoC includes the following function and features: 91 92 - Eight 64-bit ARM Cortex-A57 CPUs 93 - 1 MB platform cache with ECC 94 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support 95 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by 96 the AIOP 97 - Data path acceleration architecture (DPAA2) incorporating acceleration for 98 the following functions: 99 - Packet parsing, classification, and distribution (WRIOP) 100 - Queue and Hardware buffer management for scheduling, packet sequencing, and 101 congestion management, buffer allocation and de-allocation (QBMan) 102 - Cryptography acceleration (SEC) at up to 10 Gbps 103 - RegEx pattern matching acceleration (PME) at up to 10 Gbps 104 - Decompression/compression acceleration (DCE) at up to 20 Gbps 105 - Accelerated I/O processing (AIOP) at up to 20 Gbps 106 - QDMA engine 107 - 16 SerDes lanes at up to 10.3125 GHz 108 - Ethernet interfaces 109 - Up to eight 10 Gbps Ethernet MACs 110 - Up to eight 1 / 2.5 Gbps Ethernet MACs 111 - High-speed peripheral interfaces 112 - Four PCIe 3.0 controllers, one supporting SR-IOV 113 - Additional peripheral interfaces 114 - Two serial ATA (SATA 3.0) controllers 115 - Two high-speed USB 3.0 controllers with integrated PHY 116 - Enhanced secure digital host controller (eSDXC/eMMC) 117 - Serial peripheral interface (SPI) controller 118 - Quad Serial Peripheral Interface (QSPI) Controller 119 - Four I2C controllers 120 - Two DUARTs 121 - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash 122 - Support for hardware virtualization and partitioning enforcement 123 - QorIQ platform's trust architecture 3.0 124 - Service processor (SP) provides pre-boot initialization and secure-boot 125 capabilities 126 127LS1012A 128-------- 129The LS1012A features an advanced 64-bit ARM v8 Cortex- 130A53 processor, with 32 KB of parity protected L1-I cache, 13132 KB of ECC protected L1-D cache, as well as 256 KB of 132ECC protected L2 cache. 133 134The LS1012A SoC includes the following function and features: 135 - One 64-bit ARM v8 Cortex-A53 core with the following capabilities: 136 - ARM v8 cryptography extensions 137 - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports 138 16-/8-bit operation (no ECC support) 139 - ARM core-link CCI-400 cache coherent interconnect 140 - Packet Forwarding Engine (PFE) 141 - Cryptography acceleration (SEC) 142 - Ethernet interfaces supported by PFE: 143 - One Configurable x3 SerDes: 144 Two Serdes PLLs supported for usage by any SerDes data lane 145 Support for up to 6 GBaud operation 146 - High-speed peripheral interfaces: 147 - One PCI Express Gen2 controller, supporting x1 operation 148 - One serial ATA (SATA Gen 3.0) controller 149 - One USB 3.0/2.0 controller with integrated PHY 150 - One USB 2.0 controller with ULPI interface. . 151 - Additional peripheral interfaces: 152 - One quad serial peripheral interface (QuadSPI) controller 153 - One serial peripheral interface (SPI) controller 154 - Two enhanced secure digital host controllers 155 - Two I2C controllers 156 - One 16550 compliant DUART (two UART interfaces) 157 - Two general purpose IOs (GPIO) 158 - Two FlexTimers 159 - Five synchronous audio interfaces (SAI) 160 - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading 161 - Single-source clocking solution enabling generation of core, platform, 162 DDR, SerDes, and USB clocks from a single external crystal and internal 163 crystaloscillator 164 - Thermal monitor unit (TMU) with +/- 3C accuracy 165 - Two WatchDog timers 166 - ARM generic timer 167 - QorIQ platform's trust architecture 2.1 168 169LS1046A 170-------- 171The LS1046A integrated multicore processor combines four ARM Cortex-A72 172processor cores with datapath acceleration optimized for L2/3 packet 173processing, single pass security offload and robust traffic management 174and quality of service. 175 176The LS1046A SoC includes the following function and features: 177 - Four 64-bit ARM Cortex-A72 CPUs 178 - 2 MB unified L2 Cache 179 - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving 180 support 181 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the 182 the following functions: 183 - Packet parsing, classification, and distribution (FMan) 184 - Queue management for scheduling, packet sequencing, and congestion 185 management (QMan) 186 - Hardware buffer management for buffer allocation and de-allocation (BMan) 187 - Cryptography acceleration (SEC) 188 - Two Configurable x4 SerDes 189 - Two PLLs per four-lane SerDes 190 - Support for 10G operation 191 - Ethernet interfaces by FMan 192 - Up to 2 x XFI supporting 10G interface (MAC 9, 10) 193 - Up to 1 x QSGMII (MAC 5, 6, 10, 1) 194 - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) 195 - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10) 196 - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4) 197 - High-speed peripheral interfaces 198 - Three PCIe 3.0 controllers, one supporting x4 operation 199 - One serial ATA (SATA 3.0) controllers 200 - Additional peripheral interfaces 201 - Three high-speed USB 3.0 controllers with integrated PHY 202 - Enhanced secure digital host controller (eSDXC/eMMC) 203 - Quad Serial Peripheral Interface (QSPI) Controller 204 - Serial peripheral interface (SPI) controller 205 - Four I2C controllers 206 - Two DUARTs 207 - Integrated flash controller (IFC) supporting NAND and NOR flash 208 - QorIQ platform's trust architecture 2.1 209 210LS2088A 211-------- 212The LS2088A integrated multicore processor combines eight ARM Cortex-A72 213processor cores with high-performance data path acceleration logic and network 214and peripheral bus interfaces required for networking, telecom/datacom, 215wireless infrastructure, and mil/aerospace applications. 216 217The LS2088A SoC includes the following function and features: 218 219 - Eight 64-bit ARM Cortex-A72 CPUs 220 - 1 MB platform cache with ECC 221 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support 222 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by 223 the AIOP 224 - Data path acceleration architecture (DPAA2) incorporating acceleration for 225 the following functions: 226 - Packet parsing, classification, and distribution (WRIOP) 227 - Queue and Hardware buffer management for scheduling, packet sequencing, and 228 congestion management, buffer allocation and de-allocation (QBMan) 229 - Cryptography acceleration (SEC) at up to 10 Gbps 230 - RegEx pattern matching acceleration (PME) at up to 10 Gbps 231 - Decompression/compression acceleration (DCE) at up to 20 Gbps 232 - Accelerated I/O processing (AIOP) at up to 20 Gbps 233 - QDMA engine 234 - 16 SerDes lanes at up to 10.3125 GHz 235 - Ethernet interfaces 236 - Up to eight 10 Gbps Ethernet MACs 237 - Up to eight 1 / 2.5 Gbps Ethernet MACs 238 - High-speed peripheral interfaces 239 - Four PCIe 3.0 controllers, one supporting SR-IOV 240 - Additional peripheral interfaces 241 - Two serial ATA (SATA 3.0) controllers 242 - Two high-speed USB 3.0 controllers with integrated PHY 243 - Enhanced secure digital host controller (eSDXC/eMMC) 244 - Serial peripheral interface (SPI) controller 245 - Quad Serial Peripheral Interface (QSPI) Controller 246 - Four I2C controllers 247 - Two DUARTs 248 - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash 249 - Support for hardware virtualization and partitioning enforcement 250 - QorIQ platform's trust architecture 3.0 251 - Service processor (SP) provides pre-boot initialization and secure-boot 252 capabilities 253 254LS2088A SoC has 3 more similar SoC personalities 2551)LS2048A, few difference w.r.t. LS2088A: 256 a) Four 64-bit ARM v8 Cortex-A72 CPUs 257 2582)LS2084A, few difference w.r.t. LS2088A: 259 a) No AIOP 260 b) No 32-bit DDR3 SDRAM memory 261 c) 5 * 1/10G + 5 *1G WRIOP 262 d) No L2 switch 263 2643)LS2044A, few difference w.r.t. LS2084A: 265 a) Four 64-bit ARM v8 Cortex-A72 CPUs 266 267LS2081A 268-------- 269LS2081A is 40-pin derivative of LS2084A. 270So feature-wise it is same as LS2084A. 271Refer to LS2084A(LS2088A) section above for details. 272 273It has one more similar SoC personality 2741)LS2041A, few difference w.r.t. LS2081A: 275 a) Four 64-bit ARM v8 Cortex-A72 CPUs 276 277LX2160A 278-------- 279The QorIQ LX2160A processor is built in the 16FFC process on 280the Layerscape architecture combining sixteen ARM A72 processor 281cores with advanced, high-performance datapath acceleration and 282network, peripheral interfaces required for networking, wireless 283infrastructure, storage, and general-purpose embedded applications. 284 285LX2160A is compliant with the Layerscape Chassis Generation 3.2. 286 287The LX2160A SoC includes the following function and features: 288 Sixteen 32-bit / 64-bit ARM v8 A72 CPUs 289 Cache Coherent Interconnect Fabric (CCN508 aka “Eliot”) 290 Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC. 291 Data path acceleration architecture (DPAA2) 292 24 Serdes lanes at up to 25 GHz 293 Ethernet interfaces 294 Single WRIOP tile supporting 130Gbps using 18 MACs 295 Support for 10G-SXGMII (aka USXGMII). 296 Support for SGMII (and 1000Base-KX) 297 Support for XFI (and 10GBase-KR) 298 Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). 299 Support for XLAUI (and 40GBase-KR4) for 40G. 300 Support for two RGMII parallel interfaces. 301 Energy efficient Ethernet support (802.3az) 302 IEEE 1588 support. 303 High-speed peripheral interfaces 304 Two PCIe Gen 4.0 8-lane controllers supporting SR-IOV, 305 Four PCIe Gen 4.0 4-lane controllers. 306 Four serial ATA (SATA 3.0) controllers. 307 Two USB 3.0 controllers with integrated PHY 308 Two Enhanced secure digital host controllers 309 Two Controller Area Network (CAN) modules 310 Flexible Serial peripheral interface (FlexSPI) controller. 311 Three Serial peripheral interface (SPI) controllers. 312 Eight I2C Controllers. 313 Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. 314 General Purpose IO (GPIO) 315 Support for hardware virtualization and partitioning (ARM MMU-500) 316 Support for GIC (ARM GIC-500) 317 QorIQ platform Trust Architecture 3.0 318 One Secure WatchDog timer and one Non-Secure Watchdog timer. 319 ARM Generic Timer 320 Two Flextimers 321 Debug supporting run control, data acquisition, high-speed trace, 322 performance/event monitoring 323 Thermal Monitor Unit (TMU) with +/- 2C accuracy 324 Support for Voltage ID (VID) for yield improvement 325 326LX2160A SoC has 2 more similar SoC personalities 3271)LX2120A, few difference w.r.t. LX2160A: 328 a) Twelve 64-bit ARM v8 Cortex-A72 CPUs 329 3302)LX2080A, few difference w.r.t. LX2160A: 331 a) Eight 64-bit ARM v8 Cortex-A72 CPUs 332 333 334LS1028A 335-------- 336The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with 337a GPU and LCD controller, as well as two TSN-enabled Ethernet controllers and 338a TSNenabled 4-port switch. 339 340The high performance Cortex-A72 cores, performing above 16,000 CoreMarks, 341combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and 342Octal/Quad SPI interfaces provide capabilities for a number of industrial and 343embedded applications. The device provides excellent integration with the 344new Time-Sensitive Networking standard, and enables a number of 345TSN applications. 346 347The LS1028A SoC includes the following function and features: 348 - Two 64-bit ARM v8 A72 CPUs 349 - Cache Coherent interconnect (CCI-400) 350 - One 32-bit DDR3L/DDR4 SDRAM memory controller with ECC 351 - eDP/Displayport interface 352 - Graphics processing unit 353 - One Configurable x4 SerDes 354 - Ethernet interfaces 355 - Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one 356 ethernet MAC supporting 1G, 100M, 10M. 357 - Switched: TSN IP to support four 2.5/1G interfaces. 358 - None of the MACs support MACSEC 359 - Support for RGMII, SGMII (and 1000Base-KX), SGMII 2.5x, QSGMII 360 - Support for 10G-SXGMII and 10G-QXGMII. 361 - Energy efficient Ethernet support (802.3az) 362 - IEEE 1588 support 363 - High-speed peripheral interfaces 364 - Two PCIe 3.0 controllers, one supporting x4 operation 365 - One serial ATA (SATA 3.0) controller 366 - Additional peripheral interfaces 367 - Two high-speed USB 2.0/3.0 controllers with integrated PHY each 368 supporting host or device modes 369 - Two Enhanced secure digital host controllers (SD/SDIO/eMMC) 370 - Two Serial peripheral interface (SPI) controllers 371 - Eight I2C controllers 372 - Two UART controllers 373 - Additional six Industrual UARTs (LPUART). 374 - One FlexSPI controller 375 - General Purpose IO (GPIO) 376 - Two CAN-FD interfaces 377 - Eight Flextimers with PWM I/O 378 - Support for hardware virtualization and partitioning enforcement 379 - Layerscape Trust Architecture 380 - Service Processor (SP) provides pre-boot initialization and secure-boot 381 capabilities 382