1/* 2 * Copyright (C) 2016 Marvell Technology Group Ltd. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPLv2 or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43/* 44 * Device Tree file for Marvell Armada CP110 Slave. 45 */ 46 47#include <dt-bindings/comphy/comphy_data.h> 48 49/ { 50 cp110-slave { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 compatible = "simple-bus"; 54 interrupt-parent = <&gic>; 55 ranges; 56 57 config-space { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 compatible = "simple-bus"; 61 interrupt-parent = <&gic>; 62 ranges = <0x0 0x0 0xf4000000 0x2000000>; 63 64 cps_ethernet: ethernet@0 { 65 compatible = "marvell,armada-7k-pp22"; 66 reg = <0x0 0x100000>, <0x129000 0xb000>; 67 clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>; 68 clock-names = "pp_clk", "gop_clk", "mg_clk"; 69 status = "disabled"; 70 dma-coherent; 71 72 cps_eth0: eth0 { 73 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 74 port-id = <0>; 75 gop-port-id = <0>; 76 status = "disabled"; 77 }; 78 79 cps_eth1: eth1 { 80 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 81 port-id = <1>; 82 gop-port-id = <2>; 83 status = "disabled"; 84 }; 85 86 cps_eth2: eth2 { 87 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 88 port-id = <2>; 89 gop-port-id = <3>; 90 status = "disabled"; 91 }; 92 }; 93 94 cps_mdio: mdio@12a200 { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 compatible = "marvell,orion-mdio"; 98 reg = <0x12a200 0x10>; 99 device-name = "cps-mdio"; 100 }; 101 102 cps_xmdio: mdio@12a600 { 103 #address-cells = <1>; 104 #size-cells = <0>; 105 compatible = "marvell,xmdio"; 106 reg = <0x12a600 0x16>; 107 status = "disabled"; 108 device-name = "cps-xmdio"; 109 }; 110 111 cps_syscon0: system-controller@440000 { 112 compatible = "marvell,cp110-system-controller0", 113 "syscon"; 114 reg = <0x440000 0x1000>; 115 #clock-cells = <2>; 116 core-clock-output-names = 117 "cps-apll", "cps-ppv2-core", "cps-eip", 118 "cps-core", "cps-nand-core"; 119 gate-clock-output-names = 120 "cps-audio", "cps-communit", "cps-nand", 121 "cps-ppv2", "cps-sdio", "cps-mg-domain", 122 "cps-mg-core", "cps-xor1", "cps-xor0", 123 "cps-gop-dp", "none", "cps-pcie_x10", 124 "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor", 125 "cps-sata", "cps-sata-usb", "cps-main", 126 "cps-sd-mmc", "none", "none", 127 "cps-slow-io", "cps-usb3h0", "cps-usb3h1", 128 "cps-usb3dev", "cps-eip150", "cps-eip197"; 129 }; 130 131 cps_pinctl: cps-pinctl@440000 { 132 compatible = "marvell,mvebu-pinctrl", 133 "marvell,armada-8k-cps-pinctrl"; 134 bank-name ="cp1-110"; 135 reg = <0x440000 0x20>; 136 pin-count = <63>; 137 max-func = <0xf>; 138 139 cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 { 140 marvell,pins = < 0 1 2 3 4 5 6 7 141 8 9 10 11 >; 142 marvell,function = <3>; 143 }; 144 cps_spi1_pins: cps-spi-pins-1 { 145 marvell,pins = < 13 14 15 16 >; 146 marvell,function = <3>; 147 }; 148 }; 149 150 cps_gpio0: gpio@440100 { 151 compatible = "marvell,orion-gpio"; 152 reg = <0x440100 0x40>; 153 ngpios = <32>; 154 gpiobase = <20>; 155 gpio-controller; 156 #gpio-cells = <2>; 157 }; 158 159 cps_gpio1: gpio@440140 { 160 compatible = "marvell,orion-gpio"; 161 reg = <0x440140 0x40>; 162 ngpios = <31>; 163 gpiobase = <52>; 164 gpio-controller; 165 #gpio-cells = <2>; 166 }; 167 168 cps_sata0: sata@540000 { 169 compatible = "marvell,armada-8k-ahci"; 170 reg = <0x540000 0x30000>; 171 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&cps_syscon0 1 15>; 173 status = "disabled"; 174 }; 175 176 cps_usb3_0: usb3@500000 { 177 compatible = "marvell,armada-8k-xhci", 178 "generic-xhci"; 179 reg = <0x500000 0x4000>; 180 dma-coherent; 181 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&cps_syscon0 1 22>; 183 status = "disabled"; 184 }; 185 186 cps_usb3_1: usb3@510000 { 187 compatible = "marvell,armada-8k-xhci", 188 "generic-xhci"; 189 reg = <0x510000 0x4000>; 190 dma-coherent; 191 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 192 clocks = <&cps_syscon0 1 23>; 193 status = "disabled"; 194 }; 195 196 cps_xor0: xor@6a0000 { 197 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 198 reg = <0x6a0000 0x1000>, 199 <0x6b0000 0x1000>; 200 dma-coherent; 201 msi-parent = <&gic_v2m0>; 202 clocks = <&cps_syscon0 1 8>; 203 }; 204 205 cps_xor1: xor@6c0000 { 206 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 207 reg = <0x6c0000 0x1000>, 208 <0x6d0000 0x1000>; 209 dma-coherent; 210 msi-parent = <&gic_v2m0>; 211 clocks = <&cps_syscon0 1 7>; 212 }; 213 214 cps_spi0: spi@700600 { 215 compatible = "marvell,armada-380-spi"; 216 reg = <0x700600 0x50>; 217 #address-cells = <0x1>; 218 #size-cells = <0x0>; 219 cell-index = <1>; 220 clocks = <&cps_syscon0 0 3>; 221 status = "disabled"; 222 }; 223 224 cps_spi1: spi@700680 { 225 compatible = "marvell,armada-380-spi"; 226 reg = <0x700680 0x50>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 cell-index = <2>; 230 clocks = <&cps_syscon0 1 21>; 231 status = "disabled"; 232 }; 233 234 cps_i2c0: i2c@701000 { 235 compatible = "marvell,mv78230-i2c"; 236 reg = <0x701000 0x20>; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&cps_syscon0 1 21>; 241 status = "disabled"; 242 }; 243 244 cps_i2c1: i2c@701100 { 245 compatible = "marvell,mv78230-i2c"; 246 reg = <0x701100 0x20>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&cps_syscon0 1 21>; 251 status = "disabled"; 252 }; 253 254 cps_comphy: comphy@441000 { 255 compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; 256 reg = <0x441000 0x8>, 257 <0x120000 0x8>; 258 mux-bitcount = <4>; 259 max-lanes = <6>; 260 }; 261 262 cps_utmi0: utmi@580000 { 263 compatible = "marvell,mvebu-utmi-2.6.0"; 264 reg = <0x580000 0x1000>, /* utmi-unit */ 265 <0x440420 0x4>, /* usb-cfg */ 266 <0x440440 0x4>; /* utmi-cfg */ 267 utmi-port = <UTMI_PHY_TO_USB3_HOST0>; 268 status = "disabled"; 269 }; 270 }; 271 272 cps_pcie0: pcie@f4600000 { 273 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 274 reg = <0 0xf4600000 0 0x10000>, 275 <0 0xfaf00000 0 0x80000>; 276 reg-names = "ctrl", "config"; 277 #address-cells = <3>; 278 #size-cells = <2>; 279 #interrupt-cells = <1>; 280 device_type = "pci"; 281 dma-coherent; 282 msi-parent = <&gic_v2m0>; 283 284 bus-range = <0 0xff>; 285 ranges = 286 /* downstream I/O */ 287 <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000 288 /* non-prefetchable memory */ 289 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; 290 interrupt-map-mask = <0 0 0 0>; 291 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 292 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 293 num-lanes = <1>; 294 clocks = <&cps_syscon0 1 13>; 295 status = "disabled"; 296 }; 297 298 cps_pcie1: pcie@f4620000 { 299 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 300 reg = <0 0xf4620000 0 0x10000>, 301 <0 0xfbf00000 0 0x80000>; 302 reg-names = "ctrl", "config"; 303 #address-cells = <3>; 304 #size-cells = <2>; 305 #interrupt-cells = <1>; 306 device_type = "pci"; 307 dma-coherent; 308 msi-parent = <&gic_v2m0>; 309 310 bus-range = <0 0xff>; 311 ranges = 312 /* downstream I/O */ 313 <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000 314 /* non-prefetchable memory */ 315 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; 316 interrupt-map-mask = <0 0 0 0>; 317 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 318 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 319 320 num-lanes = <1>; 321 clocks = <&cps_syscon0 1 11>; 322 status = "disabled"; 323 }; 324 325 cps_pcie2: pcie@f4640000 { 326 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 327 reg = <0 0xf4640000 0 0x10000>, 328 <0 0xfcf00000 0 0x80000>; 329 reg-names = "ctrl", "config"; 330 #address-cells = <3>; 331 #size-cells = <2>; 332 #interrupt-cells = <1>; 333 device_type = "pci"; 334 dma-coherent; 335 msi-parent = <&gic_v2m0>; 336 337 bus-range = <0 0xff>; 338 ranges = 339 /* downstream I/O */ 340 <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000 341 /* non-prefetchable memory */ 342 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; 343 interrupt-map-mask = <0 0 0 0>; 344 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 345 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 346 347 num-lanes = <1>; 348 clocks = <&cps_syscon0 1 12>; 349 status = "disabled"; 350 }; 351 }; 352}; 353