1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * NXP ls1028a SOC common device tree source 4 * 5 * Copyright 2019 NXP 6 * 7 */ 8 9/ { 10 compatible = "fsl,ls1028a"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 sysclk: sysclk { 16 compatible = "fixed-clock"; 17 #clock-cells = <0>; 18 clock-frequency = <100000000>; 19 clock-output-names = "sysclk"; 20 }; 21 22 clockgen: clocking@1300000 { 23 compatible = "fsl,ls1028a-clockgen"; 24 reg = <0x0 0x1300000 0x0 0xa0000>; 25 #clock-cells = <2>; 26 clocks = <&sysclk>; 27 }; 28 29 memory@01080000 { 30 device_type = "memory"; 31 reg = <0x00000000 0x01080000 0 0x80000000>; 32 /* DRAM space - 1, size : 2 GB DRAM */ 33 }; 34 35 gic: interrupt-controller@6000000 { 36 compatible = "arm,gic-v3"; 37 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 38 <0x0 0x06040000 0 0x40000>; 39 #interrupt-cells = <3>; 40 interrupt-controller; 41 interrupts = <1 9 0x4>; 42 }; 43 44 timer { 45 compatible = "arm,armv8-timer"; 46 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ 47 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ 48 <1 11 0x8>, /* Virtual PPI, active-low */ 49 <1 10 0x8>; /* Hypervisor PPI, active-low */ 50 }; 51 52 fspi: flexspi@20C0000 { 53 compatible = "nxp,dn-fspi"; 54 #address-cells = <1>; 55 #size-cells = <0>; 56 reg = <0x0 0x20C0000 0x0 0x10000>, 57 <0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/ 58 reg-names = "FSPI", "FSPI-memory"; 59 num-cs = <1>; 60 status = "disabled"; 61 }; 62 63 serial0: serial@21c0500 { 64 device_type = "serial"; 65 compatible = "fsl,ns16550", "ns16550a"; 66 reg = <0x0 0x21c0500 0x0 0x100>; 67 interrupts = <0 32 0x1>; /* edge triggered */ 68 status = "disabled"; 69 }; 70 71 serial1: serial@21c0600 { 72 device_type = "serial"; 73 compatible = "fsl,ns16550", "ns16550a"; 74 reg = <0x0 0x21c0600 0x0 0x100>; 75 interrupts = <0 32 0x1>; /* edge triggered */ 76 status = "disabled"; 77 }; 78 79 pcie@3400000 { 80 compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; 81 reg = <0x00 0x03400000 0x0 0x80000 82 0x00 0x03480000 0x0 0x40000 /* lut registers */ 83 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ 84 0x80 0x00000000 0x0 0x20000>; /* configuration space */ 85 reg-names = "dbi", "lut", "ctrl", "config"; 86 #address-cells = <3>; 87 #size-cells = <2>; 88 device_type = "pci"; 89 num-lanes = <4>; 90 bus-range = <0x0 0xff>; 91 ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ 92 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 93 }; 94 95 pcie@3500000 { 96 compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; 97 reg = <0x00 0x03500000 0x0 0x80000 98 0x00 0x03580000 0x0 0x40000 /* lut registers */ 99 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ 100 0x88 0x00000000 0x0 0x20000>; /* configuration space */ 101 reg-names = "dbi", "lut", "ctrl", "config"; 102 #address-cells = <3>; 103 #size-cells = <2>; 104 device_type = "pci"; 105 num-lanes = <4>; 106 bus-range = <0x0 0xff>; 107 ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ 108 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 109 }; 110 111 pcie@1f0000000 { 112 compatible = "pci-host-ecam-generic"; 113 /* ECAM bus 0, HW has more space reserved but not populated */ 114 bus-range = <0x0 0x0>; 115 reg = <0x01 0xf0000000 0x0 0x100000>; 116 #address-cells = <3>; 117 #size-cells = <2>; 118 device_type = "pci"; 119 ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>; 120 enetc0: pci@0,0 { 121 reg = <0x000000 0 0 0 0>; 122 status = "disabled"; 123 }; 124 enetc1: pci@0,1 { 125 reg = <0x000100 0 0 0 0>; 126 status = "disabled"; 127 }; 128 enetc2: pci@0,2 { 129 reg = <0x000200 0 0 0 0>; 130 status = "okay"; 131 phy-mode = "internal"; 132 }; 133 mdio0: pci@0,3 { 134 #address-cells=<0>; 135 #size-cells=<1>; 136 reg = <0x000300 0 0 0 0>; 137 status = "disabled"; 138 }; 139 enetc6: pci@0,6 { 140 reg = <0x000600 0 0 0 0>; 141 status = "okay"; 142 phy-mode = "internal"; 143 }; 144 }; 145 146 i2c0: i2c@2000000 { 147 compatible = "fsl,vf610-i2c"; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 reg = <0x0 0x2000000 0x0 0x10000>; 151 interrupts = <0 34 0x4>; 152 clock-names = "i2c"; 153 clocks = <&clockgen 4 0>; 154 status = "disabled"; 155 }; 156 157 i2c1: i2c@2010000 { 158 compatible = "fsl,vf610-i2c"; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 reg = <0x0 0x2010000 0x0 0x10000>; 162 interrupts = <0 34 0x4>; 163 clock-names = "i2c"; 164 clocks = <&clockgen 4 0>; 165 status = "disabled"; 166 }; 167 168 i2c2: i2c@2020000 { 169 compatible = "fsl,vf610-i2c"; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 reg = <0x0 0x2020000 0x0 0x10000>; 173 interrupts = <0 35 0x4>; 174 clock-names = "i2c"; 175 clocks = <&clockgen 4 0>; 176 status = "disabled"; 177 }; 178 179 i2c3: i2c@2030000 { 180 compatible = "fsl,vf610-i2c"; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 reg = <0x0 0x2030000 0x0 0x10000>; 184 interrupts = <0 35 0x4>; 185 clock-names = "i2c"; 186 clocks = <&clockgen 4 0>; 187 status = "disabled"; 188 }; 189 190 i2c4: i2c@2040000 { 191 compatible = "fsl,vf610-i2c"; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 reg = <0x0 0x2040000 0x0 0x10000>; 195 interrupts = <0 74 0x4>; 196 clock-names = "i2c"; 197 clocks = <&clockgen 4 0>; 198 status = "disabled"; 199 }; 200 201 i2c5: i2c@2050000 { 202 compatible = "fsl,vf610-i2c"; 203 #address-cells = <1>; 204 #size-cells = <0>; 205 reg = <0x0 0x2050000 0x0 0x10000>; 206 interrupts = <0 74 0x4>; 207 clock-names = "i2c"; 208 clocks = <&clockgen 4 0>; 209 status = "disabled"; 210 }; 211 212 i2c6: i2c@2060000 { 213 compatible = "fsl,vf610-i2c"; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 reg = <0x0 0x2060000 0x0 0x10000>; 217 interrupts = <0 75 0x4>; 218 clock-names = "i2c"; 219 clocks = <&clockgen 4 0>; 220 status = "disabled"; 221 }; 222 223 i2c7: i2c@2070000 { 224 compatible = "fsl,vf610-i2c"; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 reg = <0x0 0x2070000 0x0 0x10000>; 228 interrupts = <0 75 0x4>; 229 clock-names = "i2c"; 230 clocks = <&clockgen 4 0>; 231 status = "disabled"; 232 }; 233 234 usb1: usb3@3100000 { 235 compatible = "fsl,layerscape-dwc3"; 236 reg = <0x0 0x3100000 0x0 0x10000>; 237 interrupts = <0 80 0x4>; 238 dr_mode = "host"; 239 status = "disabled"; 240 }; 241 242 usb2: usb3@3110000 { 243 compatible = "fsl,layerscape-dwc3"; 244 reg = <0x0 0x3110000 0x0 0x10000>; 245 interrupts = <0 81 0x4>; 246 dr_mode = "host"; 247 status = "disabled"; 248 }; 249 250 dspi0: dspi@2100000 { 251 compatible = "fsl,vf610-dspi"; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 reg = <0x0 0x2100000 0x0 0x10000>; 255 interrupts = <0 26 0x4>; 256 clock-names = "dspi"; 257 clocks = <&clockgen 4 0>; 258 num-cs = <5>; 259 litte-endian; 260 status = "disabled"; 261 }; 262 263 dspi1: dspi@2110000 { 264 compatible = "fsl,vf610-dspi"; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 reg = <0x0 0x2110000 0x0 0x10000>; 268 interrupts = <0 26 0x4>; 269 clock-names = "dspi"; 270 clocks = <&clockgen 4 0>; 271 num-cs = <5>; 272 little-endian; 273 status = "disabled"; 274 }; 275 276 dspi2: dspi@2120000 { 277 compatible = "fsl,vf610-dspi"; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 reg = <0x0 0x2120000 0x0 0x10000>; 281 interrupts = <0 26 0x4>; 282 clock-names = "dspi"; 283 clocks = <&clockgen 4 0>; 284 num-cs = <5>; 285 little-endian; 286 status = "disabled"; 287 }; 288 289 esdhc0: esdhc@2140000 { 290 compatible = "fsl,esdhc"; 291 reg = <0x0 0x2140000 0x0 0x10000>; 292 interrupts = <0 28 0x4>; 293 big-endian; 294 bus-width = <4>; 295 status = "disabled"; 296 }; 297 298 esdhc1: esdhc@2150000 { 299 compatible = "fsl,esdhc"; 300 reg = <0x0 0x2150000 0x0 0x10000>; 301 interrupts = <0 63 0x4>; 302 big-endian; 303 non-removable; 304 bus-width = <4>; 305 status = "disabled"; 306 }; 307 308 sata: sata@3200000 { 309 compatible = "fsl,ls1028a-ahci"; 310 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ 311 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ 312 reg-names = "sata-base", "ecc-addr"; 313 interrupts = <0 133 4>; 314 status = "disabled"; 315 }; 316 317 cluster1_core0_watchdog: wdt@c000000 { 318 compatible = "arm,sp805-wdt"; 319 reg = <0x0 0xc000000 0x0 0x1000>; 320 }; 321}; 322