1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * NXP ls1088a SOC common device tree source 4 * 5 * Copyright 2017 NXP 6 */ 7 8/ { 9 compatible = "fsl,ls1088a"; 10 interrupt-parent = <&gic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 memory@80000000 { 15 device_type = "memory"; 16 reg = <0x00000000 0x80000000 0 0x80000000>; 17 /* DRAM space - 1, size : 2 GB DRAM */ 18 }; 19 20 gic: interrupt-controller@6000000 { 21 compatible = "arm,gic-v3"; 22 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 23 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ 24 #interrupt-cells = <3>; 25 interrupt-controller; 26 interrupts = <1 9 0x4>; 27 }; 28 29 timer { 30 compatible = "arm,armv8-timer"; 31 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ 32 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ 33 <1 11 0x8>, /* Virtual PPI, active-low */ 34 <1 10 0x8>; /* Hypervisor PPI, active-low */ 35 }; 36 37 i2c0: i2c@2000000 { 38 compatible = "fsl,vf610-i2c"; 39 #address-cells = <1>; 40 #size-cells = <0>; 41 reg = <0x0 0x2000000 0x0 0x10000>; 42 interrupts = <0 34 4>; 43 }; 44 45 i2c1: i2c@2010000 { 46 compatible = "fsl,vf610-i2c"; 47 #address-cells = <1>; 48 #size-cells = <0>; 49 reg = <0x0 0x2010000 0x0 0x10000>; 50 interrupts = <0 34 4>; 51 }; 52 53 i2c2: i2c@2020000 { 54 compatible = "fsl,vf610-i2c"; 55 #address-cells = <1>; 56 #size-cells = <0>; 57 reg = <0x0 0x2020000 0x0 0x10000>; 58 interrupts = <0 35 4>; 59 }; 60 61 i2c3: i2c@2030000 { 62 compatible = "fsl,vf610-i2c"; 63 #address-cells = <1>; 64 #size-cells = <0>; 65 reg = <0x0 0x2030000 0x0 0x10000>; 66 interrupts = <0 35 4>; 67 }; 68 69 serial0: serial@21c0500 { 70 device_type = "serial"; 71 compatible = "fsl,ns16550", "ns16550a"; 72 reg = <0x0 0x21c0500 0x0 0x100>; 73 clock-frequency = <0>; /* Updated by bootloader */ 74 interrupts = <0 32 0x1>; /* edge triggered */ 75 }; 76 77 serial1: serial@21c0600 { 78 device_type = "serial"; 79 compatible = "fsl,ns16550", "ns16550a"; 80 reg = <0x0 0x21c0600 0x0 0x100>; 81 clock-frequency = <0>; /* Updated by bootloader */ 82 interrupts = <0 32 0x1>; /* edge triggered */ 83 }; 84 85 fsl_mc: fsl-mc@80c000000 { 86 compatible = "fsl,qoriq-mc"; 87 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 88 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 89 }; 90 91 dspi: dspi@2100000 { 92 compatible = "fsl,vf610-dspi"; 93 #address-cells = <1>; 94 #size-cells = <0>; 95 reg = <0x0 0x2100000 0x0 0x10000>; 96 interrupts = <0 26 0x4>; /* Level high type */ 97 num-cs = <6>; 98 }; 99 100 qspi: quadspi@1550000 { 101 compatible = "fsl,vf610-qspi"; 102 #address-cells = <1>; 103 #size-cells = <0>; 104 reg = <0x0 0x20c0000 0x0 0x10000>, 105 <0x0 0x20000000 0x0 0x10000000>; 106 reg-names = "QuadSPI", "QuadSPI-memory"; 107 num-cs = <4>; 108 }; 109 110 esdhc: esdhc@2140000 { 111 compatible = "fsl,esdhc"; 112 reg = <0x0 0x2140000 0x0 0x10000>; 113 interrupts = <0 28 0x4>; /* Level high type */ 114 little-endian; 115 bus-width = <4>; 116 }; 117 118 ifc: ifc@1530000 { 119 compatible = "fsl,ifc", "simple-bus"; 120 reg = <0x0 0x2240000 0x0 0x20000>; 121 interrupts = <0 21 0x4>; /* Level high type */ 122 }; 123 124 usb0: usb3@3100000 { 125 compatible = "fsl,layerscape-dwc3"; 126 reg = <0x0 0x3100000 0x0 0x10000>; 127 interrupts = <0 80 0x4>; /* Level high type */ 128 dr_mode = "host"; 129 }; 130 131 usb1: usb3@3110000 { 132 compatible = "fsl,layerscape-dwc3"; 133 reg = <0x0 0x3110000 0x0 0x10000>; 134 interrupts = <0 81 0x4>; /* Level high type */ 135 dr_mode = "host"; 136 }; 137 138 pcie@3400000 { 139 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 140 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 141 0x00 0x03480000 0x0 0x80000 /* lut registers */ 142 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ 143 0x20 0x00000000 0x0 0x20000>; /* configuration space */ 144 reg-names = "dbi", "lut", "ctrl", "config"; 145 #address-cells = <3>; 146 #size-cells = <2>; 147 device_type = "pci"; 148 num-lanes = <4>; 149 bus-range = <0x0 0xff>; 150 ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */ 151 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 152 }; 153 154 pcie@3500000 { 155 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 156 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ 157 0x00 0x03580000 0x0 0x80000 /* lut registers */ 158 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ 159 0x28 0x00000000 0x0 0x20000>; /* configuration space */ 160 reg-names = "dbi", "lut", "ctrl", "config"; 161 #address-cells = <3>; 162 #size-cells = <2>; 163 device_type = "pci"; 164 num-lanes = <4>; 165 bus-range = <0x0 0xff>; 166 ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */ 167 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 168 }; 169 170 pcie@3600000 { 171 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 172 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ 173 0x00 0x03680000 0x0 0x80000 /* lut registers */ 174 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */ 175 0x30 0x00000000 0x0 0x20000>; /* configuration space */ 176 reg-names = "dbi", "lut", "ctrl", "config"; 177 #address-cells = <3>; 178 #size-cells = <2>; 179 device_type = "pci"; 180 num-lanes = <8>; 181 bus-range = <0x0 0xff>; 182 ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */ 183 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 184 }; 185 186 sata: sata@3200000 { 187 compatible = "fsl,ls1088a-ahci"; 188 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ 189 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ 190 reg-names = "sata-base", "ecc-addr"; 191 interrupts = <0 133 4>; 192 status = "disabled"; 193 }; 194 195 psci { 196 compatible = "arm,psci-0.2"; 197 method = "smc"; 198 }; 199 200}; 201