1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright (C) 2015 Freescale Semiconductor, Inc. 4 5/ { 6 aliases { 7 spi5 = &{/spi4}; 8 }; 9 10 chosen { 11 stdout-path = &uart1; 12 }; 13 14 memory@80000000 { 15 device_type = "memory"; 16 reg = <0x80000000 0x20000000>; 17 }; 18 19 backlight_display: backlight-display { 20 compatible = "pwm-backlight"; 21 pwms = <&pwm1 0 5000000>; 22 brightness-levels = <0 4 8 16 32 64 128 255>; 23 default-brightness-level = <6>; 24 status = "okay"; 25 }; 26 27 28 reg_sd1_vmmc: regulator-sd1-vmmc { 29 compatible = "regulator-fixed"; 30 regulator-name = "VSD_3V3"; 31 regulator-min-microvolt = <3300000>; 32 regulator-max-microvolt = <3300000>; 33 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 34 enable-active-high; 35 }; 36 37 reg_can_3v3: regulator-can-3v3 { 38 compatible = "regulator-fixed"; 39 regulator-name = "can-3v3"; 40 regulator-min-microvolt = <3300000>; 41 regulator-max-microvolt = <3300000>; 42 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; 43 }; 44 45 spi4 { 46 compatible = "spi-gpio"; 47 pinctrl-names = "default"; 48 pinctrl-0 = <&pinctrl_spi4>; 49 status = "okay"; 50 gpio-sck = <&gpio5 11 0>; 51 gpio-mosi = <&gpio5 10 0>; 52 cs-gpios = <&gpio5 7 0>; 53 num-chipselects = <1>; 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 gpio_spi: gpio@0 { 58 compatible = "fairchild,74hc595"; 59 gpio-controller; 60 #gpio-cells = <2>; 61 reg = <0>; 62 registers-number = <1>; 63 spi-max-frequency = <100000>; 64 }; 65 }; 66 67 panel { 68 compatible = "innolux,at043tn24"; 69 backlight = <&backlight_display>; 70 71 port { 72 panel_in: endpoint { 73 remote-endpoint = <&display_out>; 74 }; 75 }; 76 }; 77}; 78 79&clks { 80 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 81 assigned-clock-rates = <786432000>; 82}; 83 84&i2c2 { 85 clock_frequency = <100000>; 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_i2c2>; 88 status = "okay"; 89 90 codec: wm8960@1a { 91 #sound-dai-cells = <0>; 92 compatible = "wlf,wm8960"; 93 reg = <0x1a>; 94 wlf,shared-lrclk; 95 }; 96}; 97 98&fec1 { 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_enet1>; 101 phy-mode = "rmii"; 102 phy-handle = <ðphy0>; 103 status = "okay"; 104}; 105 106&fec2 { 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_enet2>; 109 phy-mode = "rmii"; 110 phy-handle = <ðphy1>; 111 status = "okay"; 112 113 mdio { 114 #address-cells = <1>; 115 #size-cells = <0>; 116 117 ethphy0: ethernet-phy@2 { 118 reg = <2>; 119 micrel,led-mode = <1>; 120 clocks = <&clks IMX6UL_CLK_ENET_REF>; 121 clock-names = "rmii-ref"; 122 }; 123 124 ethphy1: ethernet-phy@1 { 125 reg = <1>; 126 micrel,led-mode = <1>; 127 clocks = <&clks IMX6UL_CLK_ENET2_REF>; 128 clock-names = "rmii-ref"; 129 }; 130 }; 131}; 132 133&can1 { 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_flexcan1>; 136 xceiver-supply = <®_can_3v3>; 137 status = "okay"; 138}; 139 140&can2 { 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_flexcan2>; 143 xceiver-supply = <®_can_3v3>; 144 status = "okay"; 145}; 146 147&i2c1 { 148 clock-frequency = <100000>; 149 pinctrl-names = "default", "gpio"; 150 pinctrl-0 = <&pinctrl_i2c1>; 151 pinctrl-1 = <&pinctrl_i2c1_gpio>; 152 scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 153 sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; 154 status = "okay"; 155 156 mag3110@e { 157 compatible = "fsl,mag3110"; 158 reg = <0x0e>; 159 }; 160}; 161 162&lcdif { 163 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; 164 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_lcdif_dat 167 &pinctrl_lcdif_ctrl>; 168 status = "okay"; 169 170 port { 171 display_out: endpoint { 172 remote-endpoint = <&panel_in>; 173 }; 174 }; 175}; 176 177&pwm1 { 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_pwm1>; 180 status = "okay"; 181}; 182 183&qspi { 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_qspi>; 186 status = "okay"; 187 188 flash0: n25q256a@0 { 189 #address-cells = <1>; 190 #size-cells = <1>; 191 compatible = "micron,n25q256a"; 192 spi-max-frequency = <29000000>; 193 spi-rx-bus-width = <4>; 194 spi-tx-bus-width = <4>; 195 reg = <0>; 196 }; 197}; 198 199&sai2 { 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_sai2>; 202 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 203 <&clks IMX6UL_CLK_SAI2>; 204 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 205 assigned-clock-rates = <0>, <12288000>; 206 fsl,sai-mclk-direction-output; 207 status = "okay"; 208}; 209 210&snvs_poweroff { 211 status = "okay"; 212}; 213 214&tsc { 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_tsc>; 217 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 218 measure-delay-time = <0xffff>; 219 pre-charge-time = <0xfff>; 220 status = "okay"; 221}; 222 223&uart1 { 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_uart1>; 226 status = "okay"; 227}; 228 229&uart2 { 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_uart2>; 232 uart-has-rtscts; 233 status = "okay"; 234}; 235 236&usbotg1 { 237 dr_mode = "otg"; 238 status = "okay"; 239}; 240 241&usbotg2 { 242 dr_mode = "host"; 243 disable-over-current; 244 status = "okay"; 245}; 246 247&usbphy1 { 248 fsl,tx-d-cal = <106>; 249}; 250 251&usbphy2 { 252 fsl,tx-d-cal = <106>; 253}; 254 255&usdhc1 { 256 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 257 pinctrl-0 = <&pinctrl_usdhc1>; 258 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 259 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 260 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 261 keep-power-in-suspend; 262 wakeup-source; 263 vmmc-supply = <®_sd1_vmmc>; 264 status = "okay"; 265}; 266 267&usdhc2 { 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_usdhc2>; 270 no-1-8-v; 271 keep-power-in-suspend; 272 wakeup-source; 273 status = "okay"; 274}; 275 276&wdog1 { 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pinctrl_wdog>; 279 fsl,ext-reset-output; 280}; 281 282&iomuxc { 283 pinctrl-names = "default"; 284 285 pinctrl_csi1: csi1grp { 286 fsl,pins = < 287 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 288 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 289 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 290 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 291 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 292 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 293 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 294 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 295 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 296 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 297 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 298 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 299 >; 300 }; 301 302 pinctrl_enet1: enet1grp { 303 fsl,pins = < 304 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 305 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 306 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 307 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 308 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 309 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 310 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 311 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 312 >; 313 }; 314 315 pinctrl_enet2: enet2grp { 316 fsl,pins = < 317 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 318 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 319 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 320 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 321 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 322 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 323 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 324 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 325 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 326 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 327 >; 328 }; 329 330 pinctrl_flexcan1: flexcan1grp{ 331 fsl,pins = < 332 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 333 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 334 >; 335 }; 336 337 pinctrl_flexcan2: flexcan2grp{ 338 fsl,pins = < 339 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 340 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 341 >; 342 }; 343 344 pinctrl_i2c1: i2c1grp { 345 fsl,pins = < 346 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 347 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 348 >; 349 }; 350 351 pinctrl_i2c1_gpio: i2c1grp_gpio { 352 fsl,pins = < 353 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 354 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 355 >; 356 }; 357 358 pinctrl_i2c2: i2c2grp { 359 fsl,pins = < 360 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 361 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 362 >; 363 }; 364 365 pinctrl_lcdif_dat: lcdifdatgrp { 366 fsl,pins = < 367 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 368 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 369 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 370 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 371 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 372 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 373 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 374 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 375 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 376 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 377 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 378 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 379 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 380 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 381 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 382 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 383 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 384 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 385 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 386 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 387 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 388 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 389 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 390 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 391 >; 392 }; 393 394 pinctrl_lcdif_ctrl: lcdifctrlgrp { 395 fsl,pins = < 396 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 397 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 398 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 399 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 400 /* used for lcd reset */ 401 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 402 >; 403 }; 404 405 pinctrl_qspi: qspigrp { 406 fsl,pins = < 407 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 408 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 409 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 410 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 411 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 412 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 413 >; 414 }; 415 416 pinctrl_sai2: sai2grp { 417 fsl,pins = < 418 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 419 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 420 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 421 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 422 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 423 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 424 >; 425 }; 426 427 pinctrl_pwm1: pwm1grp { 428 fsl,pins = < 429 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 430 >; 431 }; 432 433 pinctrl_sim2: sim2grp { 434 fsl,pins = < 435 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 436 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 437 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 438 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 439 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 440 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 441 >; 442 }; 443 444 pinctrl_spi4: spi4grp { 445 fsl,pins = < 446 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 447 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 448 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 449 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 450 >; 451 }; 452 453 pinctrl_tsc: tscgrp { 454 fsl,pins = < 455 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 456 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 457 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 458 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 459 >; 460 }; 461 462 pinctrl_uart1: uart1grp { 463 fsl,pins = < 464 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 465 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 466 >; 467 }; 468 469 pinctrl_uart2: uart2grp { 470 fsl,pins = < 471 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 472 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 473 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 474 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 475 >; 476 }; 477 478 pinctrl_usdhc1: usdhc1grp { 479 fsl,pins = < 480 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 481 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 482 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 483 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 484 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 485 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 486 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 487 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 488 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 489 >; 490 }; 491 492 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 493 fsl,pins = < 494 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 495 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 496 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 497 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 498 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 499 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 500 501 >; 502 }; 503 504 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 505 fsl,pins = < 506 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 507 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 508 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 509 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 510 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 511 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 512 >; 513 }; 514 515 pinctrl_usdhc2: usdhc2grp { 516 fsl,pins = < 517 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 518 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 519 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 520 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 521 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 522 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 523 >; 524 }; 525 526 pinctrl_wdog: wdoggrp { 527 fsl,pins = < 528 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 529 >; 530 }; 531}; 532