1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-am654-serdes.h> 9#include <dt-bindings/phy/phy.h> 10 11&cbass_main { 12 gic500: interrupt-controller@1800000 { 13 compatible = "arm,gic-v3"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 ranges; 17 #interrupt-cells = <3>; 18 interrupt-controller; 19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 20 <0x00 0x01880000 0x00 0x90000>; /* GICR */ 21 /* 22 * vcpumntirq: 23 * virtual CPU interface maintenance interrupt 24 */ 25 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 26 27 gic_its: gic-its@18200000 { 28 compatible = "arm,gic-v3-its"; 29 reg = <0x00 0x01820000 0x00 0x10000>; 30 msi-controller; 31 #msi-cells = <1>; 32 }; 33 }; 34 35 secure_proxy_main: mailbox@32c00000 { 36 compatible = "ti,am654-secure-proxy"; 37 #mbox-cells = <1>; 38 reg-names = "target_data", "rt", "scfg"; 39 reg = <0x00 0x32c00000 0x00 0x100000>, 40 <0x00 0x32400000 0x00 0x100000>, 41 <0x00 0x32800000 0x00 0x100000>; 42 interrupt-names = "rx_011"; 43 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 44 }; 45 46 main_uart0: serial@2800000 { 47 compatible = "ti,am654-uart"; 48 reg = <0x00 0x02800000 0x00 0x100>; 49 reg-shift = <2>; 50 reg-io-width = <4>; 51 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 52 clock-frequency = <48000000>; 53 current-speed = <115200>; 54 }; 55 56 main_uart1: serial@2810000 { 57 compatible = "ti,am654-uart"; 58 reg = <0x00 0x02810000 0x00 0x100>; 59 reg-shift = <2>; 60 reg-io-width = <4>; 61 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 62 clock-frequency = <48000000>; 63 current-speed = <115200>; 64 }; 65 66 main_uart2: serial@2820000 { 67 compatible = "ti,am654-uart"; 68 reg = <0x00 0x02820000 0x00 0x100>; 69 reg-shift = <2>; 70 reg-io-width = <4>; 71 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 72 clock-frequency = <48000000>; 73 current-speed = <115200>; 74 }; 75 76 main_pmx0: pinmux@11c000 { 77 compatible = "pinctrl-single"; 78 reg = <0x0 0x11c000 0x0 0x2e4>; 79 #pinctrl-cells = <1>; 80 pinctrl-single,register-width = <32>; 81 pinctrl-single,function-mask = <0xffffffff>; 82 }; 83 84 main_pmx1: pinmux@11c2e8 { 85 compatible = "pinctrl-single"; 86 reg = <0x0 0x11c2e8 0x0 0x24>; 87 #pinctrl-cells = <1>; 88 pinctrl-single,register-width = <32>; 89 pinctrl-single,function-mask = <0xffffffff>; 90 }; 91 92 sdhci0: sdhci@4f80000 { 93 compatible = "ti,am654-sdhci-5.1"; 94 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 95 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 96 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 97 clock-names = "clk_ahb", "clk_xin"; 98 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 99 mmc-ddr-1_8v; 100 mmc-hs200-1_8v; 101 ti,otap-del-sel = <0x2>; 102 ti,trm-icp = <0x8>; 103 dma-coherent; 104 }; 105 106 main_i2c0: i2c@2000000 { 107 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 108 reg = <0x0 0x2000000 0x0 0x100>; 109 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 110 #address-cells = <1>; 111 #size-cells = <0>; 112 clock-names = "fck"; 113 clocks = <&k3_clks 110 1>; 114 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 115 }; 116 117 main_i2c1: i2c@2010000 { 118 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 119 reg = <0x0 0x2010000 0x0 0x100>; 120 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 clock-names = "fck"; 124 clocks = <&k3_clks 111 1>; 125 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 126 }; 127 128 main_i2c2: i2c@2020000 { 129 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 130 reg = <0x0 0x2020000 0x0 0x100>; 131 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 clock-names = "fck"; 135 clocks = <&k3_clks 112 1>; 136 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 137 }; 138 139 main_i2c3: i2c@2030000 { 140 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 141 reg = <0x0 0x2030000 0x0 0x100>; 142 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 clock-names = "fck"; 146 clocks = <&k3_clks 113 1>; 147 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 148 }; 149 150 scm_conf: scm_conf@100000 { 151 compatible = "syscon", "simple-mfd"; 152 reg = <0 0x00100000 0 0x1c000>; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 ranges = <0x0 0x0 0x00100000 0x1c000>; 156 157 serdes_mux: mux-controller { 158 compatible = "mmio-mux"; 159 #mux-control-cells = <1>; 160 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ 161 <0x4090 0x3>; /* SERDES1 lane select */ 162 }; 163 164 pcie0_mode: pcie-mode@4060 { 165 compatible = "syscon"; 166 reg = <0x00004060 0x4>; 167 }; 168 169 pcie1_mode: pcie-mode@4070 { 170 compatible = "syscon"; 171 reg = <0x00004070 0x4>; 172 }; 173 174 serdes0_clk: serdes_clk@4080 { 175 compatible = "syscon"; 176 reg = <0x00004080 0x4>; 177 }; 178 179 serdes1_clk: serdes_clk@4090 { 180 compatible = "syscon"; 181 reg = <0x00004090 0x4>; 182 }; 183 184 pcie_devid: pcie-devid@210 { 185 compatible = "syscon"; 186 reg = <0x00000210 0x4>; 187 }; 188 }; 189 190 serdes0: serdes@900000 { 191 compatible = "ti,phy-am654-serdes"; 192 reg = <0x0 0x900000 0x0 0x2000>; 193 reg-names = "serdes"; 194 #phy-cells = <2>; 195 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 196 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 197 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 198 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 199 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 200 ti,serdes-clk = <&serdes0_clk>; 201 mux-controls = <&serdes_mux 0>; 202 #clock-cells = <1>; 203 }; 204 205 serdes1: serdes@910000 { 206 compatible = "ti,phy-am654-serdes"; 207 reg = <0x0 0x910000 0x0 0x2000>; 208 reg-names = "serdes"; 209 #phy-cells = <2>; 210 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 211 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 212 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 213 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 214 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 215 ti,serdes-clk = <&serdes1_clk>; 216 mux-controls = <&serdes_mux 1>; 217 #clock-cells = <1>; 218 }; 219 220 pcie0_rc: pcie@5500000 { 221 compatible = "ti,am654-pcie-rc"; 222 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 223 reg-names = "app", "dbics", "config", "atu"; 224 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 225 #address-cells = <3>; 226 #size-cells = <2>; 227 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 228 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 229 ti,syscon-pcie-id = <&pcie_devid>; 230 ti,syscon-pcie-mode = <&pcie0_mode>; 231 bus-range = <0x0 0xff>; 232 status = "disabled"; 233 device_type = "pci"; 234 num-lanes = <1>; 235 num-ob-windows = <16>; 236 num-viewport = <16>; 237 max-link-speed = <3>; 238 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 239 #interrupt-cells = <1>; 240 interrupt-map-mask = <0 0 0 7>; 241 interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */ 242 <0 0 0 2 &pcie0_intc 0>, /* INT B */ 243 <0 0 0 3 &pcie0_intc 0>, /* INT C */ 244 <0 0 0 4 &pcie0_intc 0>; /* INT D */ 245 msi-map = <0x0 &gic_its 0x0 0x10000>; 246 247 pcie0_intc: legacy-interrupt-controller@1 { 248 interrupt-controller; 249 #interrupt-cells = <1>; 250 interrupt-parent = <&gic500>; 251 interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>; 252 }; 253 }; 254}; 255