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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6/ {
7	aliases {
8		mmc0 = &emmc;
9		mmc1 = &sdmmc;
10	};
11
12	chosen {
13		u-boot,spl-boot-order = &emmc, &sdmmc;
14	};
15};
16
17&dmc {
18	u-boot,dm-pre-reloc;
19};
20
21&uart2 {
22	clock-frequency = <24000000>;
23	u-boot,dm-pre-reloc;
24};
25
26&uart5 {
27	clock-frequency = <24000000>;
28	u-boot,dm-pre-reloc;
29};
30
31&sdmmc {
32	u-boot,dm-pre-reloc;
33
34	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
35	u-boot,spl-fifo-mode;
36};
37
38&emmc {
39	u-boot,dm-pre-reloc;
40
41	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
42	u-boot,spl-fifo-mode;
43};
44
45&grf {
46	u-boot,dm-pre-reloc;
47};
48
49&pmugrf {
50	u-boot,dm-pre-reloc;
51};
52
53&xin24m {
54	u-boot,dm-pre-reloc;
55};
56
57&cru {
58	u-boot,dm-pre-reloc;
59};
60
61&pmucru {
62	u-boot,dm-pre-reloc;
63};
64
65&saradc {
66	u-boot,dm-pre-reloc;
67	status = "okay";
68};
69
70&gpio0 {
71	u-boot,dm-pre-reloc;
72};
73
74&gpio1 {
75	u-boot,dm-pre-reloc;
76};
77
78&gpio2 {
79	u-boot,dm-pre-reloc;
80};
81
82&gpio3 {
83	u-boot,dm-pre-reloc;
84};
85