1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2018 Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 compatible = "altr,socfpga-stratix10"; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a53", "arm,armv8"; 21 device_type = "cpu"; 22 enable-method = "psci"; 23 reg = <0x0>; 24 }; 25 26 cpu1: cpu@1 { 27 compatible = "arm,cortex-a53", "arm,armv8"; 28 device_type = "cpu"; 29 enable-method = "psci"; 30 reg = <0x1>; 31 }; 32 33 cpu2: cpu@2 { 34 compatible = "arm,cortex-a53", "arm,armv8"; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 reg = <0x2>; 38 }; 39 40 cpu3: cpu@3 { 41 compatible = "arm,cortex-a53", "arm,armv8"; 42 device_type = "cpu"; 43 enable-method = "psci"; 44 reg = <0x3>; 45 }; 46 }; 47 48 pmu { 49 compatible = "arm,armv8-pmuv3"; 50 interrupts = <0 120 8>, 51 <0 121 8>, 52 <0 122 8>, 53 <0 123 8>; 54 interrupt-affinity = <&cpu0>, 55 <&cpu1>, 56 <&cpu2>, 57 <&cpu3>; 58 interrupt-parent = <&intc>; 59 }; 60 61 psci { 62 compatible = "arm,psci-0.2"; 63 method = "smc"; 64 }; 65 66 intc: intc@fffc1000 { 67 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 68 #interrupt-cells = <3>; 69 interrupt-controller; 70 reg = <0x0 0xfffc1000 0x0 0x1000>, 71 <0x0 0xfffc2000 0x0 0x2000>, 72 <0x0 0xfffc4000 0x0 0x2000>, 73 <0x0 0xfffc6000 0x0 0x2000>; 74 }; 75 76 soc { 77 #address-cells = <1>; 78 #size-cells = <1>; 79 compatible = "simple-bus"; 80 device_type = "soc"; 81 interrupt-parent = <&intc>; 82 ranges = <0 0 0 0xffffffff>; 83 u-boot,dm-pre-reloc; 84 85 clkmgr@ffd1000 { 86 compatible = "altr,clk-mgr"; 87 reg = <0xffd10000 0x1000>; 88 }; 89 90 gmac0: ethernet@ff800000 { 91 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 92 reg = <0xff800000 0x2000>; 93 interrupts = <0 90 4>; 94 interrupt-names = "macirq"; 95 mac-address = [00 00 00 00 00 00]; 96 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 97 reset-names = "stmmaceth"; 98 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 99 status = "disabled"; 100 }; 101 102 gmac1: ethernet@ff802000 { 103 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 104 reg = <0xff802000 0x2000>; 105 interrupts = <0 91 4>; 106 interrupt-names = "macirq"; 107 mac-address = [00 00 00 00 00 00]; 108 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 109 reset-names = "stmmaceth"; 110 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 111 status = "disabled"; 112 }; 113 114 gmac2: ethernet@ff804000 { 115 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 116 reg = <0xff804000 0x2000>; 117 interrupts = <0 92 4>; 118 interrupt-names = "macirq"; 119 mac-address = [00 00 00 00 00 00]; 120 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 121 reset-names = "stmmaceth"; 122 altr,sysmgr-syscon = <&sysmgr 0x4c 0>; 123 status = "disabled"; 124 }; 125 126 gpio0: gpio@ffc03200 { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 compatible = "snps,dw-apb-gpio"; 130 reg = <0xffc03200 0x100>; 131 resets = <&rst GPIO0_RESET>; 132 status = "disabled"; 133 134 porta: gpio-controller@0 { 135 compatible = "snps,dw-apb-gpio-port"; 136 gpio-controller; 137 #gpio-cells = <2>; 138 snps,nr-gpios = <24>; 139 reg = <0>; 140 interrupt-controller; 141 #interrupt-cells = <2>; 142 interrupts = <0 110 4>; 143 bank-name = "porta"; 144 }; 145 }; 146 147 gpio1: gpio@ffc03300 { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 compatible = "snps,dw-apb-gpio"; 151 reg = <0xffc03300 0x100>; 152 resets = <&rst GPIO1_RESET>; 153 status = "disabled"; 154 155 portb: gpio-controller@0 { 156 compatible = "snps,dw-apb-gpio-port"; 157 gpio-controller; 158 #gpio-cells = <2>; 159 snps,nr-gpios = <24>; 160 reg = <0>; 161 interrupt-controller; 162 #interrupt-cells = <2>; 163 interrupts = <0 111 4>; 164 bank-name = "portb"; 165 }; 166 }; 167 168 i2c0: i2c@ffc02800 { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 compatible = "snps,designware-i2c"; 172 reg = <0xffc02800 0x100>; 173 interrupts = <0 103 4>; 174 resets = <&rst I2C0_RESET>; 175 reset-names = "i2c"; 176 status = "disabled"; 177 }; 178 179 i2c1: i2c@ffc02900 { 180 #address-cells = <1>; 181 #size-cells = <0>; 182 compatible = "snps,designware-i2c"; 183 reg = <0xffc02900 0x100>; 184 interrupts = <0 104 4>; 185 resets = <&rst I2C1_RESET>; 186 reset-names = "i2c"; 187 status = "disabled"; 188 }; 189 190 i2c2: i2c@ffc02a00 { 191 #address-cells = <1>; 192 #size-cells = <0>; 193 compatible = "snps,designware-i2c"; 194 reg = <0xffc02a00 0x100>; 195 interrupts = <0 105 4>; 196 resets = <&rst I2C2_RESET>; 197 reset-names = "i2c"; 198 status = "disabled"; 199 }; 200 201 i2c3: i2c@ffc02b00 { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 compatible = "snps,designware-i2c"; 205 reg = <0xffc02b00 0x100>; 206 interrupts = <0 106 4>; 207 resets = <&rst I2C3_RESET>; 208 reset-names = "i2c"; 209 status = "disabled"; 210 }; 211 212 i2c4: i2c@ffc02c00 { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 compatible = "snps,designware-i2c"; 216 reg = <0xffc02c00 0x100>; 217 interrupts = <0 107 4>; 218 resets = <&rst I2C4_RESET>; 219 reset-names = "i2c"; 220 status = "disabled"; 221 }; 222 223 mmc: dwmmc0@ff808000 { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 compatible = "altr,socfpga-dw-mshc"; 227 reg = <0xff808000 0x1000>; 228 interrupts = <0 96 4>; 229 fifo-depth = <0x400>; 230 resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; 231 u-boot,dm-pre-reloc; 232 status = "disabled"; 233 }; 234 235 ocram: sram@ffe00000 { 236 compatible = "mmio-sram"; 237 reg = <0xffe00000 0x100000>; 238 }; 239 240 qspi: spi@ff8d2000 { 241 compatible = "cdns,qspi-nor"; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 reg = <0xff8d2000 0x100>, 245 <0xff900000 0x100000>; 246 interrupts = <0 3 4>; 247 cdns,fifo-depth = <128>; 248 cdns,fifo-width = <4>; 249 cdns,trigger-address = <0x00000000>; 250 status = "disabled"; 251 }; 252 253 rst: rstmgr@ffd11000 { 254 #reset-cells = <1>; 255 compatible = "altr,rst-mgr"; 256 reg = <0xffd11000 0x1000>; 257 altr,modrst-offset = <0x20>; 258 u-boot,dm-pre-reloc; 259 }; 260 261 sdr: sdr@f8000400 { 262 compatible = "altr,sdr-ctl-s10"; 263 reg = <0xf8000400 0x80>, 264 <0xf8010000 0x190>, 265 <0xf8011000 0x500>; 266 resets = <&rst DDRSCH_RESET>; 267 u-boot,dm-pre-reloc; 268 }; 269 270 spi0: spi@ffda4000 { 271 compatible = "snps,dw-apb-ssi"; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 reg = <0xffda4000 0x1000>; 275 interrupts = <0 99 4>; 276 resets = <&rst SPIM0_RESET>; 277 reg-io-width = <4>; 278 num-chipselect = <4>; 279 bus-num = <0>; 280 status = "disabled"; 281 }; 282 283 spi1: spi@ffda5000 { 284 compatible = "snps,dw-apb-ssi"; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 reg = <0xffda5000 0x1000>; 288 interrupts = <0 100 4>; 289 resets = <&rst SPIM1_RESET>; 290 reg-io-width = <4>; 291 num-chipselect = <4>; 292 bus-num = <0>; 293 status = "disabled"; 294 }; 295 296 sysmgr: sysmgr@ffd12000 { 297 compatible = "altr,sys-mgr", "syscon"; 298 reg = <0xffd12000 0x1000>; 299 }; 300 301 /* Local timer */ 302 timer { 303 compatible = "arm,armv8-timer"; 304 interrupts = <1 13 0xf08>, 305 <1 14 0xf08>, 306 <1 11 0xf08>, 307 <1 10 0xf08>; 308 }; 309 310 timer0: timer0@ffc03000 { 311 compatible = "snps,dw-apb-timer"; 312 interrupts = <0 113 4>; 313 reg = <0xffc03000 0x100>; 314 }; 315 316 timer1: timer1@ffc03100 { 317 compatible = "snps,dw-apb-timer"; 318 interrupts = <0 114 4>; 319 reg = <0xffc03100 0x100>; 320 }; 321 322 timer2: timer2@ffd00000 { 323 compatible = "snps,dw-apb-timer"; 324 interrupts = <0 115 4>; 325 reg = <0xffd00000 0x100>; 326 }; 327 328 timer3: timer3@ffd00100 { 329 compatible = "snps,dw-apb-timer"; 330 interrupts = <0 116 4>; 331 reg = <0xffd00100 0x100>; 332 }; 333 334 uart0: serial0@ffc02000 { 335 compatible = "snps,dw-apb-uart"; 336 reg = <0xffc02000 0x100>; 337 interrupts = <0 108 4>; 338 reg-shift = <2>; 339 reg-io-width = <4>; 340 resets = <&rst UART0_RESET>; 341 clock-frequency = <100000000>; 342 u-boot,dm-pre-reloc; 343 status = "disabled"; 344 }; 345 346 uart1: serial1@ffc02100 { 347 compatible = "snps,dw-apb-uart"; 348 reg = <0xffc02100 0x100>; 349 interrupts = <0 109 4>; 350 reg-shift = <2>; 351 reg-io-width = <4>; 352 resets = <&rst UART1_RESET>; 353 status = "disabled"; 354 }; 355 356 usbphy0: usbphy@0 { 357 #phy-cells = <0>; 358 compatible = "usb-nop-xceiv"; 359 status = "okay"; 360 }; 361 362 usb0: usb@ffb00000 { 363 compatible = "snps,dwc2"; 364 reg = <0xffb00000 0x40000>; 365 interrupts = <0 93 4>; 366 phys = <&usbphy0>; 367 phy-names = "usb2-phy"; 368 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 369 reset-names = "dwc2", "dwc2-ecc"; 370 status = "disabled"; 371 }; 372 373 usb1: usb@ffb40000 { 374 compatible = "snps,dwc2"; 375 reg = <0xffb40000 0x40000>; 376 interrupts = <0 94 4>; 377 phys = <&usbphy0>; 378 phy-names = "usb2-phy"; 379 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 380 reset-names = "dwc2", "dwc2-ecc"; 381 status = "disabled"; 382 }; 383 384 watchdog0: watchdog@ffd00200 { 385 compatible = "snps,dw-wdt"; 386 reg = <0xffd00200 0x100>; 387 interrupts = <0 117 4>; 388 resets = <&rst WATCHDOG0_RESET>; 389 u-boot,dm-pre-reloc; 390 status = "disabled"; 391 }; 392 393 watchdog1: watchdog@ffd00300 { 394 compatible = "snps,dw-wdt"; 395 reg = <0xffd00300 0x100>; 396 interrupts = <0 118 4>; 397 resets = <&rst WATCHDOG1_RESET>; 398 status = "disabled"; 399 }; 400 401 watchdog2: watchdog@ffd00400 { 402 compatible = "snps,dw-wdt"; 403 reg = <0xffd00400 0x100>; 404 interrupts = <0 125 4>; 405 resets = <&rst WATCHDOG2_RESET>; 406 status = "disabled"; 407 }; 408 409 watchdog3: watchdog@ffd00500 { 410 compatible = "snps,dw-wdt"; 411 reg = <0xffd00500 0x100>; 412 interrupts = <0 126 4>; 413 resets = <&rst WATCHDOG3_RESET>; 414 status = "disabled"; 415 }; 416 }; 417}; 418