1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> 4 * 5 */ 6 7#include <dt-bindings/pinctrl/stm32-pinfunc.h> 8#include <dt-bindings/mfd/stm32f4-rcc.h> 9 10/ { 11 soc { 12 pinctrl: pin-controller { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0 0x40020000 0x3000>; 16 interrupt-parent = <&exti>; 17 st,syscfg = <&syscfg 0x8>; 18 pins-are-numbered; 19 20 gpioa: gpio@40020000 { 21 gpio-controller; 22 #gpio-cells = <2>; 23 interrupt-controller; 24 #interrupt-cells = <2>; 25 reg = <0x0 0x400>; 26 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; 27 st,bank-name = "GPIOA"; 28 }; 29 30 gpiob: gpio@40020400 { 31 gpio-controller; 32 #gpio-cells = <2>; 33 interrupt-controller; 34 #interrupt-cells = <2>; 35 reg = <0x400 0x400>; 36 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; 37 st,bank-name = "GPIOB"; 38 }; 39 40 gpioc: gpio@40020800 { 41 gpio-controller; 42 #gpio-cells = <2>; 43 interrupt-controller; 44 #interrupt-cells = <2>; 45 reg = <0x800 0x400>; 46 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; 47 st,bank-name = "GPIOC"; 48 }; 49 50 gpiod: gpio@40020c00 { 51 gpio-controller; 52 #gpio-cells = <2>; 53 interrupt-controller; 54 #interrupt-cells = <2>; 55 reg = <0xc00 0x400>; 56 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>; 57 st,bank-name = "GPIOD"; 58 }; 59 60 gpioe: gpio@40021000 { 61 gpio-controller; 62 #gpio-cells = <2>; 63 interrupt-controller; 64 #interrupt-cells = <2>; 65 reg = <0x1000 0x400>; 66 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>; 67 st,bank-name = "GPIOE"; 68 }; 69 70 gpiof: gpio@40021400 { 71 gpio-controller; 72 #gpio-cells = <2>; 73 interrupt-controller; 74 #interrupt-cells = <2>; 75 reg = <0x1400 0x400>; 76 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>; 77 st,bank-name = "GPIOF"; 78 }; 79 80 gpiog: gpio@40021800 { 81 gpio-controller; 82 #gpio-cells = <2>; 83 interrupt-controller; 84 #interrupt-cells = <2>; 85 reg = <0x1800 0x400>; 86 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>; 87 st,bank-name = "GPIOG"; 88 }; 89 90 gpioh: gpio@40021c00 { 91 gpio-controller; 92 #gpio-cells = <2>; 93 interrupt-controller; 94 #interrupt-cells = <2>; 95 reg = <0x1c00 0x400>; 96 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>; 97 st,bank-name = "GPIOH"; 98 }; 99 100 gpioi: gpio@40022000 { 101 gpio-controller; 102 #gpio-cells = <2>; 103 interrupt-controller; 104 #interrupt-cells = <2>; 105 reg = <0x2000 0x400>; 106 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>; 107 st,bank-name = "GPIOI"; 108 }; 109 110 gpioj: gpio@40022400 { 111 gpio-controller; 112 #gpio-cells = <2>; 113 interrupt-controller; 114 #interrupt-cells = <2>; 115 reg = <0x2400 0x400>; 116 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>; 117 st,bank-name = "GPIOJ"; 118 }; 119 120 gpiok: gpio@40022800 { 121 gpio-controller; 122 #gpio-cells = <2>; 123 interrupt-controller; 124 #interrupt-cells = <2>; 125 reg = <0x2800 0x400>; 126 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>; 127 st,bank-name = "GPIOK"; 128 }; 129 130 usart1_pins_a: usart1@0 { 131 pins1 { 132 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ 133 bias-disable; 134 drive-push-pull; 135 slew-rate = <0>; 136 }; 137 pins2 { 138 pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */ 139 bias-disable; 140 }; 141 }; 142 143 usart3_pins_a: usart3@0 { 144 pins1 { 145 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ 146 bias-disable; 147 drive-push-pull; 148 slew-rate = <0>; 149 }; 150 pins2 { 151 pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */ 152 bias-disable; 153 }; 154 }; 155 156 usbotg_fs_pins_a: usbotg_fs@0 { 157 pins { 158 pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */ 159 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */ 160 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */ 161 bias-disable; 162 drive-push-pull; 163 slew-rate = <2>; 164 }; 165 }; 166 167 usbotg_fs_pins_b: usbotg_fs@1 { 168 pins { 169 pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */ 170 <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */ 171 <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */ 172 bias-disable; 173 drive-push-pull; 174 slew-rate = <2>; 175 }; 176 }; 177 178 usbotg_hs_pins_a: usbotg_hs@0 { 179 pins { 180 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/ 181 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */ 182 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */ 183 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */ 184 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */ 185 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */ 186 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */ 187 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */ 188 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */ 189 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */ 190 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */ 191 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */ 192 bias-disable; 193 drive-push-pull; 194 slew-rate = <2>; 195 }; 196 }; 197 198 ethernet_mii: mii@0 { 199 pins { 200 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */ 201 <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */ 202 <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */ 203 <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */ 204 <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */ 205 <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */ 206 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ 207 <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */ 208 <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */ 209 <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */ 210 <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */ 211 <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */ 212 <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */ 213 <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */ 214 slew-rate = <2>; 215 }; 216 }; 217 218 adc3_in8_pin: adc@200 { 219 pins { 220 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; 221 }; 222 }; 223 224 pwm1_pins: pwm@1 { 225 pins { 226 pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */ 227 <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */ 228 <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */ 229 }; 230 }; 231 232 pwm3_pins: pwm@3 { 233 pins { 234 pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */ 235 <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ 236 }; 237 }; 238 239 i2c1_pins: i2c1@0 { 240 pins { 241 pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */ 242 <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */ 243 bias-disable; 244 drive-open-drain; 245 slew-rate = <3>; 246 }; 247 }; 248 249 ltdc_pins: ltdc@0 { 250 pins { 251 pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ 252 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ 253 <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ 254 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ 255 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ 256 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ 257 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ 258 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ 259 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ 260 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/ 261 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ 262 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ 263 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ 264 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ 265 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ 266 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ 267 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ 268 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ 269 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ 270 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/ 271 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ 272 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ 273 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ 274 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ 275 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ 276 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ 277 <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */ 278 <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */ 279 slew-rate = <2>; 280 }; 281 }; 282 283 dcmi_pins: dcmi@0 { 284 pins { 285 pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */ 286 <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */ 287 <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */ 288 <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */ 289 <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */ 290 <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */ 291 <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */ 292 <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */ 293 <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */ 294 <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */ 295 <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */ 296 <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */ 297 <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */ 298 <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */ 299 <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */ 300 bias-disable; 301 drive-push-pull; 302 slew-rate = <3>; 303 }; 304 }; 305 306 sdio_pins: sdio_pins@0 { 307 pins { 308 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */ 309 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */ 310 <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */ 311 <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */ 312 <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */ 313 <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */ 314 drive-push-pull; 315 slew-rate = <2>; 316 }; 317 }; 318 319 sdio_pins_od: sdio_pins_od@0 { 320 pins1 { 321 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */ 322 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */ 323 <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */ 324 <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */ 325 <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */ 326 drive-push-pull; 327 slew-rate = <2>; 328 }; 329 330 pins2 { 331 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */ 332 drive-open-drain; 333 slew-rate = <2>; 334 }; 335 }; 336 }; 337 }; 338}; 339