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1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 *
5 */
6
7#include "armv7-m.dtsi"
8#include <dt-bindings/clock/stm32fx-clock.h>
9#include <dt-bindings/mfd/stm32f7-rcc.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	clocks {
16		clk_hse: clk-hse {
17			#clock-cells = <0>;
18			compatible = "fixed-clock";
19			clock-frequency = <0>;
20		};
21
22		clk-lse {
23			#clock-cells = <0>;
24			compatible = "fixed-clock";
25			clock-frequency = <32768>;
26		};
27
28		clk-lsi {
29			#clock-cells = <0>;
30			compatible = "fixed-clock";
31			clock-frequency = <32000>;
32		};
33
34		clk_i2s_ckin: clk-i2s-ckin {
35			#clock-cells = <0>;
36			compatible = "fixed-clock";
37			clock-frequency = <48000000>;
38		};
39	};
40
41	soc {
42		timer2: timer@40000000 {
43			compatible = "st,stm32-timer";
44			reg = <0x40000000 0x400>;
45			interrupts = <28>;
46			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
47			status = "disabled";
48		};
49
50		timers2: timers@40000000 {
51			#address-cells = <1>;
52			#size-cells = <0>;
53			compatible = "st,stm32-timers";
54			reg = <0x40000000 0x400>;
55			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
56			clock-names = "int";
57			status = "disabled";
58
59			pwm {
60				compatible = "st,stm32-pwm";
61				#pwm-cells = <3>;
62				status = "disabled";
63			};
64
65			timer@1 {
66				compatible = "st,stm32-timer-trigger";
67				reg = <1>;
68				status = "disabled";
69			};
70		};
71
72		timer3: timer@40000400 {
73			compatible = "st,stm32-timer";
74			reg = <0x40000400 0x400>;
75			interrupts = <29>;
76			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
77			status = "disabled";
78		};
79
80		timers3: timers@40000400 {
81			#address-cells = <1>;
82			#size-cells = <0>;
83			compatible = "st,stm32-timers";
84			reg = <0x40000400 0x400>;
85			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
86			clock-names = "int";
87			status = "disabled";
88
89			pwm {
90				compatible = "st,stm32-pwm";
91				#pwm-cells = <3>;
92				status = "disabled";
93			};
94
95			timer@2 {
96				compatible = "st,stm32-timer-trigger";
97				reg = <2>;
98				status = "disabled";
99			};
100		};
101
102		timer4: timer@40000800 {
103			compatible = "st,stm32-timer";
104			reg = <0x40000800 0x400>;
105			interrupts = <30>;
106			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
107			status = "disabled";
108		};
109
110		timers4: timers@40000800 {
111			#address-cells = <1>;
112			#size-cells = <0>;
113			compatible = "st,stm32-timers";
114			reg = <0x40000800 0x400>;
115			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
116			clock-names = "int";
117			status = "disabled";
118
119			pwm {
120				compatible = "st,stm32-pwm";
121				#pwm-cells = <3>;
122				status = "disabled";
123			};
124
125			timer@3 {
126				compatible = "st,stm32-timer-trigger";
127				reg = <3>;
128				status = "disabled";
129			};
130		};
131
132		timer5: timer@40000c00 {
133			compatible = "st,stm32-timer";
134			reg = <0x40000c00 0x400>;
135			interrupts = <50>;
136			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
137		};
138
139		timers5: timers@40000c00 {
140			#address-cells = <1>;
141			#size-cells = <0>;
142			compatible = "st,stm32-timers";
143			reg = <0x40000C00 0x400>;
144			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
145			clock-names = "int";
146			status = "disabled";
147
148			pwm {
149				compatible = "st,stm32-pwm";
150				#pwm-cells = <3>;
151				status = "disabled";
152			};
153
154			timer@4 {
155				compatible = "st,stm32-timer-trigger";
156				reg = <4>;
157				status = "disabled";
158			};
159		};
160
161		timer6: timer@40001000 {
162			compatible = "st,stm32-timer";
163			reg = <0x40001000 0x400>;
164			interrupts = <54>;
165			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
166			status = "disabled";
167		};
168
169		timers6: timers@40001000 {
170			#address-cells = <1>;
171			#size-cells = <0>;
172			compatible = "st,stm32-timers";
173			reg = <0x40001000 0x400>;
174			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
175			clock-names = "int";
176			status = "disabled";
177
178			timer@5 {
179				compatible = "st,stm32-timer-trigger";
180				reg = <5>;
181				status = "disabled";
182			};
183		};
184
185		timer7: timer@40001400 {
186			compatible = "st,stm32-timer";
187			reg = <0x40001400 0x400>;
188			interrupts = <55>;
189			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
190			status = "disabled";
191		};
192
193		timers7: timers@40001400 {
194			#address-cells = <1>;
195			#size-cells = <0>;
196			compatible = "st,stm32-timers";
197			reg = <0x40001400 0x400>;
198			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
199			clock-names = "int";
200			status = "disabled";
201
202			timer@6 {
203				compatible = "st,stm32-timer-trigger";
204				reg = <6>;
205				status = "disabled";
206			};
207		};
208
209		timers12: timers@40001800 {
210			#address-cells = <1>;
211			#size-cells = <0>;
212			compatible = "st,stm32-timers";
213			reg = <0x40001800 0x400>;
214			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
215			clock-names = "int";
216			status = "disabled";
217
218			pwm {
219				compatible = "st,stm32-pwm";
220				#pwm-cells = <3>;
221				status = "disabled";
222			};
223
224			timer@11 {
225				compatible = "st,stm32-timer-trigger";
226				reg = <11>;
227				status = "disabled";
228			};
229		};
230
231		timers13: timers@40001c00 {
232			#address-cells = <1>;
233			#size-cells = <0>;
234			compatible = "st,stm32-timers";
235			reg = <0x40001C00 0x400>;
236			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
237			clock-names = "int";
238			status = "disabled";
239
240			pwm {
241				compatible = "st,stm32-pwm";
242				#pwm-cells = <3>;
243				status = "disabled";
244			};
245		};
246
247		timers14: timers@40002000 {
248			#address-cells = <1>;
249			#size-cells = <0>;
250			compatible = "st,stm32-timers";
251			reg = <0x40002000 0x400>;
252			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
253			clock-names = "int";
254			status = "disabled";
255
256			pwm {
257				compatible = "st,stm32-pwm";
258				#pwm-cells = <3>;
259				status = "disabled";
260			};
261		};
262
263		rtc: rtc@40002800 {
264			compatible = "st,stm32-rtc";
265			reg = <0x40002800 0x400>;
266			clocks = <&rcc 1 CLK_RTC>;
267			clock-names = "ck_rtc";
268			assigned-clocks = <&rcc 1 CLK_RTC>;
269			assigned-clock-parents = <&rcc 1 CLK_LSE>;
270			interrupt-parent = <&exti>;
271			interrupts = <17 1>;
272			interrupt-names = "alarm";
273			st,syscfg = <&pwrcfg 0x00 0x100>;
274			status = "disabled";
275		};
276
277		usart2: serial@40004400 {
278			compatible = "st,stm32f7-uart";
279			reg = <0x40004400 0x400>;
280			interrupts = <38>;
281			clocks = <&rcc 1 CLK_USART2>;
282			status = "disabled";
283		};
284
285		usart3: serial@40004800 {
286			compatible = "st,stm32f7-uart";
287			reg = <0x40004800 0x400>;
288			interrupts = <39>;
289			clocks = <&rcc 1 CLK_USART3>;
290			status = "disabled";
291		};
292
293		usart4: serial@40004c00 {
294			compatible = "st,stm32f7-uart";
295			reg = <0x40004c00 0x400>;
296			interrupts = <52>;
297			clocks = <&rcc 1 CLK_UART4>;
298			status = "disabled";
299		};
300
301		usart5: serial@40005000 {
302			compatible = "st,stm32f7-uart";
303			reg = <0x40005000 0x400>;
304			interrupts = <53>;
305			clocks = <&rcc 1 CLK_UART5>;
306			status = "disabled";
307		};
308
309		i2c1: i2c@40005400 {
310			compatible = "st,stm32f7-i2c";
311			reg = <0x40005400 0x400>;
312			interrupts = <31>,
313				     <32>;
314			resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
315			clocks = <&rcc 1 CLK_I2C1>;
316			#address-cells = <1>;
317			#size-cells = <0>;
318			status = "disabled";
319		};
320
321		i2c2: i2c@40005800 {
322			compatible = "st,stm32f7-i2c";
323			reg = <0x40005800 0x400>;
324			interrupts = <33>,
325				     <34>;
326			resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
327			clocks = <&rcc 1 CLK_I2C2>;
328			#address-cells = <1>;
329			#size-cells = <0>;
330			status = "disabled";
331		};
332
333		i2c3: i2c@40005C00 {
334			compatible = "st,stm32f7-i2c";
335			reg = <0x40005C00 0x400>;
336			interrupts = <72>,
337				     <73>;
338			resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
339			clocks = <&rcc 1 CLK_I2C3>;
340			#address-cells = <1>;
341			#size-cells = <0>;
342			status = "disabled";
343		};
344
345		i2c4: i2c@40006000 {
346			compatible = "st,stm32f7-i2c";
347			reg = <0x40006000 0x400>;
348			interrupts = <95>,
349				     <96>;
350			resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
351			clocks = <&rcc 1 CLK_I2C4>;
352			#address-cells = <1>;
353			#size-cells = <0>;
354			status = "disabled";
355		};
356
357		cec: cec@40006c00 {
358			compatible = "st,stm32-cec";
359			reg = <0x40006C00 0x400>;
360			interrupts = <94>;
361			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
362			clock-names = "cec", "hdmi-cec";
363			status = "disabled";
364		};
365
366		usart7: serial@40007800 {
367			compatible = "st,stm32f7-uart";
368			reg = <0x40007800 0x400>;
369			interrupts = <82>;
370			clocks = <&rcc 1 CLK_UART7>;
371			status = "disabled";
372		};
373
374		usart8: serial@40007c00 {
375			compatible = "st,stm32f7-uart";
376			reg = <0x40007c00 0x400>;
377			interrupts = <83>;
378			clocks = <&rcc 1 CLK_UART8>;
379			status = "disabled";
380		};
381
382		timers1: timers@40010000 {
383			#address-cells = <1>;
384			#size-cells = <0>;
385			compatible = "st,stm32-timers";
386			reg = <0x40010000 0x400>;
387			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
388			clock-names = "int";
389			status = "disabled";
390
391			pwm {
392				compatible = "st,stm32-pwm";
393				#pwm-cells = <3>;
394				status = "disabled";
395			};
396
397			timer@0 {
398				compatible = "st,stm32-timer-trigger";
399				reg = <0>;
400				status = "disabled";
401			};
402		};
403
404		timers8: timers@40010400 {
405			#address-cells = <1>;
406			#size-cells = <0>;
407			compatible = "st,stm32-timers";
408			reg = <0x40010400 0x400>;
409			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
410			clock-names = "int";
411			status = "disabled";
412
413			pwm {
414				compatible = "st,stm32-pwm";
415				#pwm-cells = <3>;
416				status = "disabled";
417			};
418
419			timer@7 {
420				compatible = "st,stm32-timer-trigger";
421				reg = <7>;
422				status = "disabled";
423			};
424		};
425
426		usart1: serial@40011000 {
427			compatible = "st,stm32f7-uart";
428			reg = <0x40011000 0x400>;
429			interrupts = <37>;
430			clocks = <&rcc 1 CLK_USART1>;
431			status = "disabled";
432		};
433
434		usart6: serial@40011400 {
435			compatible = "st,stm32f7-uart";
436			reg = <0x40011400 0x400>;
437			interrupts = <71>;
438			clocks = <&rcc 1 CLK_USART6>;
439			status = "disabled";
440		};
441
442		sdio2: sdio2@40011c00 {
443			compatible = "arm,pl180", "arm,primecell";
444			arm,primecell-periphid = <0x00880180>;
445			reg = <0x40011c00 0x400>;
446			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
447			clock-names = "apb_pclk";
448			interrupts = <103>;
449			max-frequency = <48000000>;
450			status = "disabled";
451		};
452
453		sdio1: sdio1@40012c00 {
454			compatible = "arm,pl180", "arm,primecell";
455			arm,primecell-periphid = <0x00880180>;
456			reg = <0x40012c00 0x400>;
457			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
458			clock-names = "apb_pclk";
459			interrupts = <49>;
460			max-frequency = <48000000>;
461			status = "disabled";
462		};
463
464		syscfg: system-config@40013800 {
465			compatible = "syscon";
466			reg = <0x40013800 0x400>;
467		};
468
469		exti: interrupt-controller@40013c00 {
470			compatible = "st,stm32-exti";
471			interrupt-controller;
472			#interrupt-cells = <2>;
473			reg = <0x40013C00 0x400>;
474			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
475		};
476
477		timers9: timers@40014000 {
478			#address-cells = <1>;
479			#size-cells = <0>;
480			compatible = "st,stm32-timers";
481			reg = <0x40014000 0x400>;
482			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
483			clock-names = "int";
484			status = "disabled";
485
486			pwm {
487				compatible = "st,stm32-pwm";
488				#pwm-cells = <3>;
489				status = "disabled";
490			};
491
492			timer@8 {
493				compatible = "st,stm32-timer-trigger";
494				reg = <8>;
495				status = "disabled";
496			};
497		};
498
499		timers10: timers@40014400 {
500			#address-cells = <1>;
501			#size-cells = <0>;
502			compatible = "st,stm32-timers";
503			reg = <0x40014400 0x400>;
504			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
505			clock-names = "int";
506			status = "disabled";
507
508			pwm {
509				compatible = "st,stm32-pwm";
510				#pwm-cells = <3>;
511				status = "disabled";
512			};
513		};
514
515		timers11: timers@40014800 {
516			#address-cells = <1>;
517			#size-cells = <0>;
518			compatible = "st,stm32-timers";
519			reg = <0x40014800 0x400>;
520			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
521			clock-names = "int";
522			status = "disabled";
523
524			pwm {
525				compatible = "st,stm32-pwm";
526				#pwm-cells = <3>;
527				status = "disabled";
528			};
529		};
530
531		pwrcfg: power-config@40007000 {
532			compatible = "syscon";
533			reg = <0x40007000 0x400>;
534		};
535
536		crc: crc@40023000 {
537			compatible = "st,stm32f7-crc";
538			reg = <0x40023000 0x400>;
539			clocks = <&rcc 0 12>;
540			status = "disabled";
541		};
542
543		rcc: rcc@40023800 {
544			#reset-cells = <1>;
545			#clock-cells = <2>;
546			compatible = "st,stm32f746-rcc", "st,stm32-rcc";
547			reg = <0x40023800 0x400>;
548			clocks = <&clk_hse>, <&clk_i2s_ckin>;
549			st,syscfg = <&pwrcfg>;
550			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
551			assigned-clock-rates = <1000000>;
552		};
553
554		dma1: dma@40026000 {
555			compatible = "st,stm32-dma";
556			reg = <0x40026000 0x400>;
557			interrupts = <11>,
558				     <12>,
559				     <13>,
560				     <14>,
561				     <15>,
562				     <16>,
563				     <17>,
564				     <47>;
565			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
566			#dma-cells = <4>;
567			status = "disabled";
568		};
569
570		dma2: dma@40026400 {
571			compatible = "st,stm32-dma";
572			reg = <0x40026400 0x400>;
573			interrupts = <56>,
574				     <57>,
575				     <58>,
576				     <59>,
577				     <60>,
578				     <68>,
579				     <69>,
580				     <70>;
581			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
582			#dma-cells = <4>;
583			st,mem2mem;
584			status = "disabled";
585		};
586
587		usbotg_hs: usb@40040000 {
588			compatible = "st,stm32f7-hsotg";
589			reg = <0x40040000 0x40000>;
590			interrupts = <77>;
591			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
592			clock-names = "otg";
593			g-rx-fifo-size = <256>;
594			g-np-tx-fifo-size = <32>;
595			g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
596			status = "disabled";
597		};
598
599		usbotg_fs: usb@50000000 {
600			compatible = "st,stm32f4x9-fsotg";
601			reg = <0x50000000 0x40000>;
602			interrupts = <67>;
603			clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
604			clock-names = "otg";
605			status = "disabled";
606		};
607	};
608};
609
610&systick {
611	clocks = <&rcc 1 0>;
612	status = "okay";
613};
614