1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2/* 3 * Copyright : STMicroelectronics 2018 4 */ 5 6#include <dt-bindings/clock/stm32mp1-clksrc.h> 7#include "stm32mp157-u-boot.dtsi" 8#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 9 10/ { 11 aliases { 12 i2c3 = &i2c4; 13 mmc0 = &sdmmc1; 14 mmc1 = &sdmmc2; 15 }; 16 17 config { 18 u-boot,boot-led = "heartbeat"; 19 u-boot,error-led = "error"; 20 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; 21 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; 22 }; 23 24 led { 25 red { 26 label = "error"; 27 gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; 28 default-state = "off"; 29 status = "okay"; 30 }; 31 32 blue { 33 default-state = "on"; 34 }; 35 }; 36}; 37 38&clk_hse { 39 st,digbypass; 40}; 41 42&i2c4 { 43 u-boot,dm-pre-reloc; 44}; 45 46&i2c4_pins_a { 47 u-boot,dm-pre-reloc; 48 pins { 49 u-boot,dm-pre-reloc; 50 }; 51}; 52 53&pmic { 54 u-boot,dm-pre-reloc; 55}; 56 57&rcc { 58 st,clksrc = < 59 CLK_MPU_PLL1P 60 CLK_AXI_PLL2P 61 CLK_MCU_PLL3P 62 CLK_PLL12_HSE 63 CLK_PLL3_HSE 64 CLK_PLL4_HSE 65 CLK_RTC_LSE 66 CLK_MCO1_DISABLED 67 CLK_MCO2_DISABLED 68 >; 69 70 st,clkdiv = < 71 1 /*MPU*/ 72 0 /*AXI*/ 73 0 /*MCU*/ 74 1 /*APB1*/ 75 1 /*APB2*/ 76 1 /*APB3*/ 77 1 /*APB4*/ 78 2 /*APB5*/ 79 23 /*RTC*/ 80 0 /*MCO1*/ 81 0 /*MCO2*/ 82 >; 83 84 st,pkcs = < 85 CLK_CKPER_HSE 86 CLK_FMC_ACLK 87 CLK_QSPI_ACLK 88 CLK_ETH_DISABLED 89 CLK_SDMMC12_PLL4P 90 CLK_DSI_DSIPLL 91 CLK_STGEN_HSE 92 CLK_USBPHY_HSE 93 CLK_SPI2S1_PLL3Q 94 CLK_SPI2S23_PLL3Q 95 CLK_SPI45_HSI 96 CLK_SPI6_HSI 97 CLK_I2C46_HSI 98 CLK_SDMMC3_PLL4P 99 CLK_USBO_USBPHY 100 CLK_ADC_CKPER 101 CLK_CEC_LSE 102 CLK_I2C12_HSI 103 CLK_I2C35_HSI 104 CLK_UART1_HSI 105 CLK_UART24_HSI 106 CLK_UART35_HSI 107 CLK_UART6_HSI 108 CLK_UART78_HSI 109 CLK_SPDIF_PLL4P 110 CLK_FDCAN_PLL4Q 111 CLK_SAI1_PLL3Q 112 CLK_SAI2_PLL3Q 113 CLK_SAI3_PLL3Q 114 CLK_SAI4_PLL3Q 115 CLK_RNG1_LSI 116 CLK_RNG2_LSI 117 CLK_LPTIM1_PCLK1 118 CLK_LPTIM23_PCLK3 119 CLK_LPTIM45_LSE 120 >; 121 122 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 123 pll1: st,pll@0 { 124 cfg = < 2 80 0 0 0 PQR(1,0,0) >; 125 frac = < 0x800 >; 126 u-boot,dm-pre-reloc; 127 }; 128 129 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 130 pll2: st,pll@1 { 131 cfg = < 2 65 1 0 0 PQR(1,1,1) >; 132 frac = < 0x1400 >; 133 u-boot,dm-pre-reloc; 134 }; 135 136 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 137 pll3: st,pll@2 { 138 cfg = < 1 33 1 16 36 PQR(1,1,1) >; 139 frac = < 0x1a04 >; 140 u-boot,dm-pre-reloc; 141 }; 142 143 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 144 pll4: st,pll@3 { 145 cfg = < 3 98 5 7 7 PQR(1,1,1) >; 146 u-boot,dm-pre-reloc; 147 }; 148}; 149 150&sdmmc1 { 151 u-boot,dm-spl; 152}; 153 154&sdmmc1_b4_pins_a { 155 u-boot,dm-spl; 156 pins { 157 u-boot,dm-spl; 158 }; 159}; 160 161&sdmmc1_dir_pins_a { 162 u-boot,dm-spl; 163 pins1 { 164 u-boot,dm-spl; 165 }; 166 pins2 { 167 u-boot,dm-spl; 168 }; 169}; 170 171&sdmmc2 { 172 u-boot,dm-spl; 173}; 174 175&sdmmc2_b4_pins_a { 176 u-boot,dm-spl; 177 pins1 { 178 u-boot,dm-spl; 179 }; 180 pins2 { 181 u-boot,dm-spl; 182 }; 183}; 184 185&sdmmc2_d47_pins_a { 186 u-boot,dm-spl; 187 pins { 188 u-boot,dm-spl; 189 }; 190}; 191 192&uart4 { 193 u-boot,dm-pre-reloc; 194}; 195 196&uart4_pins_a { 197 u-boot,dm-pre-reloc; 198 pins1 { 199 u-boot,dm-pre-reloc; 200 }; 201 pins2 { 202 u-boot,dm-pre-reloc; 203 /* pull-up on rx to avoid floating level */ 204 bias-pull-up; 205 }; 206}; 207