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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a7";
20			device_type = "cpu";
21			reg = <0>;
22		};
23
24		cpu1: cpu@1 {
25			compatible = "arm,cortex-a7";
26			device_type = "cpu";
27			reg = <1>;
28		};
29	};
30
31	psci {
32		compatible = "arm,psci-1.0";
33		method = "smc";
34		cpu_off = <0x84000002>;
35		cpu_on = <0x84000003>;
36	};
37
38	intc: interrupt-controller@a0021000 {
39		compatible = "arm,cortex-a7-gic";
40		#interrupt-cells = <3>;
41		interrupt-controller;
42		reg = <0xa0021000 0x1000>,
43		      <0xa0022000 0x2000>;
44	};
45
46	timer {
47		compatible = "arm,armv7-timer";
48		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
49			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
51			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
52		interrupt-parent = <&intc>;
53	};
54
55	clocks {
56		clk_hse: clk-hse {
57			#clock-cells = <0>;
58			compatible = "fixed-clock";
59			clock-frequency = <24000000>;
60		};
61
62		clk_hsi: clk-hsi {
63			#clock-cells = <0>;
64			compatible = "fixed-clock";
65			clock-frequency = <64000000>;
66		};
67
68		clk_lse: clk-lse {
69			#clock-cells = <0>;
70			compatible = "fixed-clock";
71			clock-frequency = <32768>;
72		};
73
74		clk_lsi: clk-lsi {
75			#clock-cells = <0>;
76			compatible = "fixed-clock";
77			clock-frequency = <32000>;
78		};
79
80		clk_csi: clk-csi {
81			#clock-cells = <0>;
82			compatible = "fixed-clock";
83			clock-frequency = <4000000>;
84		};
85	};
86
87	thermal-zones {
88		cpu_thermal: cpu-thermal {
89			polling-delay-passive = <0>;
90			polling-delay = <0>;
91			thermal-sensors = <&dts>;
92
93			trips {
94				cpu_alert1: cpu-alert1 {
95					temperature = <85000>;
96					hysteresis = <0>;
97					type = "passive";
98				};
99
100				cpu-crit {
101					temperature = <120000>;
102					hysteresis = <0>;
103					type = "critical";
104				};
105			};
106
107			cooling-maps {
108			};
109		};
110	};
111
112	booster: regulator-booster {
113		compatible = "st,stm32mp1-booster";
114		st,syscfg = <&syscfg>;
115		status = "disabled";
116	};
117
118	reboot {
119		compatible = "syscon-reboot";
120		regmap = <&rcc>;
121		offset = <0x404>;
122		mask = <0x1>;
123	};
124
125	soc {
126		compatible = "simple-bus";
127		#address-cells = <1>;
128		#size-cells = <1>;
129		interrupt-parent = <&intc>;
130		ranges;
131
132		timers2: timer@40000000 {
133			#address-cells = <1>;
134			#size-cells = <0>;
135			compatible = "st,stm32-timers";
136			reg = <0x40000000 0x400>;
137			clocks = <&rcc TIM2_K>;
138			clock-names = "int";
139			dmas = <&dmamux1 18 0x400 0x1>,
140			       <&dmamux1 19 0x400 0x1>,
141			       <&dmamux1 20 0x400 0x1>,
142			       <&dmamux1 21 0x400 0x1>,
143			       <&dmamux1 22 0x400 0x1>;
144			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
145			status = "disabled";
146
147			pwm {
148				compatible = "st,stm32-pwm";
149				#pwm-cells = <3>;
150				status = "disabled";
151			};
152
153			timer@1 {
154				compatible = "st,stm32h7-timer-trigger";
155				reg = <1>;
156				status = "disabled";
157			};
158		};
159
160		timers3: timer@40001000 {
161			#address-cells = <1>;
162			#size-cells = <0>;
163			compatible = "st,stm32-timers";
164			reg = <0x40001000 0x400>;
165			clocks = <&rcc TIM3_K>;
166			clock-names = "int";
167			dmas = <&dmamux1 23 0x400 0x1>,
168			       <&dmamux1 24 0x400 0x1>,
169			       <&dmamux1 25 0x400 0x1>,
170			       <&dmamux1 26 0x400 0x1>,
171			       <&dmamux1 27 0x400 0x1>,
172			       <&dmamux1 28 0x400 0x1>;
173			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
174			status = "disabled";
175
176			pwm {
177				compatible = "st,stm32-pwm";
178				#pwm-cells = <3>;
179				status = "disabled";
180			};
181
182			timer@2 {
183				compatible = "st,stm32h7-timer-trigger";
184				reg = <2>;
185				status = "disabled";
186			};
187		};
188
189		timers4: timer@40002000 {
190			#address-cells = <1>;
191			#size-cells = <0>;
192			compatible = "st,stm32-timers";
193			reg = <0x40002000 0x400>;
194			clocks = <&rcc TIM4_K>;
195			clock-names = "int";
196			dmas = <&dmamux1 29 0x400 0x1>,
197			       <&dmamux1 30 0x400 0x1>,
198			       <&dmamux1 31 0x400 0x1>,
199			       <&dmamux1 32 0x400 0x1>;
200			dma-names = "ch1", "ch2", "ch3", "ch4";
201			status = "disabled";
202
203			pwm {
204				compatible = "st,stm32-pwm";
205				#pwm-cells = <3>;
206				status = "disabled";
207			};
208
209			timer@3 {
210				compatible = "st,stm32h7-timer-trigger";
211				reg = <3>;
212				status = "disabled";
213			};
214		};
215
216		timers5: timer@40003000 {
217			#address-cells = <1>;
218			#size-cells = <0>;
219			compatible = "st,stm32-timers";
220			reg = <0x40003000 0x400>;
221			clocks = <&rcc TIM5_K>;
222			clock-names = "int";
223			dmas = <&dmamux1 55 0x400 0x1>,
224			       <&dmamux1 56 0x400 0x1>,
225			       <&dmamux1 57 0x400 0x1>,
226			       <&dmamux1 58 0x400 0x1>,
227			       <&dmamux1 59 0x400 0x1>,
228			       <&dmamux1 60 0x400 0x1>;
229			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
230			status = "disabled";
231
232			pwm {
233				compatible = "st,stm32-pwm";
234				#pwm-cells = <3>;
235				status = "disabled";
236			};
237
238			timer@4 {
239				compatible = "st,stm32h7-timer-trigger";
240				reg = <4>;
241				status = "disabled";
242			};
243		};
244
245		timers6: timer@40004000 {
246			#address-cells = <1>;
247			#size-cells = <0>;
248			compatible = "st,stm32-timers";
249			reg = <0x40004000 0x400>;
250			clocks = <&rcc TIM6_K>;
251			clock-names = "int";
252			dmas = <&dmamux1 69 0x400 0x1>;
253			dma-names = "up";
254			status = "disabled";
255
256			timer@5 {
257				compatible = "st,stm32h7-timer-trigger";
258				reg = <5>;
259				status = "disabled";
260			};
261		};
262
263		timers7: timer@40005000 {
264			#address-cells = <1>;
265			#size-cells = <0>;
266			compatible = "st,stm32-timers";
267			reg = <0x40005000 0x400>;
268			clocks = <&rcc TIM7_K>;
269			clock-names = "int";
270			dmas = <&dmamux1 70 0x400 0x1>;
271			dma-names = "up";
272			status = "disabled";
273
274			timer@6 {
275				compatible = "st,stm32h7-timer-trigger";
276				reg = <6>;
277				status = "disabled";
278			};
279		};
280
281		timers12: timer@40006000 {
282			#address-cells = <1>;
283			#size-cells = <0>;
284			compatible = "st,stm32-timers";
285			reg = <0x40006000 0x400>;
286			clocks = <&rcc TIM12_K>;
287			clock-names = "int";
288			status = "disabled";
289
290			pwm {
291				compatible = "st,stm32-pwm";
292				#pwm-cells = <3>;
293				status = "disabled";
294			};
295
296			timer@11 {
297				compatible = "st,stm32h7-timer-trigger";
298				reg = <11>;
299				status = "disabled";
300			};
301		};
302
303		timers13: timer@40007000 {
304			#address-cells = <1>;
305			#size-cells = <0>;
306			compatible = "st,stm32-timers";
307			reg = <0x40007000 0x400>;
308			clocks = <&rcc TIM13_K>;
309			clock-names = "int";
310			status = "disabled";
311
312			pwm {
313				compatible = "st,stm32-pwm";
314				#pwm-cells = <3>;
315				status = "disabled";
316			};
317
318			timer@12 {
319				compatible = "st,stm32h7-timer-trigger";
320				reg = <12>;
321				status = "disabled";
322			};
323		};
324
325		timers14: timer@40008000 {
326			#address-cells = <1>;
327			#size-cells = <0>;
328			compatible = "st,stm32-timers";
329			reg = <0x40008000 0x400>;
330			clocks = <&rcc TIM14_K>;
331			clock-names = "int";
332			status = "disabled";
333
334			pwm {
335				compatible = "st,stm32-pwm";
336				#pwm-cells = <3>;
337				status = "disabled";
338			};
339
340			timer@13 {
341				compatible = "st,stm32h7-timer-trigger";
342				reg = <13>;
343				status = "disabled";
344			};
345		};
346
347		lptimer1: timer@40009000 {
348			#address-cells = <1>;
349			#size-cells = <0>;
350			compatible = "st,stm32-lptimer";
351			reg = <0x40009000 0x400>;
352			clocks = <&rcc LPTIM1_K>;
353			clock-names = "mux";
354			status = "disabled";
355
356			pwm {
357				compatible = "st,stm32-pwm-lp";
358				#pwm-cells = <3>;
359				status = "disabled";
360			};
361
362			trigger@0 {
363				compatible = "st,stm32-lptimer-trigger";
364				reg = <0>;
365				status = "disabled";
366			};
367
368			counter {
369				compatible = "st,stm32-lptimer-counter";
370				status = "disabled";
371			};
372		};
373
374		spi2: spi@4000b000 {
375			#address-cells = <1>;
376			#size-cells = <0>;
377			compatible = "st,stm32h7-spi";
378			reg = <0x4000b000 0x400>;
379			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
380			clocks = <&rcc SPI2_K>;
381			resets = <&rcc SPI2_R>;
382			dmas = <&dmamux1 39 0x400 0x05>,
383			       <&dmamux1 40 0x400 0x05>;
384			dma-names = "rx", "tx";
385			status = "disabled";
386		};
387
388		i2s2: audio-controller@4000b000 {
389			compatible = "st,stm32h7-i2s";
390			#sound-dai-cells = <0>;
391			reg = <0x4000b000 0x400>;
392			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
393			dmas = <&dmamux1 39 0x400 0x01>,
394			       <&dmamux1 40 0x400 0x01>;
395			dma-names = "rx", "tx";
396			status = "disabled";
397		};
398
399		spi3: spi@4000c000 {
400			#address-cells = <1>;
401			#size-cells = <0>;
402			compatible = "st,stm32h7-spi";
403			reg = <0x4000c000 0x400>;
404			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
405			clocks = <&rcc SPI3_K>;
406			resets = <&rcc SPI3_R>;
407			dmas = <&dmamux1 61 0x400 0x05>,
408			       <&dmamux1 62 0x400 0x05>;
409			dma-names = "rx", "tx";
410			status = "disabled";
411		};
412
413		i2s3: audio-controller@4000c000 {
414			compatible = "st,stm32h7-i2s";
415			#sound-dai-cells = <0>;
416			reg = <0x4000c000 0x400>;
417			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
418			dmas = <&dmamux1 61 0x400 0x01>,
419			       <&dmamux1 62 0x400 0x01>;
420			dma-names = "rx", "tx";
421			status = "disabled";
422		};
423
424		spdifrx: audio-controller@4000d000 {
425			compatible = "st,stm32h7-spdifrx";
426			#sound-dai-cells = <0>;
427			reg = <0x4000d000 0x400>;
428			clocks = <&rcc SPDIF_K>;
429			clock-names = "kclk";
430			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
431			dmas = <&dmamux1 93 0x400 0x01>,
432			       <&dmamux1 94 0x400 0x01>;
433			dma-names = "rx", "rx-ctrl";
434			status = "disabled";
435		};
436
437		usart2: serial@4000e000 {
438			compatible = "st,stm32h7-uart";
439			reg = <0x4000e000 0x400>;
440			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
441			clocks = <&rcc USART2_K>;
442			status = "disabled";
443		};
444
445		usart3: serial@4000f000 {
446			compatible = "st,stm32h7-uart";
447			reg = <0x4000f000 0x400>;
448			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
449			clocks = <&rcc USART3_K>;
450			status = "disabled";
451		};
452
453		uart4: serial@40010000 {
454			compatible = "st,stm32h7-uart";
455			reg = <0x40010000 0x400>;
456			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
457			clocks = <&rcc UART4_K>;
458			status = "disabled";
459		};
460
461		uart5: serial@40011000 {
462			compatible = "st,stm32h7-uart";
463			reg = <0x40011000 0x400>;
464			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
465			clocks = <&rcc UART5_K>;
466			status = "disabled";
467		};
468
469		i2c1: i2c@40012000 {
470			compatible = "st,stm32f7-i2c";
471			reg = <0x40012000 0x400>;
472			interrupt-names = "event", "error";
473			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
474				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
475			clocks = <&rcc I2C1_K>;
476			resets = <&rcc I2C1_R>;
477			#address-cells = <1>;
478			#size-cells = <0>;
479			status = "disabled";
480		};
481
482		i2c2: i2c@40013000 {
483			compatible = "st,stm32f7-i2c";
484			reg = <0x40013000 0x400>;
485			interrupt-names = "event", "error";
486			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
487				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
488			clocks = <&rcc I2C2_K>;
489			resets = <&rcc I2C2_R>;
490			#address-cells = <1>;
491			#size-cells = <0>;
492			status = "disabled";
493		};
494
495		i2c3: i2c@40014000 {
496			compatible = "st,stm32f7-i2c";
497			reg = <0x40014000 0x400>;
498			interrupt-names = "event", "error";
499			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
500				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
501			clocks = <&rcc I2C3_K>;
502			resets = <&rcc I2C3_R>;
503			#address-cells = <1>;
504			#size-cells = <0>;
505			status = "disabled";
506		};
507
508		i2c5: i2c@40015000 {
509			compatible = "st,stm32f7-i2c";
510			reg = <0x40015000 0x400>;
511			interrupt-names = "event", "error";
512			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
513				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
514			clocks = <&rcc I2C5_K>;
515			resets = <&rcc I2C5_R>;
516			#address-cells = <1>;
517			#size-cells = <0>;
518			status = "disabled";
519		};
520
521		cec: cec@40016000 {
522			compatible = "st,stm32-cec";
523			reg = <0x40016000 0x400>;
524			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
525			clocks = <&rcc CEC_K>, <&clk_lse>;
526			clock-names = "cec", "hdmi-cec";
527			status = "disabled";
528		};
529
530		dac: dac@40017000 {
531			compatible = "st,stm32h7-dac-core";
532			reg = <0x40017000 0x400>;
533			clocks = <&rcc DAC12>;
534			clock-names = "pclk";
535			#address-cells = <1>;
536			#size-cells = <0>;
537			status = "disabled";
538
539			dac1: dac@1 {
540				compatible = "st,stm32-dac";
541				#io-channels-cells = <1>;
542				reg = <1>;
543				status = "disabled";
544			};
545
546			dac2: dac@2 {
547				compatible = "st,stm32-dac";
548				#io-channels-cells = <1>;
549				reg = <2>;
550				status = "disabled";
551			};
552		};
553
554		uart7: serial@40018000 {
555			compatible = "st,stm32h7-uart";
556			reg = <0x40018000 0x400>;
557			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
558			clocks = <&rcc UART7_K>;
559			status = "disabled";
560		};
561
562		uart8: serial@40019000 {
563			compatible = "st,stm32h7-uart";
564			reg = <0x40019000 0x400>;
565			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
566			clocks = <&rcc UART8_K>;
567			status = "disabled";
568		};
569
570		timers1: timer@44000000 {
571			#address-cells = <1>;
572			#size-cells = <0>;
573			compatible = "st,stm32-timers";
574			reg = <0x44000000 0x400>;
575			clocks = <&rcc TIM1_K>;
576			clock-names = "int";
577			dmas = <&dmamux1 11 0x400 0x1>,
578			       <&dmamux1 12 0x400 0x1>,
579			       <&dmamux1 13 0x400 0x1>,
580			       <&dmamux1 14 0x400 0x1>,
581			       <&dmamux1 15 0x400 0x1>,
582			       <&dmamux1 16 0x400 0x1>,
583			       <&dmamux1 17 0x400 0x1>;
584			dma-names = "ch1", "ch2", "ch3", "ch4",
585				    "up", "trig", "com";
586			status = "disabled";
587
588			pwm {
589				compatible = "st,stm32-pwm";
590				#pwm-cells = <3>;
591				status = "disabled";
592			};
593
594			timer@0 {
595				compatible = "st,stm32h7-timer-trigger";
596				reg = <0>;
597				status = "disabled";
598			};
599		};
600
601		timers8: timer@44001000 {
602			#address-cells = <1>;
603			#size-cells = <0>;
604			compatible = "st,stm32-timers";
605			reg = <0x44001000 0x400>;
606			clocks = <&rcc TIM8_K>;
607			clock-names = "int";
608			dmas = <&dmamux1 47 0x400 0x1>,
609			       <&dmamux1 48 0x400 0x1>,
610			       <&dmamux1 49 0x400 0x1>,
611			       <&dmamux1 50 0x400 0x1>,
612			       <&dmamux1 51 0x400 0x1>,
613			       <&dmamux1 52 0x400 0x1>,
614			       <&dmamux1 53 0x400 0x1>;
615			dma-names = "ch1", "ch2", "ch3", "ch4",
616				    "up", "trig", "com";
617			status = "disabled";
618
619			pwm {
620				compatible = "st,stm32-pwm";
621				#pwm-cells = <3>;
622				status = "disabled";
623			};
624
625			timer@7 {
626				compatible = "st,stm32h7-timer-trigger";
627				reg = <7>;
628				status = "disabled";
629			};
630		};
631
632		usart6: serial@44003000 {
633			compatible = "st,stm32h7-uart";
634			reg = <0x44003000 0x400>;
635			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
636			clocks = <&rcc USART6_K>;
637			status = "disabled";
638		};
639
640		spi1: spi@44004000 {
641			#address-cells = <1>;
642			#size-cells = <0>;
643			compatible = "st,stm32h7-spi";
644			reg = <0x44004000 0x400>;
645			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
646			clocks = <&rcc SPI1_K>;
647			resets = <&rcc SPI1_R>;
648			dmas = <&dmamux1 37 0x400 0x05>,
649			       <&dmamux1 38 0x400 0x05>;
650			dma-names = "rx", "tx";
651			status = "disabled";
652		};
653
654		i2s1: audio-controller@44004000 {
655			compatible = "st,stm32h7-i2s";
656			#sound-dai-cells = <0>;
657			reg = <0x44004000 0x400>;
658			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
659			dmas = <&dmamux1 37 0x400 0x01>,
660			       <&dmamux1 38 0x400 0x01>;
661			dma-names = "rx", "tx";
662			status = "disabled";
663		};
664
665		spi4: spi@44005000 {
666			#address-cells = <1>;
667			#size-cells = <0>;
668			compatible = "st,stm32h7-spi";
669			reg = <0x44005000 0x400>;
670			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
671			clocks = <&rcc SPI4_K>;
672			resets = <&rcc SPI4_R>;
673			dmas = <&dmamux1 83 0x400 0x05>,
674			       <&dmamux1 84 0x400 0x05>;
675			dma-names = "rx", "tx";
676			status = "disabled";
677		};
678
679		timers15: timer@44006000 {
680			#address-cells = <1>;
681			#size-cells = <0>;
682			compatible = "st,stm32-timers";
683			reg = <0x44006000 0x400>;
684			clocks = <&rcc TIM15_K>;
685			clock-names = "int";
686			dmas = <&dmamux1 105 0x400 0x1>,
687			       <&dmamux1 106 0x400 0x1>,
688			       <&dmamux1 107 0x400 0x1>,
689			       <&dmamux1 108 0x400 0x1>;
690			dma-names = "ch1", "up", "trig", "com";
691			status = "disabled";
692
693			pwm {
694				compatible = "st,stm32-pwm";
695				#pwm-cells = <3>;
696				status = "disabled";
697			};
698
699			timer@14 {
700				compatible = "st,stm32h7-timer-trigger";
701				reg = <14>;
702				status = "disabled";
703			};
704		};
705
706		timers16: timer@44007000 {
707			#address-cells = <1>;
708			#size-cells = <0>;
709			compatible = "st,stm32-timers";
710			reg = <0x44007000 0x400>;
711			clocks = <&rcc TIM16_K>;
712			clock-names = "int";
713			dmas = <&dmamux1 109 0x400 0x1>,
714			       <&dmamux1 110 0x400 0x1>;
715			dma-names = "ch1", "up";
716			status = "disabled";
717
718			pwm {
719				compatible = "st,stm32-pwm";
720				#pwm-cells = <3>;
721				status = "disabled";
722			};
723			timer@15 {
724				compatible = "st,stm32h7-timer-trigger";
725				reg = <15>;
726				status = "disabled";
727			};
728		};
729
730		timers17: timer@44008000 {
731			#address-cells = <1>;
732			#size-cells = <0>;
733			compatible = "st,stm32-timers";
734			reg = <0x44008000 0x400>;
735			clocks = <&rcc TIM17_K>;
736			clock-names = "int";
737			dmas = <&dmamux1 111 0x400 0x1>,
738			       <&dmamux1 112 0x400 0x1>;
739			dma-names = "ch1", "up";
740			status = "disabled";
741
742			pwm {
743				compatible = "st,stm32-pwm";
744				#pwm-cells = <3>;
745				status = "disabled";
746			};
747
748			timer@16 {
749				compatible = "st,stm32h7-timer-trigger";
750				reg = <16>;
751				status = "disabled";
752			};
753		};
754
755		spi5: spi@44009000 {
756			#address-cells = <1>;
757			#size-cells = <0>;
758			compatible = "st,stm32h7-spi";
759			reg = <0x44009000 0x400>;
760			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
761			clocks = <&rcc SPI5_K>;
762			resets = <&rcc SPI5_R>;
763			dmas = <&dmamux1 85 0x400 0x05>,
764			       <&dmamux1 86 0x400 0x05>;
765			dma-names = "rx", "tx";
766			status = "disabled";
767		};
768
769		sai1: sai@4400a000 {
770			compatible = "st,stm32h7-sai";
771			#address-cells = <1>;
772			#size-cells = <1>;
773			ranges = <0 0x4400a000 0x400>;
774			reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
775			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
776			resets = <&rcc SAI1_R>;
777			status = "disabled";
778
779			sai1a: audio-controller@4400a004 {
780				#sound-dai-cells = <0>;
781
782				compatible = "st,stm32-sai-sub-a";
783				reg = <0x4 0x1c>;
784				clocks = <&rcc SAI1_K>;
785				clock-names = "sai_ck";
786				dmas = <&dmamux1 87 0x400 0x01>;
787				status = "disabled";
788			};
789
790			sai1b: audio-controller@4400a024 {
791				#sound-dai-cells = <0>;
792				compatible = "st,stm32-sai-sub-b";
793				reg = <0x24 0x1c>;
794				clocks = <&rcc SAI1_K>;
795				clock-names = "sai_ck";
796				dmas = <&dmamux1 88 0x400 0x01>;
797				status = "disabled";
798			};
799		};
800
801		sai2: sai@4400b000 {
802			compatible = "st,stm32h7-sai";
803			#address-cells = <1>;
804			#size-cells = <1>;
805			ranges = <0 0x4400b000 0x400>;
806			reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
807			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
808			resets = <&rcc SAI2_R>;
809			status = "disabled";
810
811			sai2a: audio-controller@4400b004 {
812				#sound-dai-cells = <0>;
813				compatible = "st,stm32-sai-sub-a";
814				reg = <0x4 0x1c>;
815				clocks = <&rcc SAI2_K>;
816				clock-names = "sai_ck";
817				dmas = <&dmamux1 89 0x400 0x01>;
818				status = "disabled";
819			};
820
821			sai2b: audio-controller@4400b024 {
822				#sound-dai-cells = <0>;
823				compatible = "st,stm32-sai-sub-b";
824				reg = <0x24 0x1c>;
825				clocks = <&rcc SAI2_K>;
826				clock-names = "sai_ck";
827				dmas = <&dmamux1 90 0x400 0x01>;
828				status = "disabled";
829			};
830		};
831
832		sai3: sai@4400c000 {
833			compatible = "st,stm32h7-sai";
834			#address-cells = <1>;
835			#size-cells = <1>;
836			ranges = <0 0x4400c000 0x400>;
837			reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
838			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
839			resets = <&rcc SAI3_R>;
840			status = "disabled";
841
842			sai3a: audio-controller@4400c004 {
843				#sound-dai-cells = <0>;
844				compatible = "st,stm32-sai-sub-a";
845				reg = <0x04 0x1c>;
846				clocks = <&rcc SAI3_K>;
847				clock-names = "sai_ck";
848				dmas = <&dmamux1 113 0x400 0x01>;
849				status = "disabled";
850			};
851
852			sai3b: audio-controller@4400c024 {
853				#sound-dai-cells = <0>;
854				compatible = "st,stm32-sai-sub-b";
855				reg = <0x24 0x1c>;
856				clocks = <&rcc SAI3_K>;
857				clock-names = "sai_ck";
858				dmas = <&dmamux1 114 0x400 0x01>;
859				status = "disabled";
860			};
861		};
862
863		dfsdm: dfsdm@4400d000 {
864			compatible = "st,stm32mp1-dfsdm";
865			reg = <0x4400d000 0x800>;
866			clocks = <&rcc DFSDM_K>;
867			clock-names = "dfsdm";
868			#address-cells = <1>;
869			#size-cells = <0>;
870			status = "disabled";
871
872			dfsdm0: filter@0 {
873				compatible = "st,stm32-dfsdm-adc";
874				#io-channel-cells = <1>;
875				reg = <0>;
876				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
877				dmas = <&dmamux1 101 0x400 0x01>;
878				dma-names = "rx";
879				status = "disabled";
880			};
881
882			dfsdm1: filter@1 {
883				compatible = "st,stm32-dfsdm-adc";
884				#io-channel-cells = <1>;
885				reg = <1>;
886				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
887				dmas = <&dmamux1 102 0x400 0x01>;
888				dma-names = "rx";
889				status = "disabled";
890			};
891
892			dfsdm2: filter@2 {
893				compatible = "st,stm32-dfsdm-adc";
894				#io-channel-cells = <1>;
895				reg = <2>;
896				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
897				dmas = <&dmamux1 103 0x400 0x01>;
898				dma-names = "rx";
899				status = "disabled";
900			};
901
902			dfsdm3: filter@3 {
903				compatible = "st,stm32-dfsdm-adc";
904				#io-channel-cells = <1>;
905				reg = <3>;
906				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
907				dmas = <&dmamux1 104 0x400 0x01>;
908				dma-names = "rx";
909				status = "disabled";
910			};
911
912			dfsdm4: filter@4 {
913				compatible = "st,stm32-dfsdm-adc";
914				#io-channel-cells = <1>;
915				reg = <4>;
916				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
917				dmas = <&dmamux1 91 0x400 0x01>;
918				dma-names = "rx";
919				status = "disabled";
920			};
921
922			dfsdm5: filter@5 {
923				compatible = "st,stm32-dfsdm-adc";
924				#io-channel-cells = <1>;
925				reg = <5>;
926				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
927				dmas = <&dmamux1 92 0x400 0x01>;
928				dma-names = "rx";
929				status = "disabled";
930			};
931		};
932
933		m_can1: can@4400e000 {
934			compatible = "bosch,m_can";
935			reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
936			reg-names = "m_can", "message_ram";
937			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
938				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
939			interrupt-names = "int0", "int1";
940			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
941			clock-names = "hclk", "cclk";
942			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
943			status = "disabled";
944		};
945
946		m_can2: can@4400f000 {
947			compatible = "bosch,m_can";
948			reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
949			reg-names = "m_can", "message_ram";
950			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
951				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
952			interrupt-names = "int0", "int1";
953			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
954			clock-names = "hclk", "cclk";
955			bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
956			status = "disabled";
957		};
958
959		dma1: dma@48000000 {
960			compatible = "st,stm32-dma";
961			reg = <0x48000000 0x400>;
962			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
963				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
964				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
965				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
966				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
967				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
968				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
969				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
970			clocks = <&rcc DMA1>;
971			#dma-cells = <4>;
972			st,mem2mem;
973			dma-requests = <8>;
974		};
975
976		dma2: dma@48001000 {
977			compatible = "st,stm32-dma";
978			reg = <0x48001000 0x400>;
979			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
980				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
981				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
982				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
983				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
984				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
985				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
986				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
987			clocks = <&rcc DMA2>;
988			#dma-cells = <4>;
989			st,mem2mem;
990			dma-requests = <8>;
991		};
992
993		dmamux1: dma-router@48002000 {
994			compatible = "st,stm32h7-dmamux";
995			reg = <0x48002000 0x1c>;
996			#dma-cells = <3>;
997			dma-requests = <128>;
998			dma-masters = <&dma1 &dma2>;
999			dma-channels = <16>;
1000			clocks = <&rcc DMAMUX>;
1001		};
1002
1003		adc: adc@48003000 {
1004			compatible = "st,stm32mp1-adc-core";
1005			reg = <0x48003000 0x400>;
1006			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1007				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1008			clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1009			clock-names = "bus", "adc";
1010			interrupt-controller;
1011			st,syscfg = <&syscfg>;
1012			#interrupt-cells = <1>;
1013			#address-cells = <1>;
1014			#size-cells = <0>;
1015			status = "disabled";
1016
1017			adc1: adc@0 {
1018				compatible = "st,stm32mp1-adc";
1019				#io-channel-cells = <1>;
1020				reg = <0x0>;
1021				interrupt-parent = <&adc>;
1022				interrupts = <0>;
1023				dmas = <&dmamux1 9 0x400 0x01>;
1024				dma-names = "rx";
1025				status = "disabled";
1026			};
1027
1028			adc2: adc@100 {
1029				compatible = "st,stm32mp1-adc";
1030				#io-channel-cells = <1>;
1031				reg = <0x100>;
1032				interrupt-parent = <&adc>;
1033				interrupts = <1>;
1034				dmas = <&dmamux1 10 0x400 0x01>;
1035				dma-names = "rx";
1036				status = "disabled";
1037			};
1038		};
1039
1040		sdmmc3: sdmmc@48004000 {
1041			compatible = "arm,pl18x", "arm,primecell";
1042			arm,primecell-periphid = <0x10153180>;
1043			reg = <0x48004000 0x400>;
1044			reg-names = "sdmmc";
1045			interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
1046			clocks = <&rcc SDMMC3_K>;
1047			clock-names = "apb_pclk";
1048			resets = <&rcc SDMMC3_R>;
1049			cap-sd-highspeed;
1050			cap-mmc-highspeed;
1051			max-frequency = <120000000>;
1052			status = "disabled";
1053		};
1054
1055		usbotg_hs: usb-otg@49000000 {
1056			compatible = "snps,dwc2";
1057			reg = <0x49000000 0x10000>;
1058			clocks = <&rcc USBO_K>;
1059			clock-names = "otg";
1060			resets = <&rcc USBO_R>;
1061			reset-names = "dwc2";
1062			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1063			g-rx-fifo-size = <256>;
1064			g-np-tx-fifo-size = <32>;
1065			g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1066			dr_mode = "otg";
1067			usb33d-supply = <&usb33>;
1068			status = "disabled";
1069		};
1070
1071		hwspinlock: hwspinlock@4c000000 {
1072			compatible = "st,stm32-hwspinlock";
1073			#hwlock-cells = <1>;
1074			reg = <0x4c000000 0x400>;
1075			clocks = <&rcc HSEM>;
1076			clock-names = "hwspinlock";
1077		};
1078
1079		ipcc: mailbox@4c001000 {
1080			compatible = "st,stm32mp1-ipcc";
1081			#mbox-cells = <1>;
1082			reg = <0x4c001000 0x400>;
1083			st,proc-id = <0>;
1084			interrupts-extended =
1085				<&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1086				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1087				<&exti 61 1>;
1088			interrupt-names = "rx", "tx", "wakeup";
1089			clocks = <&rcc IPCC>;
1090			wakeup-source;
1091			status = "disabled";
1092		};
1093
1094		dcmi: dcmi@4c006000 {
1095			compatible = "st,stm32-dcmi";
1096			reg = <0x4c006000 0x400>;
1097			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1098			resets = <&rcc CAMITF_R>;
1099			clocks = <&rcc DCMI>;
1100			clock-names = "mclk";
1101			dmas = <&dmamux1 75 0x400 0x0d>;
1102			dma-names = "tx";
1103			status = "disabled";
1104		};
1105
1106		rcc: rcc@50000000 {
1107			compatible = "st,stm32mp1-rcc", "syscon";
1108			reg = <0x50000000 0x1000>;
1109			#clock-cells = <1>;
1110			#reset-cells = <1>;
1111		};
1112
1113		pwr: pwr@50001000 {
1114			compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd";
1115			reg = <0x50001000 0x400>;
1116			system-power-controller;
1117			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1118			st,sysrcc = <&rcc>;
1119			clocks = <&rcc PLL2_R>;
1120			clock-names = "phyclk";
1121
1122			pwr-regulators {
1123				compatible = "st,stm32mp1,pwr-reg";
1124				st,tzcr = <&rcc 0x0 0x1>;
1125
1126				reg11: reg11 {
1127					regulator-name = "reg11";
1128					regulator-min-microvolt = <1100000>;
1129					regulator-max-microvolt = <1100000>;
1130				};
1131
1132				reg18: reg18 {
1133					regulator-name = "reg18";
1134					regulator-min-microvolt = <1800000>;
1135					regulator-max-microvolt = <1800000>;
1136				};
1137
1138				usb33: usb33 {
1139					regulator-name = "usb33";
1140					regulator-min-microvolt = <3300000>;
1141					regulator-max-microvolt = <3300000>;
1142				};
1143			};
1144		};
1145
1146		exti: interrupt-controller@5000d000 {
1147			compatible = "st,stm32mp1-exti", "syscon";
1148			interrupt-controller;
1149			#interrupt-cells = <2>;
1150			reg = <0x5000d000 0x400>;
1151		};
1152
1153		syscfg: syscon@50020000 {
1154			compatible = "st,stm32mp157-syscfg", "syscon";
1155			reg = <0x50020000 0x400>;
1156			clocks = <&rcc SYSCFG>;
1157		};
1158
1159		lptimer2: timer@50021000 {
1160			#address-cells = <1>;
1161			#size-cells = <0>;
1162			compatible = "st,stm32-lptimer";
1163			reg = <0x50021000 0x400>;
1164			clocks = <&rcc LPTIM2_K>;
1165			clock-names = "mux";
1166			status = "disabled";
1167
1168			pwm {
1169				compatible = "st,stm32-pwm-lp";
1170				#pwm-cells = <3>;
1171				status = "disabled";
1172			};
1173
1174			trigger@1 {
1175				compatible = "st,stm32-lptimer-trigger";
1176				reg = <1>;
1177				status = "disabled";
1178			};
1179
1180			counter {
1181				compatible = "st,stm32-lptimer-counter";
1182				status = "disabled";
1183			};
1184		};
1185
1186		lptimer3: timer@50022000 {
1187			#address-cells = <1>;
1188			#size-cells = <0>;
1189			compatible = "st,stm32-lptimer";
1190			reg = <0x50022000 0x400>;
1191			clocks = <&rcc LPTIM3_K>;
1192			clock-names = "mux";
1193			status = "disabled";
1194
1195			pwm {
1196				compatible = "st,stm32-pwm-lp";
1197				#pwm-cells = <3>;
1198				status = "disabled";
1199			};
1200
1201			trigger@2 {
1202				compatible = "st,stm32-lptimer-trigger";
1203				reg = <2>;
1204				status = "disabled";
1205			};
1206		};
1207
1208		lptimer4: timer@50023000 {
1209			compatible = "st,stm32-lptimer";
1210			reg = <0x50023000 0x400>;
1211			clocks = <&rcc LPTIM4_K>;
1212			clock-names = "mux";
1213			status = "disabled";
1214
1215			pwm {
1216				compatible = "st,stm32-pwm-lp";
1217				#pwm-cells = <3>;
1218				status = "disabled";
1219			};
1220		};
1221
1222		lptimer5: timer@50024000 {
1223			compatible = "st,stm32-lptimer";
1224			reg = <0x50024000 0x400>;
1225			clocks = <&rcc LPTIM5_K>;
1226			clock-names = "mux";
1227			status = "disabled";
1228
1229			pwm {
1230				compatible = "st,stm32-pwm-lp";
1231				#pwm-cells = <3>;
1232				status = "disabled";
1233			};
1234		};
1235
1236		vrefbuf: vrefbuf@50025000 {
1237			compatible = "st,stm32-vrefbuf";
1238			reg = <0x50025000 0x8>;
1239			regulator-min-microvolt = <1500000>;
1240			regulator-max-microvolt = <2500000>;
1241			clocks = <&rcc VREF>;
1242			status = "disabled";
1243		};
1244
1245		sai4: sai@50027000 {
1246			compatible = "st,stm32h7-sai";
1247			#address-cells = <1>;
1248			#size-cells = <1>;
1249			ranges = <0 0x50027000 0x400>;
1250			reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1251			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1252			resets = <&rcc SAI4_R>;
1253			status = "disabled";
1254
1255			sai4a: audio-controller@50027004 {
1256				#sound-dai-cells = <0>;
1257				compatible = "st,stm32-sai-sub-a";
1258				reg = <0x04 0x1c>;
1259				clocks = <&rcc SAI4_K>;
1260				clock-names = "sai_ck";
1261				dmas = <&dmamux1 99 0x400 0x01>;
1262				status = "disabled";
1263			};
1264
1265			sai4b: audio-controller@50027024 {
1266				#sound-dai-cells = <0>;
1267				compatible = "st,stm32-sai-sub-b";
1268				reg = <0x24 0x1c>;
1269				clocks = <&rcc SAI4_K>;
1270				clock-names = "sai_ck";
1271				dmas = <&dmamux1 100 0x400 0x01>;
1272				status = "disabled";
1273			};
1274		};
1275
1276		dts: thermal@50028000 {
1277			compatible = "st,stm32-thermal";
1278			reg = <0x50028000 0x100>;
1279			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1280			clocks = <&rcc TMPSENS>;
1281			clock-names = "pclk";
1282			#thermal-sensor-cells = <0>;
1283			status = "disabled";
1284		};
1285
1286		cryp1: cryp@54001000 {
1287			compatible = "st,stm32mp1-cryp";
1288			reg = <0x54001000 0x400>;
1289			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1290			clocks = <&rcc CRYP1>;
1291			resets = <&rcc CRYP1_R>;
1292			status = "disabled";
1293		};
1294
1295		hash1: hash@54002000 {
1296			compatible = "st,stm32f756-hash";
1297			reg = <0x54002000 0x400>;
1298			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1299			clocks = <&rcc HASH1>;
1300			resets = <&rcc HASH1_R>;
1301			dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1302			dma-names = "in";
1303			dma-maxburst = <2>;
1304			status = "disabled";
1305		};
1306
1307		rng1: rng@54003000 {
1308			compatible = "st,stm32-rng";
1309			reg = <0x54003000 0x400>;
1310			clocks = <&rcc RNG1_K>;
1311			resets = <&rcc RNG1_R>;
1312			status = "disabled";
1313		};
1314
1315		mdma1: dma@58000000 {
1316			compatible = "st,stm32h7-mdma";
1317			reg = <0x58000000 0x1000>;
1318			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1319			clocks = <&rcc MDMA>;
1320			#dma-cells = <5>;
1321			dma-channels = <32>;
1322			dma-requests = <48>;
1323		};
1324
1325		fmc: nand-controller@58002000 {
1326			compatible = "st,stm32mp15-fmc2";
1327			reg = <0x58002000 0x1000>,
1328			      <0x80000000 0x1000>,
1329			      <0x88010000 0x1000>,
1330			      <0x88020000 0x1000>,
1331			      <0x81000000 0x1000>,
1332			      <0x89010000 0x1000>,
1333			      <0x89020000 0x1000>;
1334			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1335			dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
1336			       <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
1337			       <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
1338			dma-names = "tx", "rx", "ecc";
1339			clocks = <&rcc FMC_K>;
1340			resets = <&rcc FMC_R>;
1341			status = "disabled";
1342		};
1343
1344		qspi: spi@58003000 {
1345			compatible = "st,stm32f469-qspi";
1346			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1347			reg-names = "qspi", "qspi_mm";
1348			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1349			dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1350			       <&mdma1 22 0x10 0x100008 0x0 0x0>;
1351			dma-names = "tx", "rx";
1352			clocks = <&rcc QSPI_K>;
1353			resets = <&rcc QSPI_R>;
1354			status = "disabled";
1355		};
1356
1357		sdmmc1: sdmmc@58005000 {
1358			compatible = "arm,pl18x", "arm,primecell";
1359			arm,primecell-periphid = <0x10153180>;
1360			reg = <0x58005000 0x1000>;
1361			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1362			interrupt-names	= "cmd_irq";
1363			clocks = <&rcc SDMMC1_K>;
1364			clock-names = "apb_pclk";
1365			resets = <&rcc SDMMC1_R>;
1366			cap-sd-highspeed;
1367			cap-mmc-highspeed;
1368			max-frequency = <120000000>;
1369		};
1370
1371		sdmmc2: sdmmc@58007000 {
1372			compatible = "arm,pl18x", "arm,primecell";
1373			arm,primecell-periphid = <0x10153180>;
1374			reg = <0x58007000 0x1000>;
1375			interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
1376			clocks = <&rcc SDMMC2_K>;
1377			clock-names = "apb_pclk";
1378			resets = <&rcc SDMMC2_R>;
1379			cap-sd-highspeed;
1380			cap-mmc-highspeed;
1381			max-frequency = <120000000>;
1382			status = "disabled";
1383		};
1384
1385		crc1: crc@58009000 {
1386			compatible = "st,stm32f7-crc";
1387			reg = <0x58009000 0x400>;
1388			clocks = <&rcc CRC1>;
1389			status = "disabled";
1390		};
1391
1392		stmmac_axi_config_0: stmmac-axi-config {
1393			snps,wr_osr_lmt = <0x7>;
1394			snps,rd_osr_lmt = <0x7>;
1395			snps,blen = <0 0 0 0 16 8 4>;
1396		};
1397
1398		ethernet0: ethernet@5800a000 {
1399			compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1400			reg = <0x5800a000 0x2000>;
1401			reg-names = "stmmaceth";
1402			interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1403			interrupt-names = "macirq";
1404			clock-names = "stmmaceth",
1405				      "mac-clk-tx",
1406				      "mac-clk-rx",
1407				      "ethstp",
1408				      "syscfg-clk";
1409			clocks = <&rcc ETHMAC>,
1410				 <&rcc ETHTX>,
1411				 <&rcc ETHRX>,
1412				 <&rcc ETHSTP>,
1413				 <&rcc SYSCFG>;
1414			st,syscon = <&syscfg 0x4>;
1415			snps,mixed-burst;
1416			snps,pbl = <2>;
1417			snps,axi-config = <&stmmac_axi_config_0>;
1418			snps,tso;
1419			status = "disabled";
1420		};
1421
1422		usbh_ohci: usbh-ohci@5800c000 {
1423			compatible = "generic-ohci";
1424			reg = <0x5800c000 0x1000>;
1425			clocks = <&rcc USBH>;
1426			resets = <&rcc USBH_R>;
1427			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1428			status = "disabled";
1429		};
1430
1431		usbh_ehci: usbh-ehci@5800d000 {
1432			compatible = "generic-ehci";
1433			reg = <0x5800d000 0x1000>;
1434			clocks = <&rcc USBH>;
1435			resets = <&rcc USBH_R>;
1436			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1437			companion = <&usbh_ohci>;
1438			status = "disabled";
1439		};
1440
1441		gpu: gpu@59000000 {
1442			compatible = "vivante,gc";
1443			reg = <0x59000000 0x800>;
1444			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1445			clocks = <&rcc GPU>, <&rcc GPU_K>;
1446			clock-names = "bus" ,"core";
1447			resets = <&rcc GPU_R>;
1448			status = "disabled";
1449		};
1450
1451		dsi: dsi@5a000000 {
1452			compatible = "st,stm32-dsi";
1453			reg = <0x5a000000 0x800>;
1454			clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
1455			clock-names = "pclk", "ref", "px_clk";
1456			resets = <&rcc DSI_R>;
1457			reset-names = "apb";
1458			status = "disabled";
1459		};
1460
1461		ltdc: display-controller@5a001000 {
1462			compatible = "st,stm32-ltdc";
1463			reg = <0x5a001000 0x400>;
1464			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1465				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1466			clocks = <&rcc LTDC_PX>;
1467			clock-names = "lcd";
1468			resets = <&rcc LTDC_R>;
1469			status = "disabled";
1470		};
1471
1472		iwdg2: watchdog@5a002000 {
1473			compatible = "st,stm32mp1-iwdg";
1474			reg = <0x5a002000 0x400>;
1475			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1476			clock-names = "pclk", "lsi";
1477			status = "disabled";
1478		};
1479
1480		usbphyc: usbphyc@5a006000 {
1481			#address-cells = <1>;
1482			#size-cells = <0>;
1483			compatible = "st,stm32mp1-usbphyc";
1484			reg = <0x5a006000 0x1000>;
1485			clocks = <&rcc USBPHY_K>;
1486			resets = <&rcc USBPHY_R>;
1487			vdda1v1-supply = <&reg11>;
1488			vdda1v8-supply = <&reg18>;
1489			status = "disabled";
1490
1491			usbphyc_port0: usb-phy@0 {
1492				#phy-cells = <0>;
1493				reg = <0>;
1494			};
1495
1496			usbphyc_port1: usb-phy@1 {
1497				#phy-cells = <1>;
1498				reg = <1>;
1499			};
1500		};
1501
1502		usart1: serial@5c000000 {
1503			compatible = "st,stm32h7-uart";
1504			reg = <0x5c000000 0x400>;
1505			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1506			clocks = <&rcc USART1_K>;
1507			status = "disabled";
1508		};
1509
1510		spi6: spi@5c001000 {
1511			#address-cells = <1>;
1512			#size-cells = <0>;
1513			compatible = "st,stm32h7-spi";
1514			reg = <0x5c001000 0x400>;
1515			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1516			clocks = <&rcc SPI6_K>;
1517			resets = <&rcc SPI6_R>;
1518			dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1519			       <&mdma1 35 0x0 0x40002 0x0 0x0>;
1520			dma-names = "rx", "tx";
1521			status = "disabled";
1522		};
1523
1524		i2c4: i2c@5c002000 {
1525			compatible = "st,stm32f7-i2c";
1526			reg = <0x5c002000 0x400>;
1527			interrupt-names = "event", "error";
1528			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1529				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1530			clocks = <&rcc I2C4_K>;
1531			resets = <&rcc I2C4_R>;
1532			#address-cells = <1>;
1533			#size-cells = <0>;
1534			status = "disabled";
1535		};
1536
1537		rtc: rtc@5c004000 {
1538			compatible = "st,stm32mp1-rtc";
1539			reg = <0x5c004000 0x400>;
1540			clocks = <&rcc RTCAPB>, <&rcc RTC>;
1541			clock-names = "pclk", "rtc_ck";
1542			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1543			status = "disabled";
1544		};
1545
1546		bsec: nvmem@5c005000 {
1547			compatible = "st,stm32mp15-bsec";
1548			reg = <0x5c005000 0x400>;
1549			#address-cells = <1>;
1550			#size-cells = <1>;
1551			ts_cal1: calib@5c {
1552				reg = <0x5c 0x2>;
1553			};
1554			ts_cal2: calib@5e {
1555				reg = <0x5e 0x2>;
1556			};
1557		};
1558
1559		i2c6: i2c@5c009000 {
1560			compatible = "st,stm32f7-i2c";
1561			reg = <0x5c009000 0x400>;
1562			interrupt-names = "event", "error";
1563			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1564				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1565			clocks = <&rcc I2C6_K>;
1566			resets = <&rcc I2C6_R>;
1567			#address-cells = <1>;
1568			#size-cells = <0>;
1569			status = "disabled";
1570		};
1571	};
1572
1573	mlahb {
1574		compatible = "simple-bus";
1575		#address-cells = <1>;
1576		#size-cells = <1>;
1577		dma-ranges = <0x00000000 0x38000000 0x10000>,
1578			     <0x10000000 0x10000000 0x60000>,
1579			     <0x30000000 0x30000000 0x60000>;
1580
1581		m4_rproc: m4@10000000 {
1582			compatible = "st,stm32mp1-m4";
1583			reg = <0x10000000 0x40000>,
1584			      <0x30000000 0x40000>,
1585			      <0x38000000 0x10000>;
1586			resets = <&rcc MCU_R>;
1587			st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1588			st,syscfg-tz = <&rcc 0x000 0x1>;
1589			status = "disabled";
1590		};
1591	};
1592};
1593