1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ARM Ltd. Versatile Express 4 * 5 * Motherboard Express uATX 6 * V2M-P1 7 * 8 * HBI-0190D 9 * 10 * Original memory map ("Legacy memory map" in the board's 11 * Technical Reference Manual) 12 * 13 * WARNING! The hardware described in this file is independent from the 14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong 15 * correspondence between the two configurations. 16 * 17 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT 18 * CHANGES TO vexpress-v2m-rs1.dtsi! 19 */ 20 21/ { 22 smb@4000000 { 23 motherboard { 24 model = "V2M-P1"; 25 arm,hbi = <0x190>; 26 arm,vexpress,site = <0>; 27 compatible = "arm,vexpress,v2m-p1", "simple-bus"; 28 #address-cells = <2>; /* SMB chipselect number and offset */ 29 #size-cells = <1>; 30 #interrupt-cells = <1>; 31 ranges; 32 33 flash@0,00000000 { 34 compatible = "arm,vexpress-flash", "cfi-flash"; 35 reg = <0 0x00000000 0x04000000>, 36 <1 0x00000000 0x04000000>; 37 bank-width = <4>; 38 }; 39 40 psram@2,00000000 { 41 compatible = "arm,vexpress-psram", "mtd-ram"; 42 reg = <2 0x00000000 0x02000000>; 43 bank-width = <4>; 44 }; 45 46 ethernet@3,02000000 { 47 compatible = "smsc,lan9118", "smsc,lan9115"; 48 reg = <3 0x02000000 0x10000>; 49 interrupts = <15>; 50 phy-mode = "mii"; 51 reg-io-width = <4>; 52 smsc,irq-active-high; 53 smsc,irq-push-pull; 54 vdd33a-supply = <&v2m_fixed_3v3>; 55 vddvario-supply = <&v2m_fixed_3v3>; 56 }; 57 58 usb@3,03000000 { 59 compatible = "nxp,usb-isp1761"; 60 reg = <3 0x03000000 0x20000>; 61 interrupts = <16>; 62 port1-otg; 63 }; 64 65 iofpga@7,00000000 { 66 compatible = "simple-bus"; 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges = <0 7 0 0x20000>; 70 71 v2m_sysreg: sysreg@0 { 72 compatible = "arm,vexpress-sysreg"; 73 reg = <0x00000 0x1000>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges = <0 0 0x1000>; 77 78 v2m_led_gpios: gpio@8 { 79 compatible = "arm,vexpress-sysreg,sys_led"; 80 reg = <0x008 4>; 81 gpio-controller; 82 #gpio-cells = <2>; 83 }; 84 85 v2m_mmc_gpios: gpio@48 { 86 compatible = "arm,vexpress-sysreg,sys_mci"; 87 reg = <0x048 4>; 88 gpio-controller; 89 #gpio-cells = <2>; 90 }; 91 92 v2m_flash_gpios: gpio@4c { 93 compatible = "arm,vexpress-sysreg,sys_flash"; 94 reg = <0x04c 4>; 95 gpio-controller; 96 #gpio-cells = <2>; 97 }; 98 }; 99 100 v2m_sysctl: sysctl@1000 { 101 compatible = "arm,sp810", "arm,primecell"; 102 reg = <0x01000 0x1000>; 103 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; 104 clock-names = "refclk", "timclk", "apb_pclk"; 105 #clock-cells = <1>; 106 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; 107 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; 108 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; 109 }; 110 111 /* PCI-E I2C bus */ 112 v2m_i2c_pcie: i2c@2000 { 113 compatible = "arm,versatile-i2c"; 114 reg = <0x02000 0x1000>; 115 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 pcie-switch@60 { 120 compatible = "idt,89hpes32h8"; 121 reg = <0x60>; 122 }; 123 }; 124 125 aaci@4000 { 126 compatible = "arm,pl041", "arm,primecell"; 127 reg = <0x04000 0x1000>; 128 interrupts = <11>; 129 clocks = <&smbclk>; 130 clock-names = "apb_pclk"; 131 }; 132 133 mmci@5000 { 134 compatible = "arm,pl180", "arm,primecell"; 135 reg = <0x05000 0x1000>; 136 interrupts = <9>, <10>; 137 cd-gpios = <&v2m_mmc_gpios 0 0>; 138 wp-gpios = <&v2m_mmc_gpios 1 0>; 139 max-frequency = <12000000>; 140 vmmc-supply = <&v2m_fixed_3v3>; 141 clocks = <&v2m_clk24mhz>, <&smbclk>; 142 clock-names = "mclk", "apb_pclk"; 143 }; 144 145 kmi@6000 { 146 compatible = "arm,pl050", "arm,primecell"; 147 reg = <0x06000 0x1000>; 148 interrupts = <12>; 149 clocks = <&v2m_clk24mhz>, <&smbclk>; 150 clock-names = "KMIREFCLK", "apb_pclk"; 151 }; 152 153 kmi@7000 { 154 compatible = "arm,pl050", "arm,primecell"; 155 reg = <0x07000 0x1000>; 156 interrupts = <13>; 157 clocks = <&v2m_clk24mhz>, <&smbclk>; 158 clock-names = "KMIREFCLK", "apb_pclk"; 159 }; 160 161 v2m_serial0: uart@9000 { 162 compatible = "arm,pl011", "arm,primecell"; 163 reg = <0x09000 0x1000>; 164 interrupts = <5>; 165 clocks = <&v2m_oscclk2>, <&smbclk>; 166 clock-names = "uartclk", "apb_pclk"; 167 }; 168 169 v2m_serial1: uart@a000 { 170 compatible = "arm,pl011", "arm,primecell"; 171 reg = <0x0a000 0x1000>; 172 interrupts = <6>; 173 clocks = <&v2m_oscclk2>, <&smbclk>; 174 clock-names = "uartclk", "apb_pclk"; 175 }; 176 177 v2m_serial2: uart@b000 { 178 compatible = "arm,pl011", "arm,primecell"; 179 reg = <0x0b000 0x1000>; 180 interrupts = <7>; 181 clocks = <&v2m_oscclk2>, <&smbclk>; 182 clock-names = "uartclk", "apb_pclk"; 183 }; 184 185 v2m_serial3: uart@c000 { 186 compatible = "arm,pl011", "arm,primecell"; 187 reg = <0x0c000 0x1000>; 188 interrupts = <8>; 189 clocks = <&v2m_oscclk2>, <&smbclk>; 190 clock-names = "uartclk", "apb_pclk"; 191 }; 192 193 wdt@f000 { 194 compatible = "arm,sp805", "arm,primecell"; 195 reg = <0x0f000 0x1000>; 196 interrupts = <0>; 197 clocks = <&v2m_refclk32khz>, <&smbclk>; 198 clock-names = "wdogclk", "apb_pclk"; 199 }; 200 201 v2m_timer01: timer@11000 { 202 compatible = "arm,sp804", "arm,primecell"; 203 reg = <0x11000 0x1000>; 204 interrupts = <2>; 205 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; 206 clock-names = "timclken1", "timclken2", "apb_pclk"; 207 }; 208 209 v2m_timer23: timer@12000 { 210 compatible = "arm,sp804", "arm,primecell"; 211 reg = <0x12000 0x1000>; 212 interrupts = <3>; 213 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; 214 clock-names = "timclken1", "timclken2", "apb_pclk"; 215 }; 216 217 /* DVI I2C bus */ 218 v2m_i2c_dvi: i2c@16000 { 219 compatible = "arm,versatile-i2c"; 220 reg = <0x16000 0x1000>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 224 dvi-transmitter@39 { 225 compatible = "sil,sii9022-tpi", "sil,sii9022"; 226 reg = <0x39>; 227 228 ports { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 232 /* 233 * Both the core tile and the motherboard routes their output 234 * pads to this transmitter. The motherboard system controller 235 * can select one of them as input using a mux register in 236 * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is 237 * the only platform with this specific set-up. 238 */ 239 port@0 { 240 reg = <0>; 241 dvi_bridge_in_ct: endpoint { 242 remote-endpoint = <&clcd_pads_ct>; 243 }; 244 }; 245 port@1 { 246 reg = <1>; 247 dvi_bridge_in_mb: endpoint { 248 remote-endpoint = <&clcd_pads_mb>; 249 }; 250 }; 251 }; 252 }; 253 254 dvi-transmitter@60 { 255 compatible = "sil,sii9022-cpi", "sil,sii9022"; 256 reg = <0x60>; 257 }; 258 }; 259 260 rtc@17000 { 261 compatible = "arm,pl031", "arm,primecell"; 262 reg = <0x17000 0x1000>; 263 interrupts = <4>; 264 clocks = <&smbclk>; 265 clock-names = "apb_pclk"; 266 }; 267 268 compact-flash@1a000 { 269 compatible = "arm,vexpress-cf", "ata-generic"; 270 reg = <0x1a000 0x100 271 0x1a100 0xf00>; 272 reg-shift = <2>; 273 }; 274 275 276 clcd@1f000 { 277 compatible = "arm,pl111", "arm,primecell"; 278 reg = <0x1f000 0x1000>; 279 interrupt-names = "combined"; 280 interrupts = <14>; 281 clocks = <&v2m_oscclk1>, <&smbclk>; 282 clock-names = "clcdclk", "apb_pclk"; 283 /* 800x600 16bpp @36MHz works fine */ 284 max-memory-bandwidth = <54000000>; 285 memory-region = <&vram>; 286 287 port { 288 clcd_pads_mb: endpoint { 289 remote-endpoint = <&dvi_bridge_in_mb>; 290 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 291 }; 292 }; 293 }; 294 }; 295 296 v2m_fixed_3v3: fixed-regulator-0 { 297 compatible = "regulator-fixed"; 298 regulator-name = "3V3"; 299 regulator-min-microvolt = <3300000>; 300 regulator-max-microvolt = <3300000>; 301 regulator-always-on; 302 }; 303 304 v2m_clk24mhz: clk24mhz { 305 compatible = "fixed-clock"; 306 #clock-cells = <0>; 307 clock-frequency = <24000000>; 308 clock-output-names = "v2m:clk24mhz"; 309 }; 310 311 v2m_refclk1mhz: refclk1mhz { 312 compatible = "fixed-clock"; 313 #clock-cells = <0>; 314 clock-frequency = <1000000>; 315 clock-output-names = "v2m:refclk1mhz"; 316 }; 317 318 v2m_refclk32khz: refclk32khz { 319 compatible = "fixed-clock"; 320 #clock-cells = <0>; 321 clock-frequency = <32768>; 322 clock-output-names = "v2m:refclk32khz"; 323 }; 324 325 leds { 326 compatible = "gpio-leds"; 327 328 user1 { 329 label = "v2m:green:user1"; 330 gpios = <&v2m_led_gpios 0 0>; 331 linux,default-trigger = "heartbeat"; 332 }; 333 334 user2 { 335 label = "v2m:green:user2"; 336 gpios = <&v2m_led_gpios 1 0>; 337 linux,default-trigger = "mmc0"; 338 }; 339 340 user3 { 341 label = "v2m:green:user3"; 342 gpios = <&v2m_led_gpios 2 0>; 343 linux,default-trigger = "cpu0"; 344 }; 345 346 user4 { 347 label = "v2m:green:user4"; 348 gpios = <&v2m_led_gpios 3 0>; 349 linux,default-trigger = "cpu1"; 350 }; 351 352 user5 { 353 label = "v2m:green:user5"; 354 gpios = <&v2m_led_gpios 4 0>; 355 linux,default-trigger = "cpu2"; 356 }; 357 358 user6 { 359 label = "v2m:green:user6"; 360 gpios = <&v2m_led_gpios 5 0>; 361 linux,default-trigger = "cpu3"; 362 }; 363 364 user7 { 365 label = "v2m:green:user7"; 366 gpios = <&v2m_led_gpios 6 0>; 367 linux,default-trigger = "cpu4"; 368 }; 369 370 user8 { 371 label = "v2m:green:user8"; 372 gpios = <&v2m_led_gpios 7 0>; 373 linux,default-trigger = "cpu5"; 374 }; 375 }; 376 377 mcc { 378 compatible = "arm,vexpress,config-bus"; 379 arm,vexpress,config-bridge = <&v2m_sysreg>; 380 381 oscclk0 { 382 /* MCC static memory clock */ 383 compatible = "arm,vexpress-osc"; 384 arm,vexpress-sysreg,func = <1 0>; 385 freq-range = <25000000 60000000>; 386 #clock-cells = <0>; 387 clock-output-names = "v2m:oscclk0"; 388 }; 389 390 v2m_oscclk1: oscclk1 { 391 /* CLCD clock */ 392 compatible = "arm,vexpress-osc"; 393 arm,vexpress-sysreg,func = <1 1>; 394 freq-range = <23750000 65000000>; 395 #clock-cells = <0>; 396 clock-output-names = "v2m:oscclk1"; 397 }; 398 399 v2m_oscclk2: oscclk2 { 400 /* IO FPGA peripheral clock */ 401 compatible = "arm,vexpress-osc"; 402 arm,vexpress-sysreg,func = <1 2>; 403 freq-range = <24000000 24000000>; 404 #clock-cells = <0>; 405 clock-output-names = "v2m:oscclk2"; 406 }; 407 408 volt-vio { 409 /* Logic level voltage */ 410 compatible = "arm,vexpress-volt"; 411 arm,vexpress-sysreg,func = <2 0>; 412 regulator-name = "VIO"; 413 regulator-always-on; 414 label = "VIO"; 415 }; 416 417 temp-mcc { 418 /* MCC internal operating temperature */ 419 compatible = "arm,vexpress-temp"; 420 arm,vexpress-sysreg,func = <4 0>; 421 label = "MCC"; 422 }; 423 424 reset { 425 compatible = "arm,vexpress-reset"; 426 arm,vexpress-sysreg,func = <5 0>; 427 }; 428 429 muxfpga { 430 compatible = "arm,vexpress-muxfpga"; 431 arm,vexpress-sysreg,func = <7 0>; 432 }; 433 434 shutdown { 435 compatible = "arm,vexpress-shutdown"; 436 arm,vexpress-sysreg,func = <8 0>; 437 }; 438 439 reboot { 440 compatible = "arm,vexpress-reboot"; 441 arm,vexpress-sysreg,func = <9 0>; 442 }; 443 444 dvimode { 445 compatible = "arm,vexpress-dvimode"; 446 arm,vexpress-sysreg,func = <11 0>; 447 }; 448 }; 449 }; 450 }; 451};