1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2018 Xilinx, Inc. 4 * 5 * Michal Simek <michal.simek@xilinx.com> 6 */ 7/dts-v1/; 8#include "zynq-7000.dtsi" 9 10/ { 11 model = "Zynq DLC20 Rev1.0"; 12 compatible = "xlnx,zynq-dlc20-rev1.0", "xlnx,zynq-dlc20", 13 "xlnx,zynq-7000"; 14 15 aliases { 16 ethernet0 = &gem0; 17 i2c0 = &i2c0; 18 serial0 = &uart1; 19 spi0 = &qspi; 20 mmc0 = &sdhci0; 21 }; 22 23 memory@0 { 24 device_type = "memory"; 25 reg = <0x0 0x20000000>; 26 }; 27 28 chosen { 29 bootargs = "earlyprintk"; 30 stdout-path = "serial0:115200n8"; 31 }; 32 33 usb_phy0: phy0@e0002000 { 34 compatible = "ulpi-phy"; 35 #phy-cells = <0>; 36 reg = <0xe0002000 0x1000>; 37 view-port = <0x0170>; 38 drv-vbus; 39 }; 40}; 41 42&clkc { 43 ps-clk-frequency = <33333333>; /* U7 */ 44}; 45 46&gem0 { 47 status = "okay"; /* MIO16-MIO27, MDIO MIO52/53 */ 48 phy-mode = "rgmii-id"; 49 phy-handle = <ðernet_phy>; 50 51 ethernet_phy: ethernet-phy@7 { /* rtl8211e - U25 */ 52 reg = <1>; 53 }; 54}; 55 56&i2c0 { 57 status = "okay"; /* MIO14/15 */ 58 clock-frequency = <400000>; 59 /* U46 - m24c08 */ 60 eeprom: eeprom@54 { 61 compatible = "atmel,24c08"; 62 reg = <0x54>; 63 }; 64}; 65 66&qspi { 67 u-boot,dm-pre-reloc; 68 status = "okay"; 69 is-dual = <0>; 70 num-cs = <1>; 71 spi-tx-bus-width = <4>; 72 spi-rx-bus-width = <4>; 73 flash@0 { 74 /* Rev1.0 W25Q128FWSIG, RevC N25Q128A */ 75 compatible = "n25q128a11", "jedec,spi-nor"; 76 reg = <0x0>; 77 spi-tx-bus-width = <1>; 78 spi-rx-bus-width = <4>; 79 spi-max-frequency = <50000000>; 80 }; 81}; 82 83&sdhci0 { 84 u-boot,dm-pre-reloc; 85 status = "okay"; /* EMMC MTFC4GACAJCN - MIO40-MIO45 */ 86 non-removable; 87 bus-width = <4>; 88}; 89 90&uart1 { 91 u-boot,dm-pre-reloc; 92 status = "okay"; /* MIO8/9 */ 93}; 94 95&usb0 { 96 status = "okay"; /* MIO28-MIO39 */ 97 dr_mode = "device"; 98 usb-phy = <&usb_phy0>; 99}; 100 101&watchdog0 { 102 reset-on-timeout; 103}; 104