1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU104 4 * 5 * (C) Copyright 2017 - 2018, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/phy/phy.h> 16 17/ { 18 model = "ZynqMP ZCU104 RevA"; 19 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; 20 21 aliases { 22 ethernet0 = &gem3; 23 gpio0 = &gpio; 24 i2c0 = &i2c1; 25 mmc0 = &sdhci1; 26 rtc0 = &rtc; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &dcc; 30 spi0 = &qspi; 31 usb0 = &usb0; 32 }; 33 34 chosen { 35 bootargs = "earlycon"; 36 stdout-path = "serial0:115200n8"; 37 }; 38 39 memory@0 { 40 device_type = "memory"; 41 reg = <0x0 0x0 0x0 0x80000000>; 42 }; 43}; 44 45&can1 { 46 status = "okay"; 47}; 48 49&dcc { 50 status = "okay"; 51}; 52 53&fpd_dma_chan1 { 54 status = "okay"; 55}; 56 57&fpd_dma_chan2 { 58 status = "okay"; 59}; 60 61&fpd_dma_chan3 { 62 status = "okay"; 63}; 64 65&fpd_dma_chan4 { 66 status = "okay"; 67}; 68 69&fpd_dma_chan5 { 70 status = "okay"; 71}; 72 73&fpd_dma_chan6 { 74 status = "okay"; 75}; 76 77&fpd_dma_chan7 { 78 status = "okay"; 79}; 80 81&fpd_dma_chan8 { 82 status = "okay"; 83}; 84 85&gem3 { 86 status = "okay"; 87 phy-handle = <&phy0>; 88 phy-mode = "rgmii-id"; 89 phy0: ethernet-phy@c { 90 reg = <0xc>; 91 ti,rx-internal-delay = <0x8>; 92 ti,tx-internal-delay = <0xa>; 93 ti,fifo-depth = <0x1>; 94 ti,dp83867-rxctrl-strap-quirk; 95 }; 96}; 97 98&gpio { 99 status = "okay"; 100}; 101 102&gpu { 103 status = "okay"; 104}; 105 106&i2c1 { 107 status = "okay"; 108 clock-frequency = <400000>; 109 110 /* Another connection to this bus via PL i2c via PCA9306 - u45 */ 111 i2c-mux@74 { /* u34 */ 112 compatible = "nxp,pca9548"; 113 #address-cells = <1>; 114 #size-cells = <0>; 115 reg = <0x74>; 116 i2c@0 { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 reg = <0>; 120 /* 121 * IIC_EEPROM 1kB memory which uses 256B blocks 122 * where every block has different address. 123 * 0 - 256B address 0x54 124 * 256B - 512B address 0x55 125 * 512B - 768B address 0x56 126 * 768B - 1024B address 0x57 127 */ 128 eeprom: eeprom@54 { /* u23 */ 129 compatible = "atmel,24c08"; 130 reg = <0x54>; 131 #address-cells = <1>; 132 #size-cells = <1>; 133 }; 134 }; 135 136 i2c@1 { 137 #address-cells = <1>; 138 #size-cells = <0>; 139 reg = <1>; 140 clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ 141 compatible = "idt,8t49n287"; 142 reg = <0x6c>; 143 }; 144 }; 145 146 i2c@2 { 147 #address-cells = <1>; 148 #size-cells = <0>; 149 reg = <2>; 150 irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ 151 #clock-cells = <0>; 152 compatible = "infineon,irps5401"; 153 reg = <0x43>; 154 }; 155 irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ 156 #clock-cells = <0>; 157 compatible = "infineon,irps5401"; 158 reg = <0x4d>; 159 }; 160 }; 161 162 i2c@4 { 163 #address-cells = <1>; 164 #size-cells = <0>; 165 reg = <4>; 166 tca6416_u97: gpio@20 { 167 compatible = "ti,tca6416"; 168 reg = <0x20>; 169 gpio-controller; 170 #gpio-cells = <2>; 171 /* 172 * IRQ not connected 173 * Lines: 174 * 0 - IRPS5401_ALERT_B 175 * 1 - HDMI_8T49N241_INT_ALM 176 * 2 - MAX6643_OT_B 177 * 3 - MAX6643_FANFAIL_B 178 * 5 - IIC_MUX_RESET_B 179 * 6 - GEM3_EXP_RESET_B 180 * 7 - FMC_LPC_PRSNT_M2C_B 181 * 4, 10 - 17 - not connected 182 */ 183 }; 184 }; 185 186 i2c@5 { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 reg = <5>; 190 }; 191 192 i2c@7 { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 reg = <7>; 196 }; 197 198 /* 3, 6 not connected */ 199 }; 200}; 201 202&qspi { 203 status = "okay"; 204 flash@0 { 205 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ 206 #address-cells = <1>; 207 #size-cells = <1>; 208 reg = <0x0>; 209 spi-tx-bus-width = <1>; 210 spi-rx-bus-width = <4>; 211 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 212 partition@qspi-fsbl-uboot { /* for testing purpose */ 213 label = "qspi-fsbl-uboot"; 214 reg = <0x0 0x100000>; 215 }; 216 partition@qspi-linux { /* for testing purpose */ 217 label = "qspi-linux"; 218 reg = <0x100000 0x500000>; 219 }; 220 partition@qspi-device-tree { /* for testing purpose */ 221 label = "qspi-device-tree"; 222 reg = <0x600000 0x20000>; 223 }; 224 partition@qspi-rootfs { /* for testing purpose */ 225 label = "qspi-rootfs"; 226 reg = <0x620000 0x5E0000>; 227 }; 228 }; 229}; 230 231&rtc { 232 status = "okay"; 233}; 234 235&sata { 236 status = "okay"; 237 /* SATA OOB timing settings */ 238 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 239 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 240 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 241 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 242 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 243 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 244 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 245 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 246 phy-names = "sata-phy"; 247 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; 248}; 249 250/* SD1 with level shifter */ 251&sdhci1 { 252 status = "okay"; 253 no-1-8-v; 254 xlnx,mio_bank = <1>; 255 disable-wp; 256}; 257 258&serdes { 259 status = "okay"; 260}; 261 262&uart0 { 263 status = "okay"; 264}; 265 266&uart1 { 267 status = "okay"; 268}; 269 270/* ULPI SMSC USB3320 */ 271&usb0 { 272 status = "okay"; 273}; 274 275&dwc3_0 { 276 status = "okay"; 277 dr_mode = "host"; 278 snps,usb3_lpm_capable; 279 phy-names = "usb3-phy"; 280 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; 281 maximum-speed = "super-speed"; 282}; 283 284&watchdog0 { 285 status = "okay"; 286}; 287 288&xilinx_ams { 289 status = "okay"; 290}; 291 292&ams_ps { 293 status = "okay"; 294}; 295 296&ams_pl { 297 status = "okay"; 298}; 299