1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU111 4 * 5 * (C) Copyright 2017 - 2018, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/phy/phy.h> 17 18/ { 19 model = "ZynqMP ZCU111 RevA"; 20 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; 21 22 aliases { 23 ethernet0 = &gem3; 24 gpio0 = &gpio; 25 i2c0 = &i2c0; 26 i2c1 = &i2c1; 27 mmc0 = &sdhci1; 28 rtc0 = &rtc; 29 serial0 = &uart0; 30 serial1 = &dcc; 31 spi0 = &qspi; 32 usb0 = &usb0; 33 }; 34 35 chosen { 36 bootargs = "earlycon"; 37 stdout-path = "serial0:115200n8"; 38 xlnx,eeprom = &eeprom; 39 }; 40 41 memory@0 { 42 device_type = "memory"; 43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 44 /* Another 4GB connected to PL */ 45 }; 46 47 gpio-keys { 48 compatible = "gpio-keys"; 49 autorepeat; 50 sw19 { 51 label = "sw19"; 52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 53 linux,code = <KEY_DOWN>; 54 gpio-key,wakeup; 55 autorepeat; 56 }; 57 }; 58 59 leds { 60 compatible = "gpio-leds"; 61 heartbeat_led { 62 label = "heartbeat"; 63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 64 linux,default-trigger = "heartbeat"; 65 }; 66 }; 67 68 ina226-u67 { 69 compatible = "iio-hwmon"; 70 io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; 71 }; 72 ina226-u59 { 73 compatible = "iio-hwmon"; 74 io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; 75 }; 76 ina226-u61 { 77 compatible = "iio-hwmon"; 78 io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; 79 }; 80 ina226-u60 { 81 compatible = "iio-hwmon"; 82 io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; 83 }; 84 ina226-u64 { 85 compatible = "iio-hwmon"; 86 io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; 87 }; 88 ina226-u69 { 89 compatible = "iio-hwmon"; 90 io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; 91 }; 92 ina226-u66 { 93 compatible = "iio-hwmon"; 94 io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; 95 }; 96 ina226-u65 { 97 compatible = "iio-hwmon"; 98 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 99 }; 100 ina226-u63 { 101 compatible = "iio-hwmon"; 102 io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; 103 }; 104 ina226-u3 { 105 compatible = "iio-hwmon"; 106 io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; 107 }; 108 ina226-u71 { 109 compatible = "iio-hwmon"; 110 io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; 111 }; 112 ina226-u77 { 113 compatible = "iio-hwmon"; 114 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 115 }; 116 ina226-u73 { 117 compatible = "iio-hwmon"; 118 io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; 119 }; 120 ina226-u79 { 121 compatible = "iio-hwmon"; 122 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 123 }; 124}; 125 126&dcc { 127 status = "okay"; 128}; 129 130&fpd_dma_chan1 { 131 status = "okay"; 132}; 133 134&fpd_dma_chan2 { 135 status = "okay"; 136}; 137 138&fpd_dma_chan3 { 139 status = "okay"; 140}; 141 142&fpd_dma_chan4 { 143 status = "okay"; 144}; 145 146&fpd_dma_chan5 { 147 status = "okay"; 148}; 149 150&fpd_dma_chan6 { 151 status = "okay"; 152}; 153 154&fpd_dma_chan7 { 155 status = "okay"; 156}; 157 158&fpd_dma_chan8 { 159 status = "okay"; 160}; 161 162&gem3 { 163 status = "okay"; 164 phy-handle = <&phy0>; 165 phy-mode = "rgmii-id"; 166 phy0: ethernet-phy@c { 167 reg = <0xc>; 168 ti,rx-internal-delay = <0x8>; 169 ti,tx-internal-delay = <0xa>; 170 ti,fifo-depth = <0x1>; 171 ti,dp83867-rxctrl-strap-quirk; 172 }; 173}; 174 175&gpio { 176 status = "okay"; 177}; 178 179&gpu { 180 status = "okay"; 181}; 182 183&i2c0 { 184 status = "okay"; 185 clock-frequency = <400000>; 186 187 tca6416_u22: gpio@20 { 188 compatible = "ti,tca6416"; 189 reg = <0x20>; 190 gpio-controller; /* interrupt not connected */ 191 #gpio-cells = <2>; 192 /* 193 * IRQ not connected 194 * Lines: 195 * 0 - MAX6643_OT_B 196 * 1 - MAX6643_FANFAIL_B 197 * 2 - MIO26_PMU_INPUT_LS 198 * 4 - SFP_SI5382_INT_ALM 199 * 5 - IIC_MUX_RESET_B 200 * 6 - GEM3_EXP_RESET_B 201 * 10 - FMCP_HSPC_PRSNT_M2C_B 202 * 11 - CLK_SPI_MUX_SEL0 203 * 12 - CLK_SPI_MUX_SEL1 204 * 16 - IRPS5401_ALERT_B 205 * 17 - INA226_PMBUS_ALERT 206 * 3, 7, 13-15 - not connected 207 */ 208 }; 209 210 i2c-mux@75 { /* u23 */ 211 compatible = "nxp,pca9544"; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 reg = <0x75>; 215 i2c@0 { 216 #address-cells = <1>; 217 #size-cells = <0>; 218 reg = <0>; 219 /* PS_PMBUS */ 220 /* PMBUS_ALERT done via pca9544 */ 221 u67: ina226@40 { /* u67 */ 222 compatible = "ti,ina226"; 223 #io-channel-cells = <1>; 224 label = "ina226-u67"; 225 reg = <0x40>; 226 shunt-resistor = <2000>; 227 }; 228 u59: ina226@41 { /* u59 */ 229 compatible = "ti,ina226"; 230 #io-channel-cells = <1>; 231 label = "ina226-u59"; 232 reg = <0x41>; 233 shunt-resistor = <5000>; 234 }; 235 u61: ina226@42 { /* u61 */ 236 compatible = "ti,ina226"; 237 #io-channel-cells = <1>; 238 label = "ina226-u61"; 239 reg = <0x42>; 240 shunt-resistor = <5000>; 241 }; 242 u60: ina226@43 { /* u60 */ 243 compatible = "ti,ina226"; 244 #io-channel-cells = <1>; 245 label = "ina226-u60"; 246 reg = <0x43>; 247 shunt-resistor = <5000>; 248 }; 249 u64: ina226@45 { /* u64 */ 250 compatible = "ti,ina226"; 251 #io-channel-cells = <1>; 252 label = "ina226-u64"; 253 reg = <0x45>; 254 shunt-resistor = <5000>; 255 }; 256 u69: ina226@46 { /* u69 */ 257 compatible = "ti,ina226"; 258 #io-channel-cells = <1>; 259 label = "ina226-u69"; 260 reg = <0x46>; 261 shunt-resistor = <2000>; 262 }; 263 u66: ina226@47 { /* u66 */ 264 compatible = "ti,ina226"; 265 #io-channel-cells = <1>; 266 label = "ina226-u66"; 267 reg = <0x47>; 268 shunt-resistor = <5000>; 269 }; 270 u65: ina226@48 { /* u65 */ 271 compatible = "ti,ina226"; 272 #io-channel-cells = <1>; 273 label = "ina226-u65"; 274 reg = <0x48>; 275 shunt-resistor = <5000>; 276 }; 277 u63: ina226@49 { /* u63 */ 278 compatible = "ti,ina226"; 279 #io-channel-cells = <1>; 280 label = "ina226-u63"; 281 reg = <0x49>; 282 shunt-resistor = <5000>; 283 }; 284 u3: ina226@4a { /* u3 */ 285 compatible = "ti,ina226"; 286 #io-channel-cells = <1>; 287 label = "ina226-u3"; 288 reg = <0x4a>; 289 shunt-resistor = <5000>; 290 }; 291 u71: ina226@4b { /* u71 */ 292 compatible = "ti,ina226"; 293 #io-channel-cells = <1>; 294 label = "ina226-u71"; 295 reg = <0x4b>; 296 shunt-resistor = <5000>; 297 }; 298 u77: ina226@4c { /* u77 */ 299 compatible = "ti,ina226"; 300 #io-channel-cells = <1>; 301 label = "ina226-u77"; 302 reg = <0x4c>; 303 shunt-resistor = <5000>; 304 }; 305 u73: ina226@4d { /* u73 */ 306 compatible = "ti,ina226"; 307 #io-channel-cells = <1>; 308 label = "ina226-u73"; 309 reg = <0x4d>; 310 shunt-resistor = <5000>; 311 }; 312 u79: ina226@4e { /* u79 */ 313 compatible = "ti,ina226"; 314 #io-channel-cells = <1>; 315 label = "ina226-u79"; 316 reg = <0x4e>; 317 shunt-resistor = <5000>; 318 }; 319 }; 320 i2c@1 { 321 #address-cells = <1>; 322 #size-cells = <0>; 323 reg = <1>; 324 /* NC */ 325 }; 326 i2c@2 { 327 #address-cells = <1>; 328 #size-cells = <0>; 329 reg = <2>; 330 irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ 331 #clock-cells = <0>; 332 compatible = "infineon,irps5401"; 333 reg = <0x43>; 334 }; 335 irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ 336 #clock-cells = <0>; 337 compatible = "infineon,irps5401"; 338 reg = <0x44>; 339 }; 340 irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ 341 #clock-cells = <0>; 342 compatible = "infineon,irps5401"; 343 reg = <0x45>; 344 }; 345 /* u68 IR38064 +0 */ 346 /* u70 IR38060 +1 */ 347 /* u74 IR38060 +2 */ 348 /* u75 IR38060 +6 */ 349 /* J19 header too */ 350 351 }; 352 i2c@3 { 353 #address-cells = <1>; 354 #size-cells = <0>; 355 reg = <3>; 356 /* SYSMON */ 357 }; 358 }; 359}; 360 361&i2c1 { 362 status = "okay"; 363 clock-frequency = <400000>; 364 365 i2c-mux@74 { /* u26 */ 366 compatible = "nxp,pca9548"; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 reg = <0x74>; 370 i2c@0 { 371 #address-cells = <1>; 372 #size-cells = <0>; 373 reg = <0>; 374 /* 375 * IIC_EEPROM 1kB memory which uses 256B blocks 376 * where every block has different address. 377 * 0 - 256B address 0x54 378 * 256B - 512B address 0x55 379 * 512B - 768B address 0x56 380 * 768B - 1024B address 0x57 381 */ 382 eeprom: eeprom@54 { /* u88 */ 383 compatible = "atmel,24c08"; 384 reg = <0x54>; 385 }; 386 }; 387 i2c@1 { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 reg = <1>; 391 si5341: clock-generator@36 { /* SI5341 - u46 */ 392 compatible = "si5341"; 393 reg = <0x36>; 394 }; 395 396 }; 397 i2c@2 { 398 #address-cells = <1>; 399 #size-cells = <0>; 400 reg = <2>; 401 si570_1: clock-generator@5d { /* USER SI570 - u47 */ 402 #clock-cells = <0>; 403 compatible = "silabs,si570"; 404 reg = <0x5d>; 405 temperature-stability = <50>; 406 factory-fout = <300000000>; 407 clock-frequency = <300000000>; 408 clock-output-names = "si570_user"; 409 }; 410 }; 411 i2c@3 { 412 #address-cells = <1>; 413 #size-cells = <0>; 414 reg = <3>; 415 si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ 416 #clock-cells = <0>; 417 compatible = "silabs,si570"; 418 reg = <0x5d>; 419 temperature-stability = <50>; 420 factory-fout = <156250000>; 421 clock-frequency = <156250000>; 422 clock-output-names = "si570_mgt"; 423 }; 424 }; 425 i2c@4 { 426 #address-cells = <1>; 427 #size-cells = <0>; 428 reg = <4>; 429 si5328: clock-generator@69 { /* SI5328 - u48 */ 430 compatible = "silabs,si5328"; 431 reg = <0x69>; 432 }; 433 }; 434 i2c@5 { 435 #address-cells = <1>; 436 #size-cells = <0>; 437 reg = <5>; 438 sc18is603@2f { /* sc18is602 - u93 */ 439 compatible = "nxp,sc18is603"; 440 reg = <0x2f>; 441 /* 4 gpios for CS not handled by driver */ 442 /* 443 * USB2ANY cable or 444 * LMK04208 - u90 or 445 * LMX2594 - u102 or 446 * LMX2594 - u103 or 447 * LMX2594 - u104 448 */ 449 }; 450 }; 451 i2c@6 { 452 #address-cells = <1>; 453 #size-cells = <0>; 454 reg = <6>; 455 /* FMC connector */ 456 }; 457 /* 7 NC */ 458 }; 459 460 i2c-mux@75 { 461 compatible = "nxp,pca9548"; /* u27 */ 462 #address-cells = <1>; 463 #size-cells = <0>; 464 reg = <0x75>; 465 466 i2c@0 { 467 #address-cells = <1>; 468 #size-cells = <0>; 469 reg = <0>; 470 /* FMCP_HSPC_IIC */ 471 }; 472 i2c@1 { 473 #address-cells = <1>; 474 #size-cells = <0>; 475 reg = <1>; 476 /* NC */ 477 }; 478 i2c@2 { 479 #address-cells = <1>; 480 #size-cells = <0>; 481 reg = <2>; 482 /* SYSMON */ 483 }; 484 i2c@3 { 485 #address-cells = <1>; 486 #size-cells = <0>; 487 reg = <3>; 488 /* DDR4 SODIMM */ 489 }; 490 i2c@4 { 491 #address-cells = <1>; 492 #size-cells = <0>; 493 reg = <4>; 494 /* SFP3 */ 495 }; 496 i2c@5 { 497 #address-cells = <1>; 498 #size-cells = <0>; 499 reg = <5>; 500 /* SFP2 */ 501 }; 502 i2c@6 { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 reg = <6>; 506 /* SFP1 */ 507 }; 508 i2c@7 { 509 #address-cells = <1>; 510 #size-cells = <0>; 511 reg = <7>; 512 /* SFP0 */ 513 }; 514 }; 515}; 516 517&qspi { 518 status = "okay"; 519 is-dual = <1>; 520 flash@0 { 521 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 522 #address-cells = <1>; 523 #size-cells = <1>; 524 reg = <0x0>; 525 spi-tx-bus-width = <1>; 526 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 527 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 528 partition@qspi-fsbl-uboot { /* for testing purpose */ 529 label = "qspi-fsbl-uboot"; 530 reg = <0x0 0x100000>; 531 }; 532 partition@qspi-linux { /* for testing purpose */ 533 label = "qspi-linux"; 534 reg = <0x100000 0x500000>; 535 }; 536 partition@qspi-device-tree { /* for testing purpose */ 537 label = "qspi-device-tree"; 538 reg = <0x600000 0x20000>; 539 }; 540 partition@qspi-rootfs { /* for testing purpose */ 541 label = "qspi-rootfs"; 542 reg = <0x620000 0x5E0000>; 543 }; 544 }; 545}; 546 547&rtc { 548 status = "okay"; 549}; 550 551&sata { 552 status = "okay"; 553 /* SATA OOB timing settings */ 554 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 555 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 556 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 557 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 558 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 559 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 560 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 561 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 562 phy-names = "sata-phy"; 563 phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; 564}; 565 566/* SD1 with level shifter */ 567&sdhci1 { 568 status = "okay"; 569 no-1-8-v; 570 disable-wp; 571 xlnx,mio_bank = <1>; 572}; 573 574&serdes { 575 status = "okay"; 576}; 577 578&uart0 { 579 status = "okay"; 580}; 581 582/* ULPI SMSC USB3320 */ 583&usb0 { 584 status = "okay"; 585}; 586 587&dwc3_0 { 588 status = "okay"; 589 dr_mode = "host"; 590 snps,usb3_lpm_capable; 591 phy-names = "usb3-phy"; 592 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; 593}; 594