1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_RK3399_H 7 #define _ASM_ARCH_SDRAM_RK3399_H 8 #include <asm/arch-rockchip/sdram_common.h> 9 #include <asm/arch-rockchip/sdram_msch.h> 10 11 struct rk3399_ddr_pctl_regs { 12 u32 denali_ctl[332]; 13 }; 14 15 struct rk3399_ddr_publ_regs { 16 u32 denali_phy[959]; 17 }; 18 19 struct rk3399_ddr_pi_regs { 20 u32 denali_pi[200]; 21 }; 22 23 struct rk3399_ddr_cic_regs { 24 u32 cic_ctrl0; 25 u32 cic_ctrl1; 26 u32 cic_idle_th; 27 u32 cic_cg_wait_th; 28 u32 cic_status0; 29 u32 cic_status1; 30 u32 cic_ctrl2; 31 u32 cic_ctrl3; 32 u32 cic_ctrl4; 33 }; 34 35 /* DENALI_CTL_00 */ 36 #define START 1 37 38 /* DENALI_CTL_68 */ 39 #define PWRUP_SREFRESH_EXIT BIT(16) 40 41 /* DENALI_CTL_274 */ 42 #define MEM_RST_VALID 1 43 44 struct msch_regs { 45 u32 coreid; 46 u32 revisionid; 47 u32 ddrconf; 48 u32 ddrsize; 49 union noc_ddrtiminga0 ddrtiminga0; 50 union noc_ddrtimingb0 ddrtimingb0; 51 union noc_ddrtimingc0 ddrtimingc0; 52 union noc_devtodev0 devtodev0; 53 u32 reserved0[(0x110 - 0x20) / 4]; 54 union noc_ddrmode ddrmode; 55 u32 reserved1[(0x1000 - 0x114) / 4]; 56 u32 agingx0; 57 }; 58 59 struct sdram_msch_timings { 60 union noc_ddrtiminga0 ddrtiminga0; 61 union noc_ddrtimingb0 ddrtimingb0; 62 union noc_ddrtimingc0 ddrtimingc0; 63 union noc_devtodev0 devtodev0; 64 union noc_ddrmode ddrmode; 65 u32 agingx0; 66 }; 67 68 struct rk3399_sdram_channel { 69 struct sdram_cap_info cap_info; 70 struct sdram_msch_timings noc_timings; 71 }; 72 73 struct rk3399_sdram_params { 74 struct rk3399_sdram_channel ch[2]; 75 struct sdram_base_params base; 76 struct rk3399_ddr_pctl_regs pctl_regs; 77 struct rk3399_ddr_pi_regs pi_regs; 78 struct rk3399_ddr_publ_regs phy_regs; 79 }; 80 81 #define PI_CA_TRAINING BIT(0) 82 #define PI_WRITE_LEVELING BIT(1) 83 #define PI_READ_GATE_TRAINING BIT(2) 84 #define PI_READ_LEVELING BIT(3) 85 #define PI_WDQ_LEVELING BIT(4) 86 #define PI_FULL_TRAINING 0xff 87 88 enum { 89 STRIDE_128B = 0, 90 STRIDE_256B = 1, 91 STRIDE_512B = 2, 92 STRIDE_4KB = 3, 93 UN_STRIDE = 4, 94 PART_STRIDE = 5, 95 }; 96 97 #endif 98