1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2013 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 7 #ifndef _TEGRA124_SYSCTR_H_ 8 #define _TEGRA124_SYSCTR_H_ 9 10 struct sysctr_ctlr { 11 u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ 12 u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ 13 u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ 14 u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ 15 u32 reserved1[4]; /* 0x10 - 0x1C */ 16 u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ 17 u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ 18 u32 reserved2[1002]; /* 0x28 - 0xFCC */ 19 u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ 20 }; 21 22 #define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ 23 #define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ 24 25 #endif /* _TEGRA124_SYSCTR_H_ */ 26