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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2002
4  * Lineo, Inc. <www.lineo.com>
5  * Bernhard Kuhn <bkuhn@lineo.com>
6  *
7  * (C) Copyright 2002
8  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9  * Marius Groeger <mgroeger@sysgo.de>
10  *
11  * (C) Copyright 2002
12  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13  * Alex Zuepke <azu@sysgo.de>
14  */
15 
16 #include <common.h>
17 #include <time.h>
18 
19 #include <asm/io.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/at91_tc.h>
22 #include <asm/arch/clk.h>
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 /* the number of clocks per CONFIG_SYS_HZ */
27 #define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
28 
timer_init(void)29 int timer_init(void)
30 {
31 	at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
32 
33 	at91_periph_clk_enable(ATMEL_ID_TC0);
34 
35 	writel(0, &tc->bcr);
36 	writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
37 		AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
38 
39 	writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
40 	/* set to MCLK/2 and restart the timer
41 	when the value in TC_RC is reached */
42 	writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
43 
44 	writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
45 	writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
46 
47 	writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
48 	gd->arch.lastinc = 0;
49 	gd->arch.tbl = 0;
50 
51 	return 0;
52 }
53 
54 /*
55  * timer without interrupts
56  */
get_timer_raw(void)57 ulong get_timer_raw(void)
58 {
59 	at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
60 	u32 now;
61 
62 	now = readl(&tc->tc[0].cv) & 0x0000ffff;
63 
64 	if (now >= gd->arch.lastinc) {
65 		/* normal mode */
66 		gd->arch.tbl += now - gd->arch.lastinc;
67 	} else {
68 		/* we have an overflow ... */
69 		gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
70 	}
71 	gd->arch.lastinc = now;
72 
73 	return gd->arch.tbl;
74 }
75 
get_timer_masked(void)76 static ulong get_timer_masked(void)
77 {
78 	return get_timer_raw()/TIMER_LOAD_VAL;
79 }
80 
get_timer(ulong base)81 ulong get_timer(ulong base)
82 {
83 	return get_timer_masked() - base;
84 }
85 
__udelay(unsigned long usec)86 void __udelay(unsigned long usec)
87 {
88 	u32 tmo;
89 	u32 endtime;
90 	signed long diff;
91 
92 	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
93 	tmo *= usec;
94 	tmo /= 1000;
95 
96 	endtime = get_timer_raw() + tmo;
97 
98 	do {
99 		u32 now = get_timer_raw();
100 		diff = endtime - now;
101 	} while (diff >= 0);
102 }
103 
104 /*
105  * This function is derived from PowerPC code (read timebase as long long).
106  * On ARM it just returns the timer value.
107  */
get_ticks(void)108 unsigned long long get_ticks(void)
109 {
110 	return get_timer(0);
111 }
112 
113 /*
114  * This function is derived from PowerPC code (timebase clock frequency).
115  * On ARM it returns the number of timer ticks per second.
116  */
get_tbclk(void)117 ulong get_tbclk(void)
118 {
119 	return CONFIG_SYS_HZ;
120 }
121