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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
4  * Copyright (C) 2016 Grinn
5  */
6 
7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6ul_pins.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/gpio.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/io.h>
18 #include <common.h>
19 #include <fsl_esdhc_imx.h>
20 #include <linux/sizes.h>
21 #include <mmc.h>
22 
23 DECLARE_GLOBAL_DATA_PTR;
24 
25 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
26 	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
27 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
28 
dram_init(void)29 int dram_init(void)
30 {
31 	gd->ram_size = imx_ddr_size();
32 
33 	return 0;
34 }
35 
36 static iomux_v3_cfg_t const emmc_pads[] = {
37 	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
38 	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
39 	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
40 	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
41 	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
42 	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
43 	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
44 	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
45 	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
46 	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
47 
48 	/* RST_B */
49 	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
50 };
51 
52 #ifdef CONFIG_FSL_ESDHC_IMX
53 static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8};
54 
55 #define EMMC_PWR_GPIO	IMX_GPIO_NR(4, 10)
56 
litesom_mmc_init(bd_t * bis)57 int litesom_mmc_init(bd_t *bis)
58 {
59 	int ret;
60 
61 	/* eMMC */
62 	imx_iomux_v3_setup_multiple_pads(emmc_pads, ARRAY_SIZE(emmc_pads));
63 	gpio_direction_output(EMMC_PWR_GPIO, 0);
64 	udelay(500);
65 	gpio_direction_output(EMMC_PWR_GPIO, 1);
66 	emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
67 
68 	ret = fsl_esdhc_initialize(bis, &emmc_cfg);
69 	if (ret) {
70 		printf("Warning: failed to initialize mmc dev 1 (eMMC)\n");
71 		return ret;
72 	}
73 
74 	return 0;
75 }
76 #endif
77 
78 #ifdef CONFIG_SPL_BUILD
79 #include <linux/libfdt.h>
80 #include <spl.h>
81 #include <asm/arch/mx6-ddr.h>
82 
83 
84 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
85 	.grp_addds = 0x00000030,
86 	.grp_ddrmode_ctl = 0x00020000,
87 	.grp_b0ds = 0x00000030,
88 	.grp_ctlds = 0x00000030,
89 	.grp_b1ds = 0x00000030,
90 	.grp_ddrpke = 0x00000000,
91 	.grp_ddrmode = 0x00020000,
92 	.grp_ddr_type = 0x000c0000,
93 };
94 
95 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
96 	.dram_dqm0 = 0x00000030,
97 	.dram_dqm1 = 0x00000030,
98 	.dram_ras = 0x00000030,
99 	.dram_cas = 0x00000030,
100 	.dram_odt0 = 0x00000030,
101 	.dram_odt1 = 0x00000030,
102 	.dram_sdba2 = 0x00000000,
103 	.dram_sdclk_0 = 0x00000030,
104 	.dram_sdqs0 = 0x00000030,
105 	.dram_sdqs1 = 0x00000030,
106 	.dram_reset = 0x00000030,
107 };
108 
109 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
110 	.p0_mpwldectrl0 = 0x00000000,
111 	.p0_mpdgctrl0 = 0x41570155,
112 	.p0_mprddlctl = 0x4040474A,
113 	.p0_mpwrdlctl = 0x40405550,
114 };
115 
116 struct mx6_ddr_sysinfo ddr_sysinfo = {
117 	.dsize = 0,
118 	.cs_density = 20,
119 	.ncs = 1,
120 	.cs1_mirror = 0,
121 	.rtt_wr = 2,
122 	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
123 	.walat = 0,		/* Write additional latency */
124 	.ralat = 5,		/* Read additional latency */
125 	.mif3_mode = 3,		/* Command prediction working mode */
126 	.bi_on = 1,		/* Bank interleaving enabled */
127 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
128 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
129 	.ddr_type = DDR_TYPE_DDR3,
130 	.refsel = 0,		/* Refresh cycles at 64KHz */
131 	.refr = 1,		/* 2 refresh commands per refresh cycle */
132 };
133 
134 static struct mx6_ddr3_cfg mem_ddr = {
135 	.mem_speed = 800,
136 	.density = 4,
137 	.width = 16,
138 	.banks = 8,
139 	.rowaddr = 15,
140 	.coladdr = 10,
141 	.pagesz = 2,
142 	.trcd = 1375,
143 	.trcmin = 4875,
144 	.trasmin = 3500,
145 };
146 
ccgr_init(void)147 static void ccgr_init(void)
148 {
149 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
150 
151 	writel(0xFFFFFFFF, &ccm->CCGR0);
152 	writel(0xFFFFFFFF, &ccm->CCGR1);
153 	writel(0xFFFFFFFF, &ccm->CCGR2);
154 	writel(0xFFFFFFFF, &ccm->CCGR3);
155 	writel(0xFFFFFFFF, &ccm->CCGR4);
156 	writel(0xFFFFFFFF, &ccm->CCGR5);
157 	writel(0xFFFFFFFF, &ccm->CCGR6);
158 	writel(0xFFFFFFFF, &ccm->CCGR7);
159 }
160 
spl_dram_init(void)161 static void spl_dram_init(void)
162 {
163 	unsigned long ram_size;
164 
165 	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
166 	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
167 
168 	/*
169 	 * Get actual RAM size, so we can adjust DDR row size for <512M
170 	 * memories
171 	 */
172 	ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
173 	if (ram_size < SZ_512M) {
174 		mem_ddr.rowaddr = 14;
175 		mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
176 	}
177 }
178 
litesom_init_f(void)179 void litesom_init_f(void)
180 {
181 	ccgr_init();
182 
183 	/* setup AIPS and disable watchdog */
184 	arch_cpu_init();
185 
186 #ifdef CONFIG_BOARD_EARLY_INIT_F
187 	board_early_init_f();
188 #endif
189 
190 	/* setup GP timer */
191 	timer_init();
192 
193 	/* UART clocks enabled and gd valid - init serial console */
194 	preloader_console_init();
195 
196 	/* DDR initialization */
197 	spl_dram_init();
198 }
199 #endif
200