1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/mach-imx/dma.h>
12 #include <asm/mach-imx/hab.h>
13 #include <asm/mach-imx/rdc-sema.h>
14 #include <asm/arch/imx-rdc.h>
15 #include <asm/arch/crm_regs.h>
16 #include <dm.h>
17 #include <env.h>
18 #include <imx_thermal.h>
19 #include <fsl_sec.h>
20 #include <asm/setup.h>
21
22 #define IOMUXC_GPR1 0x4
23 #define BM_IOMUXC_GPR1_IRQ 0x1000
24
25 #define GPC_LPCR_A7_BSC 0x0
26 #define GPC_LPCR_M4 0x8
27 #define GPC_SLPCR 0x14
28 #define GPC_PGC_ACK_SEL_A7 0x24
29 #define GPC_IMR1_CORE0 0x30
30 #define GPC_IMR1_CORE1 0x40
31 #define GPC_IMR1_M4 0x50
32 #define GPC_PGC_CPU_MAPPING 0xec
33 #define GPC_PGC_C0_PUPSCR 0x804
34 #define GPC_PGC_SCU_TIMING 0x890
35 #define GPC_PGC_C1_PUPSCR 0x844
36
37 #define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
38 #define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
39 #define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
40 #define BM_SLPCR_EN_DSM 0x80000000
41 #define BM_SLPCR_RBC_EN 0x40000000
42 #define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
43 #define BM_SLPCR_VSTBY 0x4
44 #define BM_SLPCR_SBYOS 0x2
45 #define BM_SLPCR_BYPASS_PMIC_READY 0x1
46 #define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
47
48 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
49 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
50
51 #define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
52
53 #if defined(CONFIG_IMX_THERMAL)
54 static const struct imx_thermal_plat imx7_thermal_plat = {
55 .regs = (void *)ANATOP_BASE_ADDR,
56 .fuse_bank = 3,
57 .fuse_word = 3,
58 };
59
60 U_BOOT_DEVICE(imx7_thermal) = {
61 .name = "imx_thermal",
62 .platdata = &imx7_thermal_plat,
63 };
64 #endif
65
66 #if CONFIG_IS_ENABLED(IMX_RDC)
67 /*
68 * In current design, if any peripheral was assigned to both A7 and M4,
69 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
70 * low power mode. So M4 sleep will cause some peripherals fail to work
71 * at A7 core side. At default, all resources are in domain 0 - 3.
72 *
73 * There are 26 peripherals impacted by this IC issue:
74 * SIM2(sim2/emvsim2)
75 * SIM1(sim1/emvsim1)
76 * UART1/UART2/UART3/UART4/UART5/UART6/UART7
77 * SAI1/SAI2/SAI3
78 * WDOG1/WDOG2/WDOG3/WDOG4
79 * GPT1/GPT2/GPT3/GPT4
80 * PWM1/PWM2/PWM3/PWM4
81 * ENET1/ENET2
82 * Software Workaround:
83 * Here we setup some resources to domain 0 where M4 codes will move
84 * the M4 out of this domain. Then M4 is not able to access them any longer.
85 * This is a workaround for ic issue. So the peripherals are not shared
86 * by them. This way requires the uboot implemented the RDC driver and
87 * set the 26 IPs above to domain 0 only. M4 code will assign resource
88 * to its own domain, if it want to use the resource.
89 */
90 static rdc_peri_cfg_t const resources[] = {
91 (RDC_PER_SIM1 | RDC_DOMAIN(0)),
92 (RDC_PER_SIM2 | RDC_DOMAIN(0)),
93 (RDC_PER_UART1 | RDC_DOMAIN(0)),
94 (RDC_PER_UART2 | RDC_DOMAIN(0)),
95 (RDC_PER_UART3 | RDC_DOMAIN(0)),
96 (RDC_PER_UART4 | RDC_DOMAIN(0)),
97 (RDC_PER_UART5 | RDC_DOMAIN(0)),
98 (RDC_PER_UART6 | RDC_DOMAIN(0)),
99 (RDC_PER_UART7 | RDC_DOMAIN(0)),
100 (RDC_PER_SAI1 | RDC_DOMAIN(0)),
101 (RDC_PER_SAI2 | RDC_DOMAIN(0)),
102 (RDC_PER_SAI3 | RDC_DOMAIN(0)),
103 (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
104 (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
105 (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
106 (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
107 (RDC_PER_GPT1 | RDC_DOMAIN(0)),
108 (RDC_PER_GPT2 | RDC_DOMAIN(0)),
109 (RDC_PER_GPT3 | RDC_DOMAIN(0)),
110 (RDC_PER_GPT4 | RDC_DOMAIN(0)),
111 (RDC_PER_PWM1 | RDC_DOMAIN(0)),
112 (RDC_PER_PWM2 | RDC_DOMAIN(0)),
113 (RDC_PER_PWM3 | RDC_DOMAIN(0)),
114 (RDC_PER_PWM4 | RDC_DOMAIN(0)),
115 (RDC_PER_ENET1 | RDC_DOMAIN(0)),
116 (RDC_PER_ENET2 | RDC_DOMAIN(0)),
117 };
118
isolate_resource(void)119 static void isolate_resource(void)
120 {
121 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
122 }
123 #endif
124
125 #if defined(CONFIG_IMX_HAB)
126 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
127 .bank = 1,
128 .word = 3,
129 };
130 #endif
131
is_mx7d(void)132 static bool is_mx7d(void)
133 {
134 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
135 struct fuse_bank *bank = &ocotp->bank[1];
136 struct fuse_bank1_regs *fuse =
137 (struct fuse_bank1_regs *)bank->fuse_regs;
138 int val;
139
140 val = readl(&fuse->tester4);
141 if (val & 1)
142 return false;
143 else
144 return true;
145 }
146
get_cpu_rev(void)147 u32 get_cpu_rev(void)
148 {
149 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
150 ANATOP_BASE_ADDR;
151 u32 reg = readl(&ccm_anatop->digprog);
152 u32 type = (reg >> 16) & 0xff;
153
154 if (!is_mx7d())
155 type = MXC_CPU_MX7S;
156
157 reg &= 0xff;
158 return (type << 12) | reg;
159 }
160
161 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)162 u32 __weak get_board_rev(void)
163 {
164 return get_cpu_rev();
165 }
166 #endif
167
imx_enet_mdio_fixup(void)168 static void imx_enet_mdio_fixup(void)
169 {
170 struct iomuxc_gpr_base_regs *gpr_regs =
171 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
172
173 /*
174 * The management data input/output (MDIO) requires open-drain,
175 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
176 * this feature. So to TO1.1, need to enable open drain by setting
177 * bits GPR0[8:7].
178 */
179
180 if (soc_rev() >= CHIP_REV_1_1) {
181 setbits_le32(&gpr_regs->gpr[0],
182 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
183 }
184 }
185
init_cpu_basic(void)186 static void init_cpu_basic(void)
187 {
188 imx_enet_mdio_fixup();
189
190 #ifdef CONFIG_APBH_DMA
191 /* Start APBH DMA */
192 mxs_dma_init();
193 #endif
194 }
195
196 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
197 /* enable all periherial can be accessed in nosec mode */
init_csu(void)198 static void init_csu(void)
199 {
200 int i = 0;
201
202 for (i = 0; i < CSU_NUM_REGS; i++)
203 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
204 }
205
imx_gpcv2_init(void)206 static void imx_gpcv2_init(void)
207 {
208 u32 val, i;
209
210 /*
211 * Force IOMUXC irq pending, so that the interrupt to GPC can be
212 * used to deassert dsm_request signal when the signal gets
213 * asserted unexpectedly.
214 */
215 val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
216 val |= BM_IOMUXC_GPR1_IRQ;
217 writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
218
219 /* Initially mask all interrupts */
220 for (i = 0; i < 4; i++) {
221 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
222 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
223 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
224 }
225
226 /* set SCU timing */
227 writel((0x59 << 10) | 0x5B | (0x2 << 20),
228 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
229
230 /* only external IRQs to wake up LPM and core 0/1 */
231 val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
232 val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
233 writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
234
235 /* set C0 power up timming per design requirement */
236 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
237 val &= ~BM_GPC_PGC_CORE_PUPSCR;
238 val |= (0x1A << 7);
239 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
240
241 /* set C1 power up timming per design requirement */
242 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
243 val &= ~BM_GPC_PGC_CORE_PUPSCR;
244 val |= (0x1A << 7);
245 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
246
247 /* dummy ack for time slot by default */
248 writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
249 BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
250 GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
251
252 /* mask M4 DSM trigger */
253 writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
254 BM_LPCR_M4_MASK_DSM_TRIGGER,
255 GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
256
257 /* set mega/fast mix in A7 domain */
258 writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
259
260 /* DSM related settings */
261 val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
262 val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
263 BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
264 BM_SLPCR_REG_BYPASS_COUNT);
265 val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
266 writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
267
268 /*
269 * disabling RBC need to delay at least 2 cycles of CKIL(32K)
270 * due to hardware design requirement, which is
271 * ~61us, here we use 65us for safe
272 */
273 udelay(65);
274 }
275
arch_cpu_init(void)276 int arch_cpu_init(void)
277 {
278 init_aips();
279
280 init_csu();
281 /* Disable PDE bit of WMCR register */
282 imx_wdog_disable_powerdown();
283
284 init_cpu_basic();
285
286 #if CONFIG_IS_ENABLED(IMX_RDC)
287 isolate_resource();
288 #endif
289
290 init_snvs();
291
292 imx_gpcv2_init();
293
294 return 0;
295 }
296 #else
arch_cpu_init(void)297 int arch_cpu_init(void)
298 {
299 init_cpu_basic();
300
301 return 0;
302 }
303 #endif
304
305 #ifdef CONFIG_ARCH_MISC_INIT
arch_misc_init(void)306 int arch_misc_init(void)
307 {
308 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
309 if (is_mx7d())
310 env_set("soc", "imx7d");
311 else
312 env_set("soc", "imx7s");
313 #endif
314
315 #ifdef CONFIG_FSL_CAAM
316 sec_init();
317 #endif
318
319 return 0;
320 }
321 #endif
322
323 #ifdef CONFIG_SERIAL_TAG
324 /*
325 * OCOTP_TESTER
326 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
327 * OCOTP_TESTER describes a unique ID based on silicon wafer
328 * and die X/Y position
329 *
330 * OCOTOP_TESTER offset 0x410
331 * 31:0 fuse 0
332 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
333 *
334 * OCOTP_TESTER1 offset 0x420
335 * 31:24 fuse 1
336 * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
337 * 23:16 fuse 1
338 * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
339 * 15:11 fuse 1
340 * The wafer number of the wafer on which the device was fabricated/SJC
341 * CHALLENGE/ Unique ID
342 * 10:0 fuse 1
343 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
344 */
get_board_serial(struct tag_serialnr * serialnr)345 void get_board_serial(struct tag_serialnr *serialnr)
346 {
347 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
348 struct fuse_bank *bank = &ocotp->bank[0];
349 struct fuse_bank0_regs *fuse =
350 (struct fuse_bank0_regs *)bank->fuse_regs;
351
352 serialnr->low = fuse->tester0;
353 serialnr->high = fuse->tester1;
354 }
355 #endif
356
set_wdog_reset(struct wdog_regs * wdog)357 void set_wdog_reset(struct wdog_regs *wdog)
358 {
359 u32 reg = readw(&wdog->wcr);
360 /*
361 * Output WDOG_B signal to reset external pmic or POR_B decided by
362 * the board desgin. Without external reset, the peripherals/DDR/
363 * PMIC are not reset, that may cause system working abnormal.
364 */
365 reg = readw(&wdog->wcr);
366 reg |= 1 << 3;
367 /*
368 * WDZST bit is write-once only bit. Align this bit in kernel,
369 * otherwise kernel code will have no chance to set this bit.
370 */
371 reg |= 1 << 0;
372 writew(reg, &wdog->wcr);
373 }
374
s_init(void)375 void s_init(void)
376 {
377 /* clock configuration. */
378 clock_init();
379
380 return;
381 }
382
reset_misc(void)383 void reset_misc(void)
384 {
385 #ifndef CONFIG_SPL_BUILD
386 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
387 lcdif_power_down();
388 #endif
389 #endif
390 }
391
392