1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 */
5 #include <init.h>
6 #include <asm/io.h>
7 #include <asm/arch/clock.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/mach-imx/boot_mode.h>
11 #include <asm/mach-imx/hab.h>
12
13 #define PMC0_BASE_ADDR 0x410a1000
14 #define PMC0_CTRL 0x28
15 #define PMC0_CTRL_LDOEN BIT(31)
16 #define PMC0_CTRL_LDOOKDIS BIT(30)
17 #define PMC0_CTRL_PMC1ON BIT(24)
18 #define PMC1_BASE_ADDR 0x40400000
19 #define PMC1_RUN 0x8
20 #define PMC1_STOP 0x10
21 #define PMC1_VLPS 0x14
22 #define PMC1_LDOVL_SHIFT 16
23 #define PMC1_LDOVL_MASK (0x3f << PMC1_LDOVL_SHIFT)
24 #define PMC1_LDOVL_900 0x1e
25 #define PMC1_LDOVL_950 0x23
26 #define PMC1_STATUS 0x20
27 #define PMC1_STATUS_LDOVLF BIT(8)
28
29 static char *get_reset_cause(char *);
30
31 #if defined(CONFIG_IMX_HAB)
32 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
33 .bank = 29,
34 .word = 6,
35 };
36 #endif
37
38 #define ROM_VERSION_ADDR 0x80
get_cpu_rev(void)39 u32 get_cpu_rev(void)
40 {
41 /* Check the ROM version for cpu revision */
42 u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR);
43
44 return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF);
45 }
46
47 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)48 u32 __weak get_board_rev(void)
49 {
50 return get_cpu_rev();
51 }
52 #endif
53
get_boot_mode(void)54 enum bt_mode get_boot_mode(void)
55 {
56 u32 bt0_cfg = 0;
57
58 bt0_cfg = readl(CMC0_RBASE + 0x40);
59 bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
60
61 if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
62 /* No low power boot */
63 if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
64 return DUAL_BOOT;
65 else
66 return SINGLE_BOOT;
67 }
68
69 return LOW_POWER_BOOT;
70 }
71
arch_cpu_init(void)72 int arch_cpu_init(void)
73 {
74 return 0;
75 }
76
77 #ifdef CONFIG_BOARD_POSTCLK_INIT
board_postclk_init(void)78 int board_postclk_init(void)
79 {
80 return 0;
81 }
82 #endif
83
84 #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
85 #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
86 #define REFRESH_WORD0 0xA602 /* 1st refresh word */
87 #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
88
disable_wdog(u32 wdog_base)89 static void disable_wdog(u32 wdog_base)
90 {
91 writel(UNLOCK_WORD0, (wdog_base + 0x04));
92 writel(UNLOCK_WORD1, (wdog_base + 0x04));
93 writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
94 writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
95 writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
96
97 writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
98 writel(REFRESH_WORD1, (wdog_base + 0x04));
99 }
100
init_wdog(void)101 void init_wdog(void)
102 {
103 /*
104 * ROM will configure WDOG1, disable it or enable it
105 * depending on FUSE. The update bit is set for reconfigurable.
106 * We have to use unlock sequence to reconfigure it.
107 * WDOG2 is not touched by ROM, so it will have default value
108 * which is enabled. We can directly configure it.
109 * To simplify the codes, we still use same reconfigure
110 * process as WDOG1. Because the update bit is not set for
111 * WDOG2, the unlock sequence won't take effect really.
112 * It actually directly configure the wdog.
113 * In this function, we will disable both WDOG1 and WDOG2,
114 * and set update bit for both. So that kernel can reconfigure them.
115 */
116 disable_wdog(WDG1_RBASE);
117 disable_wdog(WDG2_RBASE);
118 }
119
120 #if defined(CONFIG_LDO_ENABLED_MODE)
init_ldo_mode(void)121 static void init_ldo_mode(void)
122 {
123 unsigned int reg;
124
125 /* Set LDOOKDIS */
126 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
127
128 /* Set LDOVL to 0.95V in PMC1_RUN */
129 reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
130 reg &= ~PMC1_LDOVL_MASK;
131 reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
132 writel(PMC1_BASE_ADDR + PMC1_RUN, reg);
133
134 /* Wait for LDOVLF to be cleared */
135 reg = readl(PMC1_BASE_ADDR + PMC1_STATUS);
136 while (reg & PMC1_STATUS_LDOVLF)
137 ;
138
139 /* Set LDOVL to 0.95V in PMC1_STOP */
140 reg = readl(PMC1_BASE_ADDR + PMC1_STOP);
141 reg &= ~PMC1_LDOVL_MASK;
142 reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
143 writel(PMC1_BASE_ADDR + PMC1_STOP, reg);
144
145 /* Set LDOVL to 0.90V in PMC1_VLPS */
146 reg = readl(PMC1_BASE_ADDR + PMC1_VLPS);
147 reg &= ~PMC1_LDOVL_MASK;
148 reg |= (PMC1_LDOVL_900 << PMC1_LDOVL_SHIFT);
149 writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
150
151 /* Set LDOEN bit */
152 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
153
154 /* Set the PMC1ON bit */
155 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
156 }
157 #endif
158
s_init(void)159 void s_init(void)
160 {
161 /* Disable wdog */
162 init_wdog();
163
164 /* clock configuration. */
165 clock_init();
166
167 if (soc_rev() < CHIP_REV_2_0) {
168 /* enable dumb pmic */
169 writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
170 }
171
172 #if defined(CONFIG_LDO_ENABLED_MODE)
173 init_ldo_mode();
174 #endif
175 return;
176 }
177
178 #ifndef CONFIG_ULP_WATCHDOG
reset_cpu(ulong addr)179 void reset_cpu(ulong addr)
180 {
181 setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
182 while (1)
183 ;
184 }
185 #endif
186
187 #if defined(CONFIG_DISPLAY_CPUINFO)
get_imx_type(u32 imxtype)188 const char *get_imx_type(u32 imxtype)
189 {
190 return "7ULP";
191 }
192
193 #define PMC0_BASE_ADDR 0x410a1000
194 #define PMC0_CTRL 0x28
195 #define PMC0_CTRL_LDOEN BIT(31)
196
ldo_mode_is_enabled(void)197 static bool ldo_mode_is_enabled(void)
198 {
199 unsigned int reg;
200
201 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
202 if (reg & PMC0_CTRL_LDOEN)
203 return true;
204 else
205 return false;
206 }
207
print_cpuinfo(void)208 int print_cpuinfo(void)
209 {
210 u32 cpurev;
211 char cause[18];
212
213 cpurev = get_cpu_rev();
214
215 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
216 get_imx_type((cpurev & 0xFF000) >> 12),
217 (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
218 mxc_get_clock(MXC_ARM_CLK) / 1000000);
219
220 printf("Reset cause: %s\n", get_reset_cause(cause));
221
222 printf("Boot mode: ");
223 switch (get_boot_mode()) {
224 case LOW_POWER_BOOT:
225 printf("Low power boot\n");
226 break;
227 case DUAL_BOOT:
228 printf("Dual boot\n");
229 break;
230 case SINGLE_BOOT:
231 default:
232 printf("Single boot\n");
233 break;
234 }
235
236 if (ldo_mode_is_enabled())
237 printf("PMC1: LDO enabled mode\n");
238 else
239 printf("PMC1: LDO bypass mode\n");
240
241 return 0;
242 }
243 #endif
244
245 #define CMC_SRS_TAMPER (1 << 31)
246 #define CMC_SRS_SECURITY (1 << 30)
247 #define CMC_SRS_TZWDG (1 << 29)
248 #define CMC_SRS_JTAG_RST (1 << 28)
249 #define CMC_SRS_CORE1 (1 << 16)
250 #define CMC_SRS_LOCKUP (1 << 15)
251 #define CMC_SRS_SW (1 << 14)
252 #define CMC_SRS_WDG (1 << 13)
253 #define CMC_SRS_PIN_RESET (1 << 8)
254 #define CMC_SRS_WARM (1 << 4)
255 #define CMC_SRS_HVD (1 << 3)
256 #define CMC_SRS_LVD (1 << 2)
257 #define CMC_SRS_POR (1 << 1)
258 #define CMC_SRS_WUP (1 << 0)
259
260 static u32 reset_cause = -1;
261
get_reset_cause(char * ret)262 static char *get_reset_cause(char *ret)
263 {
264 u32 cause1, cause = 0, srs = 0;
265 u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
266 u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
267
268 if (!ret)
269 return "null";
270
271 srs = readl(reg_srs);
272 cause1 = readl(reg_ssrs);
273 writel(cause1, reg_ssrs);
274
275 reset_cause = cause1;
276
277 cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
278
279 switch (cause) {
280 case CMC_SRS_POR:
281 sprintf(ret, "%s", "POR");
282 break;
283 case CMC_SRS_WUP:
284 sprintf(ret, "%s", "WUP");
285 break;
286 case CMC_SRS_WARM:
287 cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
288 CMC_SRS_JTAG_RST);
289 switch (cause) {
290 case CMC_SRS_WDG:
291 sprintf(ret, "%s", "WARM-WDG");
292 break;
293 case CMC_SRS_SW:
294 sprintf(ret, "%s", "WARM-SW");
295 break;
296 case CMC_SRS_JTAG_RST:
297 sprintf(ret, "%s", "WARM-JTAG");
298 break;
299 default:
300 sprintf(ret, "%s", "WARM-UNKN");
301 break;
302 }
303 break;
304 default:
305 sprintf(ret, "%s-%X", "UNKN", cause1);
306 break;
307 }
308
309 debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
310 return ret;
311 }
312
313 #ifdef CONFIG_ENV_IS_IN_MMC
board_mmc_get_env_dev(int devno)314 __weak int board_mmc_get_env_dev(int devno)
315 {
316 return CONFIG_SYS_MMC_ENV_DEV;
317 }
318
mmc_get_env_dev(void)319 int mmc_get_env_dev(void)
320 {
321 int devno = 0;
322 u32 bt1_cfg = 0;
323
324 /* If not boot from sd/mmc, use default value */
325 if (get_boot_mode() == LOW_POWER_BOOT)
326 return CONFIG_SYS_MMC_ENV_DEV;
327
328 bt1_cfg = readl(CMC1_RBASE + 0x40);
329 devno = (bt1_cfg >> 9) & 0x7;
330
331 return board_mmc_get_env_dev(devno);
332 }
333 #endif
334
get_boot_device(void)335 enum boot_device get_boot_device(void)
336 {
337 struct bootrom_sw_info **p =
338 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
339
340 enum boot_device boot_dev = SD1_BOOT;
341 u8 boot_type = (*p)->boot_dev_type;
342 u8 boot_instance = (*p)->boot_dev_instance;
343
344 switch (boot_type) {
345 case BOOT_TYPE_SD:
346 boot_dev = boot_instance + SD1_BOOT;
347 break;
348 case BOOT_TYPE_MMC:
349 boot_dev = boot_instance + MMC1_BOOT;
350 break;
351 case BOOT_TYPE_USB:
352 boot_dev = USB_BOOT;
353 break;
354 default:
355 break;
356 }
357
358 return boot_dev;
359 }
360