1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 MediaTek Inc.
4 * Copyright (C) 2019 BayLibre, SAS
5 * Author: Fabien Parent <fparent@baylibre.com>
6 */
7
8 #include <clk.h>
9 #include <common.h>
10 #include <dm.h>
11 #include <fdtdec.h>
12 #include <ram.h>
13 #include <asm/arch/misc.h>
14 #include <asm/armv8/mmu.h>
15 #include <asm/sections.h>
16 #include <dm/uclass.h>
17 #include <dt-bindings/clock/mt8516-clk.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
dram_init(void)21 int dram_init(void)
22 {
23 int ret;
24
25 ret = fdtdec_setup_memory_banksize();
26 if (ret)
27 return ret;
28
29 return fdtdec_setup_mem_size_base();
30 }
31
dram_init_banksize(void)32 int dram_init_banksize(void)
33 {
34 gd->bd->bi_dram[0].start = gd->ram_base;
35 gd->bd->bi_dram[0].size = gd->ram_size;
36
37 return 0;
38 }
39
mtk_pll_early_init(void)40 int mtk_pll_early_init(void)
41 {
42 unsigned long pll_rates[] = {
43 [CLK_APMIXED_ARMPLL] = 1300000000,
44 [CLK_APMIXED_MAINPLL] = 1501000000,
45 [CLK_APMIXED_UNIVPLL] = 1248000000,
46 [CLK_APMIXED_MMPLL] = 380000000,
47 };
48 struct udevice *dev;
49 int ret, i;
50
51 ret = uclass_get_device_by_driver(UCLASS_CLK,
52 DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
53 if (ret)
54 return ret;
55
56 /* configure default rate then enable apmixedsys */
57 for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
58 struct clk clk = { .id = i, .dev = dev };
59
60 ret = clk_set_rate(&clk, pll_rates[i]);
61 if (ret)
62 return ret;
63
64 ret = clk_enable(&clk);
65 if (ret)
66 return ret;
67 }
68
69 return 0;
70 }
71
mtk_soc_early_init(void)72 int mtk_soc_early_init(void)
73 {
74 int ret;
75
76 /* initialize early clocks */
77 ret = mtk_pll_early_init();
78 if (ret)
79 return ret;
80
81 return 0;
82 }
83
reset_cpu(ulong addr)84 void reset_cpu(ulong addr)
85 {
86 psci_system_reset();
87 }
88
print_cpuinfo(void)89 int print_cpuinfo(void)
90 {
91 printf("CPU: MediaTek MT8516\n");
92 return 0;
93 }
94
95 static struct mm_region mt8516_mem_map[] = {
96 {
97 /* DDR */
98 .virt = 0x40000000UL,
99 .phys = 0x40000000UL,
100 .size = 0x20000000UL,
101 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
102 }, {
103 .virt = 0x00000000UL,
104 .phys = 0x00000000UL,
105 .size = 0x20000000UL,
106 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
107 PTE_BLOCK_NON_SHARE |
108 PTE_BLOCK_PXN | PTE_BLOCK_UXN
109 }, {
110 0,
111 }
112 };
113 struct mm_region *mem_map = mt8516_mem_map;
114