1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 * 7 * Header file for the Marvell's Feroceon CPU core. 8 */ 9 10 #ifndef _MVEBU_SOC_H 11 #define _MVEBU_SOC_H 12 13 #define SOC_MV78230_ID 0x7823 14 #define SOC_MV78260_ID 0x7826 15 #define SOC_MV78460_ID 0x7846 16 #define SOC_88F6720_ID 0x6720 17 #define SOC_88F6810_ID 0x6810 18 #define SOC_88F6820_ID 0x6820 19 #define SOC_88F6828_ID 0x6828 20 #define SOC_98DX3236_ID 0xf410 21 #define SOC_98DX3336_ID 0xf400 22 #define SOC_98DX4251_ID 0xfc00 23 24 /* A375 revisions */ 25 #define MV_88F67XX_A0_ID 0x3 26 27 /* A38x revisions */ 28 #define MV_88F68XX_Z1_ID 0x0 29 #define MV_88F68XX_A0_ID 0x4 30 #define MV_88F68XX_B0_ID 0xa 31 32 /* TCLK Core Clock definition */ 33 #ifndef CONFIG_SYS_TCLK 34 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 35 #endif 36 37 /* SOC specific definations */ 38 #define INTREG_BASE 0xd0000000 39 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) 40 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700) 41 /* 42 * The SPL U-Boot version still runs with the default 43 * address for the internal registers, configured by 44 * the BootROM. Only the main U-Boot version uses the 45 * new internal register base address, that also is 46 * required for the Linux kernel. 47 */ 48 #define SOC_REGS_PHY_BASE 0xd0000000 49 #elif defined(CONFIG_ARMADA_8K) 50 #define SOC_REGS_PHY_BASE 0xf0000000 51 #else 52 #define SOC_REGS_PHY_BASE 0xf1000000 53 #endif 54 #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x) 55 56 #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) 57 #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) 58 #define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE 59 #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) 60 #define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100)) 61 #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) 62 #define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) 63 #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) 64 #define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180)) 65 #define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200)) 66 #define MVEBU_CLOCK_BASE (MVEBU_REGISTER(0x18700)) 67 #define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000)) 68 #define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180)) 69 #define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300)) 70 #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) 71 #define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000)) 72 #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) 73 #define MVEBU_REG_PCIE0_BASE (MVEBU_REGISTER(0x80000)) 74 #define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000)) 75 #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) 76 #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) 77 #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) 78 #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000)) 79 #ifdef CONFIG_ARMADA_MSYS 80 #define MVEBU_DFX_BASE (MBUS_DFX_BASE) 81 #else 82 #define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000)) 83 #endif 84 85 #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200)) 86 #define MBUS_ERR_PROP_EN (1 << 8) 87 88 #define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250)) 89 #define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254)) 90 91 #define MVEBU_SOC_DEV_MUX_REG (MVEBU_SYSTEM_REG_BASE + 0x08) 92 #define NAND_EN BIT(0) 93 #define NAND_ARBITER_EN BIT(27) 94 95 #define ARMADA_XP_PUP_ENABLE (MVEBU_SYSTEM_REG_BASE + 0x44c) 96 #define GE0_PUP_EN BIT(0) 97 #define GE1_PUP_EN BIT(1) 98 #define LCD_PUP_EN BIT(2) 99 #define NAND_PUP_EN BIT(4) 100 #define SPI_PUP_EN BIT(5) 101 102 #define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8)) 103 #ifdef CONFIG_ARMADA_MSYS 104 #define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4)) 105 #define NAND_ECC_DIVCKL_RATIO_OFFS 6 106 #define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS) 107 #else 108 #define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4)) 109 #endif 110 #ifdef CONFIG_ARMADA_MSYS 111 #define NAND_ECC_DIVCKL_RATIO_OFFS 6 112 #define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS) 113 #else 114 #define NAND_ECC_DIVCKL_RATIO_OFFS 8 115 #define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS) 116 #endif 117 118 #define SDRAM_MAX_CS 4 119 #define SDRAM_ADDR_MASK 0xFF000000 120 121 /* MVEBU CPU memory windows */ 122 #define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA 123 #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE 124 #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE 125 126 #define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) 127 128 /* BootROM error register (also includes some status infos) */ 129 #define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) 130 #define BOOTROM_ERR_MODE_OFFS 28 131 #define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) 132 #define BOOTROM_ERR_MODE_UART 0x6 133 #define BOOTROM_ERR_CODE_OFFS 0 134 #define BOOTROM_ERR_CODE_MASK (0xf << BOOTROM_ERR_CODE_OFFS) 135 136 #if defined(CONFIG_ARMADA_375) 137 /* SAR values for Armada 375 */ 138 #define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200)) 139 #define CONFIG_SAR2_REG (MVEBU_REGISTER(0xe8204)) 140 141 #define SAR_CPU_FREQ_OFFS 17 142 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) 143 144 #define BOOT_DEV_SEL_OFFS 3 145 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) 146 147 #define BOOT_FROM_UART 0x30 148 #define BOOT_FROM_SPI 0x38 149 #elif defined(CONFIG_ARMADA_38X) 150 /* SAR values for Armada 38x */ 151 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) 152 153 #define SAR_CPU_FREQ_OFFS 10 154 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) 155 #define SAR_BOOT_DEVICE_OFFS 4 156 #define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) 157 158 #define BOOT_DEV_SEL_OFFS 4 159 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) 160 161 #define BOOT_FROM_NAND 0x0A 162 #define BOOT_FROM_SATA 0x22 163 #define BOOT_FROM_UART 0x28 164 #define BOOT_FROM_SATA_ALT 0x2A 165 #define BOOT_FROM_UART_ALT 0x3f 166 #define BOOT_FROM_SPI 0x32 167 #define BOOT_FROM_MMC 0x30 168 #define BOOT_FROM_MMC_ALT 0x31 169 #elif defined(CONFIG_ARMADA_MSYS) 170 /* SAR values for MSYS */ 171 #define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) 172 #define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) 173 174 #define SAR_CPU_FREQ_OFFS 18 175 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) 176 #define SAR_BOOT_DEVICE_OFFS 11 177 #define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS) 178 179 #define BOOT_DEV_SEL_OFFS 11 180 #define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS) 181 182 #define BOOT_FROM_NAND 0x1 183 #define BOOT_FROM_UART 0x2 184 #define BOOT_FROM_SPI 0x3 185 #else 186 /* SAR values for Armada XP */ 187 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) 188 #define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) 189 190 #define SAR_CPU_FREQ_OFFS 21 191 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) 192 #define SAR_FFC_FREQ_OFFS 24 193 #define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) 194 #define SAR2_CPU_FREQ_OFFS 20 195 #define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) 196 #define SAR_BOOT_DEVICE_OFFS 5 197 #define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS) 198 199 #define BOOT_DEV_SEL_OFFS 5 200 #define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS) 201 202 #define BOOT_FROM_UART 0x2 203 #define BOOT_FROM_SPI 0x3 204 #endif 205 206 #endif /* _MVEBU_SOC_H */ 207